| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * f32k_clk_hw.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Maui_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file is intended for F32K_CLK driver. |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
| 58 | * removed! |
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| 102 | * |
| 103 | *------------------------------------------------------------------------------ |
| 104 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 105 | *============================================================================ |
| 106 | ****************************************************************************/ |
| 107 | #ifndef F32K_CLK_HW_H |
| 108 | #define F32K_CLK_HW_H |
| 109 | |
| 110 | #include "drv_features_f32k.h" |
| 111 | #include "reg_base.h" |
| 112 | |
| 113 | #if !defined(DRV_F32K_CLK_OFF) |
| 114 | #if defined(DRV_F32K_FQMTR_AS_6255) |
| 115 | #define FQMTR_BASE (PLL_base+0x0000) |
| 116 | #define FQMTR_CON0 (PLL_base+0x1080) |
| 117 | #define FQMTR_CON1 (PLL_base+0x1084) |
| 118 | #define FQMTR_CON2 (PLL_base+0x1088) |
| 119 | #define FQMTR_CON3 (PLL_base+0x108c) |
| 120 | #define FQMTR_CON4 (PLL_base+0x1090) |
| 121 | #elif defined(DRV_F32K_FQMTR_AS_6250) |
| 122 | #define FQMTR_CON0 (PMU_base+0x0ff0) |
| 123 | #define FQMTR_CON1 (PMU_base+0x0ff4) |
| 124 | #define FQMTR_CON2 (PMU_base+0x0ff8) |
| 125 | #define FQMTR_CON3 (PMU_base+0x0ffc) |
| 126 | #elif defined(DRV_F32K_FQMTR_AS_6280) |
| 127 | #define FQMTR_CON0 (MIX_ABB_base+0x0400) |
| 128 | #define FQMTR_CON1 (MIX_ABB_base+0x0404) |
| 129 | #define FQMTR_CON2 (MIX_ABB_base+0x0408) |
| 130 | #define FQMTR_CON3 (MIX_ABB_base+0x040C) |
| 131 | #endif |
| 132 | |
| 133 | #if defined(DRV_F32K_SWITCH_32K) |
| 134 | #define F32K_MD_CHIP_STATUS (CONFIG_base+0x0018) |
| 135 | #define F32K_AP_F32K_SEL (AP_CONFIG_base+0x000c) |
| 136 | |
| 137 | #define F32K_SYS_PAD32K_BOND_EN (0x200) //(((*(volatile kal_uint16 *)(F32K_MD_CHIP_STATUS))&0x200)>>9) |
| 138 | |
| 139 | #define F32K_AP_DCXO32K_CK_EN (0x0) |
| 140 | #define F32K_AP_PAD32K_CK_EN (0x2) |
| 141 | |
| 142 | #endif |
| 143 | |
| 144 | #if defined(DRV_F32K_FQMTR_AS_6255) |
| 145 | |
| 146 | #define FQMTR_EN (0x8000) |
| 147 | #define FQMTR_RST (0x4000) |
| 148 | |
| 149 | #define FQMTR_TCKSEL_CLKSQ13M (0x1) |
| 150 | #define FQMTR_TCKSEL_EOSC32K (0xe) |
| 151 | |
| 152 | #define FQMTR_FCKSEL_CLKSQ13M (0x00) |
| 153 | #define FQMTR_FCKSEL_DCXO32K (0x10) |
| 154 | #define FQMTR_FCKSEL_EOSC32K (0x20) |
| 155 | |
| 156 | #define FQMTR_COND_ON (0x0) |
| 157 | #define FQMTR_BUSY (0x8000) |
| 158 | |
| 159 | #define FQMTR_WINSET_LV1 (0x1) |
| 160 | #define FQMTR_WINSET_LV2 (0x10) |
| 161 | |
| 162 | #elif defined(DRV_F32K_FQMTR_AS_6250) |
| 163 | |
| 164 | #define FQMTR_BUSY (0x8000) |
| 165 | #define FQMTR_EN (0x4000) |
| 166 | #define FQMTR_RST (0x2000) |
| 167 | |
| 168 | #define FQMTR_TCKSEL_DCXO32K (0x3) |
| 169 | #define FQMTR_TCKSEL_EOSC32K (0x4) |
| 170 | |
| 171 | #define FQMTR_WINSET_LV1 (0xFFFF) |
| 172 | |
| 173 | #elif defined(DRV_F32K_FQMTR_AS_6280) |
| 174 | |
| 175 | #define FQMTR_EN (0x8000) |
| 176 | #define FQMTR_RST (0x4000) |
| 177 | #define FQMTR_FCKSEL_CLK26M (0x000) |
| 178 | #define FQMTR_FCKSEL_PAD32K (0x100) |
| 179 | #define FQMTR_FCKSEL_DCXO32K (0x200) |
| 180 | |
| 181 | #define FQMTR_TCKSEL_CLKSSQ26M (0x1) |
| 182 | #define FQMTR_BUSY (0x8000) |
| 183 | #define FQMTR_CLKDIV_1_OVER_2 (0x0) |
| 184 | #define F32K_FQMTR_WINSET (0x0) |
| 185 | |
| 186 | #define FQMTR_CON0_DEFAULT_VAL (0x0) |
| 187 | #define FQMTR_CON1_DEFAULT_VAL (0x0) |
| 188 | |
| 189 | #endif |
| 190 | |
| 191 | #if defined(DRV_F32K_XOSC_CALI_DEF_9) |
| 192 | #define F32K_XOSCCALI_DEF_VAL (0x9) |
| 193 | #elif defined(DRV_F32K_XOSC_CALI_DEF_F) |
| 194 | #define F32K_XOSCCALI_DEF_VAL (0xf) |
| 195 | #endif |
| 196 | |
| 197 | #define F32K_EOSCCALI_DEF_VAL (0xF) |
| 198 | |
| 199 | #endif /*!defined(DRV_F32K_CLK_OFF)*/ |
| 200 | |
| 201 | #endif //#ifndef F32K_CLK_HW_H |
| 202 | |