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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / peripheral / inc / f32k_clk_sw.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
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7* permission of MediaTek Inc. (C) 2005
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24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
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33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * f32k_clk_sw.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file is intended for F32K_CLK driver.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
59 * removed!
60 * removed!
61 *
62 * removed!
63 * removed!
64 * removed!
65 *
66 * removed!
67 * removed!
68 * removed!
69 *
70 * removed!
71 * removed!
72 * removed!
73 *
74 * removed!
75 * removed!
76 * removed!
77 *
78 * removed!
79 * removed!
80 * removed!
81 *
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83 * removed!
84 * removed!
85 *
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87 * removed!
88 * removed!
89 *
90 * removed!
91 * removed!
92 * removed!
93 *
94 *------------------------------------------------------------------------------
95 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
96 *============================================================================
97 ****************************************************************************/
98#ifndef F32K_CLK_SW_H
99#define F32K_CLK_SW_H
100
101#include "kal_general_types.h"
102#include "drv_comm.h"
103
104#if defined(DRV_F32K_FQMTR_AS_6255)
105#define IDLE_VAL_WITH_WINSET_LV1 (0x319) //13M meter 32K with winset=1
106#define IDLE_VAL_WITH_WINSET_LV2 (0x1a59) //13M meter 32K with winset=16
107#elif defined(DRV_F32K_FQMTR_AS_6250)
108#define IDLE_VAL_WITH_WINSET_LV1 (0x52) //26M meter 32K with winset=0xffff
109#endif
110
111#if defined(DRV_F32K_FQMTR_AS_6280)
112// 26MHZ = PAD_32K clock*(1+-2.5%) * FQMTR_data/(0x1)
113#define FQMTR_PAD32K_LOWER_BOUND (774)
114#define FQMTR_PAD32K_UPPER_BOUND (814)
115#endif
116
117#define F32K_EOSCCALI_MAX (0x1f)
118#define F32K_EOSCCALI_MIN (0x0)
119// =================================================================
120// Exported APIs, used by modules other than driver level functions
121#if defined(DRV_F32K_INTERNAL_32K)
122extern void F32K_XOSC32_EMB_setting(void);
123#endif //#if defined(DRV_F32K_INTERNAL_32K)
124
125
126#if !defined(__MINI_BOOTLOADER__)
127#if defined(DRV_F32K_INTERNAL_32K) || defined(DRV_F32K_SWITCH_32K)
128extern kal_bool F32K_Query_Is_XOSC32(void);
129#endif //#if defined(DRV_F32K_INTERNAL_32K) || defined(DRV_F32K_SWITCH_32K)
130
131
132#if defined(DRV_F32K_INTERNAL_32K)
133extern kal_uint16 F32K_EOSC32_trimming(void);
134#endif //#if defined(DRV_F32K_INTERNAL_32K)
135
136#if defined(DRV_F32K_SWITCH_32K)
137extern void F32K_Switch_32K_setting(void);
138#endif //#if defined(DRV_F32K_SWITCH_32K)
139
140#endif //#if !defined(__MINI_BOOTLOADER__)
141
142#if !defined(DRV_F32K_CLK_OFF)
143#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_F32K_CLK_REG_DBG__)
144#define DRV_F32K_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
145#define DRV_F32K_Reg(addr) DRV_DBG_Reg(addr)
146#define DRV_F32K_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
147#define DRV_F32K_Reg32(addr) DRV_DBG_Reg32(addr)
148#define DRV_F32K_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
149#define DRV_F32K_Reg8(addr) DRV_DBG_Reg8(addr)
150#define DRV_F32K_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
151#define DRV_F32K_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
152#define DRV_F32K_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
153#define DRV_F32K_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
154#define DRV_F32K_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
155#define DRV_F32K_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
156#define DRV_F32K_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
157#define DRV_F32K_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
158#define DRV_F32K_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
159#else
160#define DRV_F32K_WriteReg(addr,data) DRV_WriteReg(addr,data)
161#define DRV_F32K_Reg(addr) DRV_Reg(addr)
162#define DRV_F32K_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
163#define DRV_F32K_Reg32(addr) DRV_Reg32(addr)
164#define DRV_F32K_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
165#define DRV_F32K_Reg8(addr) DRV_Reg8(addr)
166#define DRV_F32K_ClearBits(addr,data) DRV_ClearBits(addr,data)
167#define DRV_F32K_SetBits(addr,data) DRV_SetBits(addr,data)
168#define DRV_F32K_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
169#define DRV_F32K_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
170#define DRV_F32K_SetBits32(addr,data) DRV_SetBits32(addr,data)
171#define DRV_F32K_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
172#define DRV_F32K_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
173#define DRV_F32K_SetBits8(addr,data) DRV_SetBits8(addr,data)
174#define DRV_F32K_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
175#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_F32K_CLK_REG_DBG__)
176
177#else //!defined(DRV_F32K_CLK_OFF)
178
179#define DRV_F32K_WriteReg(addr,data)
180#define DRV_F32K_Reg(addr) drv_dummy_return()
181#define DRV_F32K_WriteReg32(addr,data)
182#define DRV_F32K_Reg32(addr) drv_dummy_return()
183#define DRV_F32K_WriteReg8(addr,data)
184#define DRV_F32K_Reg8(addr) drv_dummy_return()
185#define DRV_F32K_ClearBits(addr,data)
186#define DRV_F32K_SetBits(addr,data)
187#define DRV_F32K_SetData(addr, bitmask, value)
188#define DRV_F32K_ClearBits32(addr,data)
189#define DRV_F32K_SetBits32(addr,data)
190#define DRV_F32K_SetData32(addr, bitmask, value)
191#define DRV_F32K_ClearBits8(addr,data)
192#define DRV_F32K_SetBits8(addr,data)
193#define DRV_F32K_SetData8(addr, bitmask, value)
194
195#endif //!defined(DRV_F32K_CLK_OFF)
196
197
198#endif //#ifndef F32K_CLK_SW_H
199