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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / peripheral / inc / i2c_dual_hw.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * i2c_dual_hw.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file is intends for I2C DUAL driver.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
59 * removed!
60 * removed!
61 *
62 * removed!
63 * removed!
64 * removed!
65 *
66 * removed!
67 * removed!
68 * removed!
69 *
70 * removed!
71 * removed!
72 * removed!
73 *
74 * removed!
75 * removed!
76 * removed!
77 *
78 * removed!
79 * removed!
80 * removed!
81 *
82 * removed!
83 * removed!
84 * removed!
85 *
86 * removed!
87 * removed!
88 *
89 *
90 * removed!
91 * removed!
92 *
93 *
94 *------------------------------------------------------------------------------
95 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
96 *============================================================================
97 ****************************************************************************/
98#ifndef _I2C_DUAL_HW_H
99#define _I2C_DUAL_HW_H
100#include "drv_features.h"
101
102#include "drv_comm.h"
103#include "reg_base.h"
104
105#if defined(DRV_I2C_DUAL)
106
107#ifndef __DRV_DEBUG_I2C_DUAL_REG_READ_WRITE__
108#define I2C_DUAL_DRV_ClearBits16(addr, data) DRV_ClearBits(addr,data)
109#define I2C_DUAL_DRV_SetBits16(addr, data) DRV_SetBits(addr,data)
110#define I2C_DUAL_DRV_WriteReg16(addr, data) DRV_WriteReg(addr, data)
111#define I2C_DUAL_DRV_ReadReg16(addr) DRV_Reg(addr)
112#define I2C_DUAL_DRV_ClearBits32(addr, data) DRV_ClearBits32(addr, data)
113#else // #ifndef __DRV_DEBUG_I2C_DUAL_REG_READ_WRITE__
114#define I2C_DUAL_DRV_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
115#define I2C_DUAL_DRV_SetBits16(addr) DRV_DBG_SetBits(addr)
116#define I2C_DUAL_DRV_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
117#define I2C_DUAL_DRV_ReadReg16(addr) DRV_DBG_Reg(addr)
118#define I2C_DUAL_DRV_ClearBits32(addr, data) DRV_DBG_ClearBits32(addr, data)
119#endif // #ifndef __DRV_DEBUG_I2C_DUAL_REG_READ_WRITE__
120
121
122
123// I2CD means I2C DUAL
124
125#define I2CD_CH1_DATA_PORT (I2C_DUAL_base + 0x00)
126#define I2CD_CH1_SLAVE_ADDR (I2C_DUAL_base + 0x04)
127#define I2CD_INTR_MASK (I2C_DUAL_base + 0x08)
128#define I2CD_INTR_STAT (I2C_DUAL_base + 0x0C)
129#define I2CD_CH1_CTRL (I2C_DUAL_base + 0x10)
130#define I2CD_CH1_TRANSFER_LEN (I2C_DUAL_base + 0x14)
131#define I2CD_CH1_TRANSAC_LEN (I2C_DUAL_base + 0x18)
132#define I2CD_CH1_DELAY_LEN (I2C_DUAL_base + 0x1C)
133#define I2CD_CH1_TIMING (I2C_DUAL_base + 0x20)
134#define I2CD_CH1_START (I2C_DUAL_base + 0x24)
135#define I2CD_CH1_FIFO_STAT (I2C_DUAL_base + 0x30)
136#define I2CD_CH1_FIFO_THRESH (I2C_DUAL_base + 0x34)
137#define I2CD_CH1_FIFO_ADDR_CLR (I2C_DUAL_base + 0x38)
138#define I2CD_IO_CONFIG (I2C_DUAL_base + 0x40)
139#define I2CD_CH1_HS (I2C_DUAL_base + 0x48)
140#define I2CD_SOFTRESET (I2C_DUAL_base + 0x50)
141#if defined(MT6329)
142#define I2CD_IRQSEL (I2C_DUAL_base + 0x60)
143#endif // End of #if defined(MT6329)
144#define I2CD_CH2_DATA_PORT (I2C_DUAL_base + 0x80)
145#define I2CD_CH2_SLAVE_ADDR (I2C_DUAL_base + 0x84)
146#define I2CD_CH2_CTRL (I2C_DUAL_base + 0x90)
147#define I2CD_CH2_TRANSFER_LEN (I2C_DUAL_base + 0x94)
148#define I2CD_CH2_TRANSAC_LEN (I2C_DUAL_base + 0x98)
149#define I2CD_CH2_DELAY_LEN (I2C_DUAL_base + 0x9C)
150#define I2CD_CH2_TIMING (I2C_DUAL_base + 0xA0)
151#define I2CD_CH2_START (I2C_DUAL_base + 0xA4)
152#define I2CD_CH2_FIFO_STAT (I2C_DUAL_base + 0xB0)
153#define I2CD_CH2_FIFO_ADDR_CLR (I2C_DUAL_base + 0xB8)
154
155// 0x00
156#define I2CD_CH1_DATA_PORT_MASK 0x00FF
157#define I2CD_CH1_DATA_PORT_SHIFT 0
158
159// 0x04
160#define I2CD_CH1_SLAVE_ADDR_MASK 0x00FF
161#define I2CD_CH1_SLAVE_ADDR_SHIFT 0
162
163// 0x08
164#define I2CD_INTR_MASK_CH1_TRANS_COMP_MASK 0x0001
165#define I2CD_INTR_MASK_CH1_TRANS_COMP_SHIFT 0
166#define I2CD_INTR_MASK_CH1_ACK_ERR_MASK 0x0002
167#define I2CD_INTR_MASK_CH1_ACK_ERR_SHIFT 1
168#define I2CD_INTR_MASK_CH1_HSNAK_ERR_MASK 0x0004
169#define I2CD_INTR_MASK_CH1_HSNAK_ERR_SHIFT 2
170#define I2CD_INTR_MASK_CH2_TRANS_COMP_MASK 0x0010
171#define I2CD_INTR_MASK_CH2_TRANS_COMP_SHIFT 4
172#define I2CD_INTR_MASK_CH2_ACK_ERR_MASK 0x0020
173#define I2CD_INTR_MASK_CH2_ACK_ERR_SHIFT 5
174
175// 0x0C
176#define I2CD_INTR_STAT_CH1_TRANS_COMP_MASK 0x0001
177#define I2CD_INTR_STAT_CH1_TRANS_COMP_SHIFT 0
178#define I2CD_INTR_STAT_CH1_ACK_ERR_MASK 0x0002
179#define I2CD_INTR_STAT_CH1_ACK_ERR_SHIFT 1
180#define I2CD_INTR_STAT_CH1_HSNAK_ERR_MASK 0x0004
181#define I2CD_INTR_STAT_CH1_HSNAK_ERR_SHIFT 2
182#define I2CD_INTR_STAT_CH2_TRANS_COMP_MASK 0x0010
183#define I2CD_INTR_STAT_CH2_TRANS_COMP_SHIFT 4
184#define I2CD_INTR_STAT_CH2_ACK_ERR_MASK 0x0020
185#define I2CD_INTR_STAT_CH2_ACK_ERR_SHIFT 5
186
187// 0x10
188#define I2CD_CH1_CTRL_RESTART_MASK 0x0002
189#define I2CD_CH1_CTRL_RESTART_SHIFT 1
190#define I2CD_CH1_CTRL_DMAEN_MASK 0x0004
191#define I2CD_CH1_CTRL_DMAEN_SHIFT 2
192#define I2CD_CH1_CTRL_CLK_EXT_EN_MASK 0x0008
193#define I2CD_CH1_CTRL_CLK_EXT_EN_SHIFT 3
194#define I2CD_CH1_CTRL_DIR_CHANGE_MASK 0x0010
195#define I2CD_CH1_CTRL_DIR_CHANGE_SHIFT 4
196#define I2CD_CH1_CTRL_ACKERR_DET_EN_MASK 0x0020
197#define I2CD_CH1_CTRL_ACKERR_DET_EN_SHIFT 5
198#define I2CD_CH1_CTRL_TRANSFER_LEN_CHANGE_MASK 0x0040
199#define I2CD_CH1_CTRL_TRANSFER_LEN_CHANGE_SHIFT 6
200
201// 0x14
202#define I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_MASK 0x00FF
203#define I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_SHIFT 0
204#define I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_AUX_MASK 0x1F00
205#define I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_AUX_SHIFT 8
206
207// 0x18
208#define I2CD_CH1_TRANSAC_LEN_TRANSAC_LEN_MASK 0x00FF
209#define I2CD_CH1_TRANSAC_LEN_TRANSAC_LEN_SHIFT 0
210
211// 0x1C
212#define I2CD_CH1_DELAY_LEN_DELAY_LEN_MASK 0x00FF
213#define I2CD_CH1_DELAY_LEN_DELAY_LEN_SHIFT 0
214
215// 0x20
216#define I2CD_CH1_TIMING_STEP_CNT_DIV_MASK 0x003F
217#define I2CD_CH1_TIMING_STEP_CNT_DIV_SHIFT 0
218#define I2CD_CH1_TIMING_SAMPLE_CNT_DIV_MASK 0x0700
219#define I2CD_CH1_TIMING_SAMPLE_CNT_DIV_SHIFT 8
220#define I2CD_CH1_TIMING_DATA_READ_MASK 0x7000
221#define I2CD_CH1_TIMING_DATA_READ_SHIFT 12
222#define I2CD_CH1_TIMING_DATA_READ_ADJ_MASK 0x8000
223#define I2CD_CH1_TIMING_DATA_READ_ADJ_SHIFT 15
224
225// 0x24
226#define I2CD_CH1_START_START_MASK 0x0001
227#define I2CD_CH1_START_START_SHIFT 0
228
229// 0x30
230#define I2CD_CH1_FIFO_STAT_RD_EMPTY_MASK 0x0001
231#define I2CD_CH1_FIFO_STAT_RD_EMPTY_SHIFT 0
232#define I2CD_CH1_FIFO_STAT_WR_FULL_MASK 0x0002
233#define I2CD_CH1_FIFO_STAT_WR_FULL_SHIFT 1
234#define I2CD_CH1_FIFO_STAT_OFFSET_MASK 0x00F0
235#define I2CD_CH1_FIFO_STAT_OFFSET_SHIFT 4
236#define I2CD_CH1_FIFO_STAT_WR_ADDR_MASK 0x0F00
237#define I2CD_CH1_FIFO_STAT_WR_ADDR_SHIFT 8
238#define I2CD_CH1_FIFO_STAT_RD_ADDR_MASK 0xF000
239#define I2CD_CH1_FIFO_STAT_RD_ADDR_SHIFT 12
240
241// 0x34
242#define I2CD_CH1_FIFO_THRESH_RX_TRIG_MASK 0x0007
243#define I2CD_CH1_FIFO_THRESH_RX_TRIG_SHIFT 0
244#define I2CD_CH1_FIFO_THRESH_TX_TRIG_MASK 0x0700
245#define I2CD_CH1_FIFO_THRESH_TX_TRIG_SHIFT 8
246
247// 0x38
248#define I2CD_CH1_FIFO_ADDR_CLR_CR_MASK 0x0001
249#define I2CD_CH1_FIFO_ADDR_CLR_CR_SHIFT 0
250
251// 0x40
252#define I2CD_IO_CONFIG_SCL_IO_MASK 0x0001
253#define I2CD_IO_CONFIG_SCL_IO_SHIFT 0
254#define I2CD_IO_CONFIG_SDA_IO_MASK 0x0002
255#define I2CD_IO_CONFIG_SDA_IO_SHIFT 1
256#define I2CD_IO_CONFIG_SYNC_EN_MASK 0x0004
257#define I2CD_IO_CONFIG_SYNC_EN_SHIFT 2
258#define I2CD_IO_CONFIG_IDLE_OE_EN_MASK 0x0008 // MT6575
259#define I2CD_IO_CONFIG_IDLE_OE_SIFT 3 // MT6575
260
261// 0x48
262#define I2CD_CH1_HS_HS_EN_MASK 0x0001
263#define I2CD_CH1_HS_HS_EN_SHIFT 0
264#define I2CD_CH1_HS_HS_NAK_ERR_DET_EN_MASK 0x0002
265#define I2CD_CH1_HS_HS_NAK_ERR_DET_EN_SHIFT 1
266#define I2CD_CH1_HS_MASTER_CODE_MASK 0x0070
267#define I2CD_CH1_HS_MASTER_CODE_SHIFT 4
268#define I2CD_CH1_HS_HS_STEP_CNT_DIV_MASK 0x0700
269#define I2CD_CH1_HS_HS_STEP_CNT_DIV_SHIFT 8
270#define I2CD_CH1_HS_HS_SAMPLE_CNT_DIV_MASK 0x7000
271#define I2CD_CH1_HS_HS_SAMPLE_CNT_DIV_SHIFT 12
272
273// 0x50
274#define I2CD_SOFTRESET_SOFTRESET_MASK 0x0001
275#define I2CD_SOFTRESET_SOFTRESET_SHIFT 0
276
277// 0x60
278#define I2CD_IRQ_SEL_IRQ_SEL_MASK 0x0001 // MT6575
279#define I2CD_IRQ_SEL_IRQ_SEL_SHIFT 0 // MT6575
280
281// 0x80
282#define I2CD_CH2_DATA_PORT_MASK 0x00FF
283#define I2CD_CH2_DATA_PORT_SHIFT 0
284
285// 0x84
286#define I2CD_CH2_SLAVE_ADDR_MASK 0x00FF
287#define I2CD_CH2_SLAVE_ADDR_SHIFT 0
288
289// 0x90
290#define I2CD_CH2_CTRL_RESTART_MASK 0x0002
291#define I2CD_CH2_CTRL_RESTART_SHIFT 1
292#define I2CD_CH2_CTRL_CLK_EXT_EN_MASK 0x0008
293#define I2CD_CH2_CTRL_CLK_EXT_EN_SHIFT 3
294#define I2CD_CH2_CTRL_DIR_CHANGE_MASK 0x0010
295#define I2CD_CH2_CTRL_DIR_CHANGE_SHIFT 4
296#define I2CD_CH2_CTRL_ACKERR_DET_EN_MASK 0x0020
297#define I2CD_CH2_CTRL_ACKERR_DET_EN_SHIFT 5
298#define I2CD_CH2_CTRL_TRANSFER_LEN_CHANGE_MASK 0x0040
299#define I2CD_CH2_CTRL_TRANSFER_LEN_CHANGE_SHIFT 6
300#define I2CD_CH2_CTRL_CH_WAIT_EN_MASK 0x0080
301#define I2CD_CH2_CTRL_CH_WAIT_EN_SHIFT 7
302
303// 0x94
304#define I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_MASK 0x0007
305#define I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_SHIFT 0
306#define I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_AUX_MASK 0x0700
307#define I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_AUX_SHIFT 8
308
309// 0x98
310#define I2CD_CH2_TRANSAC_LEN_TRANSAC_LEN_MASK 0x0007
311#define I2CD_CH2_TRANSAC_LEN_TRANSAC_LEN_SHIFT 0
312
313// 0x9C
314#define I2CD_CH2_DELAY_LEN_DELAY_LEN_MASK 0x0003
315#define I2CD_CH2_DELAY_LEN_DELAY_LEN_SHIFT 0
316
317// 0xA0
318#define I2CD_CH2_TIMING_STEP_CNT_DIV_MASK 0x003F
319#define I2CD_CH2_TIMING_STEP_CNT_DIV_SHIFT 0
320#define I2CD_CH2_TIMING_SAMPLE_CNT_DIV_MASK 0x0700
321#define I2CD_CH2_TIMING_SAMPLE_CNT_DIV_SHIFT 8
322#define I2CD_CH2_TIMING_DATA_READ_MASK 0x7000
323#define I2CD_CH2_TIMING_DATA_READ_SHIFT 12
324#define I2CD_CH2_TIMING_DATA_READ_ADJ_MASK 0x8000
325#define I2CD_CH2_TIMING_DATA_READ_ADJ_SHIFT 15
326
327// 0xA4
328#define I2CD_CH2_START_START_MASK 0x0001
329#define I2CD_CH2_START_START_SHIFT 0
330
331// 0xB0
332#define I2CD_CH2_FIFO_STAT_RD_EMPTY_MASK 0x0001
333#define I2CD_CH2_FIFO_STAT_RD_EMPTY_SHIFT 0
334#define I2CD_CH2_FIFO_STAT_WR_FULL_MASK 0x0002
335#define I2CD_CH2_FIFO_STAT_WR_FULL_SHIFT 1
336#define I2CD_CH2_FIFO_STAT_OFFSET_MASK 0x00F0
337#define I2CD_CH2_FIFO_STAT_OFFSET_SHIFT 4
338#define I2CD_CH2_FIFO_STAT_WR_ADDR_MASK 0x0F00
339#define I2CD_CH2_FIFO_STAT_WR_ADDR_SHIFT 8
340#define I2CD_CH2_FIFO_STAT_RD_ADDR_MASK 0xF000
341#define I2CD_CH2_FIFO_STAT_RD_ADDR_SHIFT 12
342
343// 0xB8
344#define I2CD_CH2_FIFO_ADDR_CLR_CR_MASK 0x0001
345#define I2CD_CH2_FIFO_ADDR_CLR_CR_SHIFT 0
346
347///////////////////////////////////////////////////////////////////////////////
348// Ch1 macros
349#define I2C_DUAL_CH1_CLEAR_FIFO(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH1_FIFO_ADDR_CLR, (kal_uint16)1)
350#define I2C_DUAL_CH1_CLEAR_INTR_STAT(val) {\
351 kal_uint16 tmp;\
352 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_INTR_STAT);\
353 tmp &= (I2CD_INTR_STAT_CH1_TRANS_COMP_MASK | I2CD_INTR_STAT_CH1_ACK_ERR_MASK | I2CD_INTR_STAT_CH1_HSNAK_ERR_MASK);\
354 tmp |= (val);\
355 I2C_DUAL_DRV_WriteReg16(I2CD_INTR_STAT, tmp);\
356}
357#define I2C_DUAL_CH1_SET_SLAVE_ADDR(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH1_SLAVE_ADDR, (kal_uint16)val)
358#define I2C_DUAL_CH1_SET_TRANSFER_LEN(len1, len2) {\
359 kal_uint16 tmp;\
360 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH1_TRANSFER_LEN);\
361 tmp &= ~(I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_MASK | I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_AUX_MASK);\
362 tmp |= ((kal_uint16)len1 << I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_SHIFT);\
363 tmp |= ((kal_uint16)len2 << I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_AUX_SHIFT);\
364 I2C_DUAL_DRV_WriteReg16(I2CD_CH1_TRANSFER_LEN, tmp);\
365}
366#define I2C_DUAL_CH1_SET_TIMING(sample_cnt, step_cnt) {\
367 kal_uint16 tmp;\
368 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH1_TIMING);\
369 tmp &= ~(I2CD_CH1_TIMING_STEP_CNT_DIV_MASK | I2CD_CH1_TIMING_SAMPLE_CNT_DIV_MASK);\
370 tmp |= ((kal_uint16)sample_cnt << I2CD_CH1_TIMING_SAMPLE_CNT_DIV_SHIFT);\
371 tmp |= ((kal_uint16)step_cnt << I2CD_CH1_TIMING_STEP_CNT_DIV_SHIFT);\
372 I2C_DUAL_DRV_WriteReg16(I2CD_CH1_TIMING, tmp);\
373}
374
375#define I2C_DUAL_CH1_SET_TRANSAC_LEN(len) I2C_DUAL_DRV_WriteReg16(I2CD_CH1_TRANSAC_LEN, (kal_uint16)len);
376#define I2C_DUAL_CH1_SET_DIR_CHANGE(val) {\
377 kal_uint16 tmp;\
378 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH1_CTRL);\
379 tmp &= ~I2CD_CH1_CTRL_DIR_CHANGE_MASK;\
380 tmp |= ((kal_uint16)val << I2CD_CH1_CTRL_DIR_CHANGE_SHIFT);\
381 I2C_DUAL_DRV_WriteReg16(I2CD_CH1_CTRL, tmp);\
382}
383
384#define I2C_DUAL_CH1_SET_RESTART(val) {\
385 kal_uint16 tmp;\
386 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH1_CTRL);\
387 tmp &= ~I2CD_CH1_CTRL_RESTART_MASK;\
388 tmp |= ((kal_uint16)val << I2CD_CH1_CTRL_RESTART_SHIFT);\
389 I2C_DUAL_DRV_WriteReg16(I2CD_CH1_CTRL, tmp);\
390}
391
392#define I2C_DUAL_CH1_SET_INTR(val) {\
393 kal_uint16 tmp;\
394 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_INTR_MASK);\
395 tmp |= (val & (I2CD_INTR_MASK_CH1_TRANS_COMP_MASK | I2CD_INTR_MASK_CH1_ACK_ERR_MASK | I2CD_INTR_MASK_CH1_HSNAK_ERR_MASK));\
396 I2C_DUAL_DRV_WriteReg16(I2CD_INTR_MASK, (kal_uint16)tmp);\
397}
398
399#define I2C_DUAL_CH1_CLR_INTR(val) {\
400 kal_uint16 tmp;\
401 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_INTR_MASK);\
402 tmp &= ~(val & (I2CD_INTR_MASK_CH1_TRANS_COMP_MASK | I2CD_INTR_MASK_CH1_ACK_ERR_MASK | I2CD_INTR_MASK_CH1_HSNAK_ERR_MASK) );\
403 I2C_DUAL_DRV_WriteReg16(I2CD_INTR_MASK, (kal_uint16)tmp);\
404}
405
406
407#define I2C_DUAL_CH1_SET_DATA_PORT(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH1_DATA_PORT, (kal_uint16)val)
408#define I2C_DUAL_CH1_SET_START(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH1_START, I2CD_CH1_START_START_MASK);
409
410
411///////////////////////////////////////////////////////////////////////////////
412// Ch2 macros
413#define I2C_DUAL_CH2_CLEAR_FIFO(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH2_FIFO_ADDR_CLR, (kal_uint16)1)
414#define I2C_DUAL_CH2_CLEAR_INTR_STAT(val) {\
415 kal_uint16 tmp;\
416 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_INTR_STAT);\
417 tmp &= (I2CD_INTR_STAT_CH2_TRANS_COMP_MASK | I2CD_INTR_STAT_CH2_ACK_ERR_MASK);\
418 tmp |= (val);\
419 I2C_DUAL_DRV_WriteReg16(I2CD_INTR_STAT, tmp);\
420}
421#define I2C_DUAL_CH2_SET_SLAVE_ADDR(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH2_SLAVE_ADDR, (kal_uint16)val)
422#define I2C_DUAL_CH2_SET_TRANSFER_LEN(len1, len2) {\
423 kal_uint16 tmp;\
424 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH2_TRANSFER_LEN);\
425 tmp &= ~(I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_MASK | I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_AUX_MASK);\
426 tmp |= ((kal_uint16)len1 << I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_SHIFT);\
427 tmp |= ((kal_uint16)len2 << I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_AUX_SHIFT);\
428 I2C_DUAL_DRV_WriteReg16(I2CD_CH2_TRANSFER_LEN, tmp);\
429}
430#define I2C_DUAL_CH2_SET_TIMING(sample_cnt, step_cnt) {\
431 kal_uint16 tmp;\
432 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH2_TIMING);\
433 tmp &= ~(I2CD_CH2_TIMING_STEP_CNT_DIV_MASK | I2CD_CH2_TIMING_SAMPLE_CNT_DIV_MASK);\
434 tmp |= ((kal_uint16)sample_cnt << I2CD_CH2_TIMING_SAMPLE_CNT_DIV_SHIFT);\
435 tmp |= ((kal_uint16)step_cnt << I2CD_CH2_TIMING_STEP_CNT_DIV_SHIFT);\
436 I2C_DUAL_DRV_WriteReg16(I2CD_CH2_TIMING, tmp);\
437}
438
439#define I2C_DUAL_CH2_SET_TRANSAC_LEN(len) I2C_DUAL_DRV_WriteReg16(I2CD_CH2_TRANSAC_LEN, (kal_uint16)len);
440#define I2C_DUAL_CH2_SET_DIR_CHANGE(val) {\
441 kal_uint16 tmp;\
442 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH2_CTRL);\
443 tmp &= ~I2CD_CH2_CTRL_DIR_CHANGE_MASK;\
444 tmp |= ((kal_uint16)val << I2CD_CH2_CTRL_DIR_CHANGE_SHIFT);\
445 I2C_DUAL_DRV_WriteReg16(I2CD_CH2_CTRL, tmp);\
446}
447
448#define I2C_DUAL_CH2_SET_RESTART(val) {\
449 kal_uint16 tmp;\
450 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH2_CTRL);\
451 tmp &= ~I2CD_CH2_CTRL_RESTART_MASK;\
452 tmp |= ((kal_uint16)val << I2CD_CH2_CTRL_RESTART_SHIFT);\
453 I2C_DUAL_DRV_WriteReg16(I2CD_CH2_CTRL, tmp);\
454}
455
456#define I2C_DUAL_CH2_SET_INTR(val) {\
457 kal_uint16 tmp;\
458 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_INTR_MASK);\
459 tmp |= (val & (I2CD_INTR_MASK_CH2_TRANS_COMP_MASK | I2CD_INTR_MASK_CH2_ACK_ERR_MASK));\
460 I2C_DUAL_DRV_WriteReg16(I2CD_INTR_MASK, (kal_uint16)tmp);\
461}
462
463#define I2C_DUAL_CH2_CLR_INTR(val) {\
464 kal_uint16 tmp;\
465 tmp = I2C_DUAL_DRV_ReadReg16(I2CD_INTR_MASK);\
466 tmp &= ~(val & (I2CD_INTR_MASK_CH2_TRANS_COMP_MASK | I2CD_INTR_MASK_CH2_ACK_ERR_MASK) );\
467 I2C_DUAL_DRV_WriteReg16(I2CD_INTR_MASK, (kal_uint16)tmp);\
468}
469
470#define I2C_DUAL_CH2_SET_DATA_PORT(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH2_DATA_PORT, (kal_uint16)val)
471#define I2C_DUAL_CH2_SET_START(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH2_START, I2CD_CH2_START_START_MASK);
472
473#endif // #if defined(DRV_I2C_DUAL)
474
475#endif // #ifndef _I2C_DUAL_HW_H
476