| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * rtc_hw.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Maui_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file is intends for RTC driver. |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
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| 187 | *------------------------------------------------------------------------------ |
| 188 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 189 | *============================================================================ |
| 190 | ****************************************************************************/ |
| 191 | #ifndef _RTC_HW_H |
| 192 | #define _RTC_HW_H |
| 193 | #include "reg_base.h" |
| 194 | |
| 195 | #if !defined(DRV_RTC_OFF) |
| 196 | /***************** |
| 197 | * RTC Registers * |
| 198 | *****************/ |
| 199 | #define RTC_BBPU (RTC_base+0x0000) /*Baseband Power-up ctrl */ |
| 200 | #define RTC_IRQ_STATUS (RTC_base+0x0004) /*IRQ Status */ |
| 201 | #define RTC_IRQ_EN (RTC_base+0x0008) /*IRQ Enable */ |
| 202 | #define RTC_CII_EN (RTC_base+0x000C) /*Counter increment IRQ */ |
| 203 | #define RTC_AL_MASK (RTC_base+0x0010)/*Alarm mask control */ |
| 204 | #define RTC_TC_SEC (RTC_base+0x0014)/*Second time counter */ |
| 205 | #define RTC_TC_MIN (RTC_base+0x0018)/*Minute time counter */ |
| 206 | #define RTC_TC_HOU (RTC_base+0x001C)/*Hour time counter */ |
| 207 | #define RTC_TC_DOM (RTC_base+0x0020)/*Day of Mth time counter */ |
| 208 | #define RTC_TC_DOW (RTC_base+0x0024)/*Day of Wk time counter */ |
| 209 | #define RTC_TC_MTH (RTC_base+0x0028)/*Month time counter */ |
| 210 | #define RTC_TC_YEA (RTC_base+0x002C)/*Year time counter */ |
| 211 | #define RTC_AL_SEC (RTC_base+0x0030)/*Second alarm */ |
| 212 | #define RTC_AL_MIN (RTC_base+0x0034)/*Minute alarm */ |
| 213 | #define RTC_AL_HOU (RTC_base+0x0038)/*Hour alarm */ |
| 214 | #define RTC_AL_DOM (RTC_base+0x003C)/*Day of Month alarm */ |
| 215 | #define RTC_AL_DOW (RTC_base+0x0040)/*Day of Week alarm */ |
| 216 | #define RTC_AL_MTH (RTC_base+0x0044)/*Month alarm */ |
| 217 | #define RTC_AL_YEA (RTC_base+0x0048)/*Year alarm */ |
| 218 | #define RTC_XOSCCAL (RTC_base+0x004C) |
| 219 | #define RTC_POWERKEY1 (RTC_base+0x0050) |
| 220 | #define RTC_POWERKEY2 (RTC_base+0x0054) |
| 221 | #if defined(DRV_RTC_REG_COMM) |
| 222 | #define RTC_INFO1 (RTC_base+0x0058) |
| 223 | #define RTC_INFO2 (RTC_base+0x005c) |
| 224 | #if defined(DRV_RTC_W_FLAG) |
| 225 | #define RTC_W_FLAG (RTC_base+0x0060) |
| 226 | #endif |
| 227 | #endif /*DRV_RTC_REG_COMM*/ |
| 228 | |
| 229 | #if defined(DRV_RTC_HW_CALI) |
| 230 | #define RTC_SPAR0 (RTC_base+0x0060) |
| 231 | #define RTC_SPAR1 (RTC_base+0x0064) |
| 232 | #define RTC_PROT (RTC_base+0x0068) |
| 233 | #define RTC_DIFF (RTC_base+0x006C) |
| 234 | #define RTC_CALI (RTC_base+0x0070) |
| 235 | #define RTC_WRTGR (RTC_base+0x0074) |
| 236 | #endif /* DRV_RTC_HW_CALI */ |
| 237 | |
| 238 | #if defined(DRV_RTC_GPIO) |
| 239 | #define RTC_GPIO (RTC_base+0x0078) |
| 240 | #endif /* DRV_RTC_GPIO */ |
| 241 | |
| 242 | //RTC_IRQ_STATUS |
| 243 | #define RTC_IRQ_STATUS_AL_STAT 0x0001 |
| 244 | #define RTC_IRQ_STATUS_TC_STAT 0x0002 |
| 245 | #if defined(DRV_RTC_LOW_POWER_DETECT) |
| 246 | #define RTC_IRQ_STATUS_LP_STAT 0x0008 |
| 247 | #endif /* DRV_RTC_GPIO */ |
| 248 | |
| 249 | //RTC_IRQ_EN |
| 250 | #define RTC_IRQ_EN_AL 0x0001 |
| 251 | #define RTC_IRQ_EN_TC 0x0002 |
| 252 | #define RTC_IRQ_EN_ONESHOT 0x0004 |
| 253 | |
| 254 | #define RTC_IRQ_EN_ALLOFF 0x0000 |
| 255 | |
| 256 | //RTC_CII_EN |
| 257 | #define RTC_CII_EN_SEC 0x0001 |
| 258 | #define RTC_CII_EN_MIN 0x0002 |
| 259 | #define RTC_CII_EN_HOU 0x0004 |
| 260 | #define RTC_CII_EN_DOM 0x0008 |
| 261 | #define RTC_CII_EN_DOW 0x0010 |
| 262 | #define RTC_CII_EN_MTH 0x0020 |
| 263 | #define RTC_CII_EN_YEA 0x0040 |
| 264 | #define RTC_CII_EN_ALLOFF 0x0000 |
| 265 | #if defined(DRV_RTC_CII_HALF_SEC) |
| 266 | #define RTC_CII_EN_1_2S 0x0080 |
| 267 | #define RTC_CII_EN_1_4S 0x0100 |
| 268 | #define RTC_CII_EN_1_8S 0x0200 |
| 269 | #endif /*DRV_RTC_CII_HALF_SEC*/ |
| 270 | |
| 271 | //RTC_AL_MASK, mask ==> 1 close intr, 0 open intr. |
| 272 | #define RTC_AL_MASK_SEC 0x0001 |
| 273 | #define RTC_AL_MASK_MIN 0x0003 |
| 274 | #define RTC_AL_MASK_HOU 0x0007 |
| 275 | #define RTC_AL_MASK_DOM 0x000f |
| 276 | #define RTC_AL_MASK_DOW 0x0017 |
| 277 | #define RTC_AL_MASK_MTH 0x002f |
| 278 | #define RTC_AL_MASK_YEA 0x006f |
| 279 | #define RTC_AL_MASK_ALLOFF 0x0000 |
| 280 | #define RTC_AL_MASK_NORMAL (RTC_AL_MASK_HOU | RTC_AL_MASK_MIN) |
| 281 | |
| 282 | //RTC_POWERKEY |
| 283 | #define RTC_POWERKEY1_KEY 0xa357 |
| 284 | #define RTC_POWERKEY2_KEY 0x67d2 |
| 285 | |
| 286 | #define RTC_PROTECT1 0x586a |
| 287 | #define RTC_PROTECT2 0x9136 |
| 288 | |
| 289 | #if defined(DRV_RTC_INFO_MASK) |
| 290 | #define RTC_INFO1_RESETDTIME 0x000f |
| 291 | #define RTC_INFO1_INFO_MASK 0x00f0 |
| 292 | #define RTC_INFO2_INFO_MASK 0x00ff |
| 293 | #endif /*DRV_RTC_INFO_MASK*/ |
| 294 | |
| 295 | #if defined(DRV_RTC_REG_COMM) |
| 296 | #if !defined(DRV_RTC_PDN_EXTEND) |
| 297 | #define RTC_PDN1_MASK 0x00f1 |
| 298 | #endif /*!defined(DRV_RTC_PDN_EXTEND)*/ |
| 299 | #endif /*DRV_RTC_REG_COMM*/ |
| 300 | |
| 301 | |
| 302 | #if defined(DRV_RTC_W_FLAG) |
| 303 | |
| 304 | #define RTC_POWERKEY_BUSY 0x3 |
| 305 | #define RTC_BBPU_BUSY 0x4 |
| 306 | #define RTC_TIME_BUSY 0x8000 |
| 307 | |
| 308 | #endif |
| 309 | |
| 310 | #if defined(DRV_RTC_HW_CALI) |
| 311 | #define RTC_DIFF_MASK 0x0fff |
| 312 | #define RTC_CALI_MASK 0x007f |
| 313 | #define RTC_WRTGR_WRTGR 0x0001 |
| 314 | #endif |
| 315 | |
| 316 | |
| 317 | #define RTC_OSC32_AMP_EN 0x100 |
| 318 | |
| 319 | #if defined(DRV_RTC_INTERNAL_32K_AS_6255) |
| 320 | #define RTC_OSC32_XOSC32_ENB 0x020 |
| 321 | #define RTC_OSC32_EMBCK_SEL_MODE 0x040 |
| 322 | #define RTC_OSC32_EMBCK_SEL 0x080 |
| 323 | #define RTC_OSC32_EOSC_CHOP_EN 0x400 |
| 324 | |
| 325 | #define RTC_GPIO_VBAT_LPSTA_RAW 0x0001 |
| 326 | #define RTC_GPIO_EMBCK_SWITCH_FAIL 0x0002 |
| 327 | #endif |
| 328 | |
| 329 | #if defined(DRV_RTC_GPIO) |
| 330 | #define RTC_GPIO_LPEN 0x0004 |
| 331 | #define RTC_GPIO_LPRST 0x0008 |
| 332 | #define RTC_GPIO_CDBO 0x0010 |
| 333 | #define RTC_GPIO_F32KOB 0x0020 |
| 334 | #define RTC_GPIO_GPO 0x0040 |
| 335 | #define RTC_GPIO_GOE 0x0080 |
| 336 | #define RTC_GPIO_GSR 0x0100 |
| 337 | #define RTC_GPIO_GSMT 0x0200 |
| 338 | #define RTC_GPIO_GPEN 0x0400 |
| 339 | #define RTC_GPIO_GPU 0x0800 |
| 340 | #define RTC_GPIO_GE4 0x1000 |
| 341 | #define RTC_GPIO_GE8 0x2000 |
| 342 | #define RTC_GPIO_GPI 0x4000 |
| 343 | #define RTC_GPIO_LPSTA_RAW 0x8000 |
| 344 | #endif |
| 345 | |
| 346 | #endif /*!defined(DRV_RTC_OFF)*/ |
| 347 | |
| 348 | #endif /*_RTC_HW_H*/ |
| 349 | |