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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / peripheral / inc / uart_hw.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * uart_hw.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file is intends for UART driver.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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304 *------------------------------------------------------------------------------
305 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
306 *============================================================================
307 ****************************************************************************/
308#ifndef UART_HW_H
309#define UART_HW_H
310//#include "drv_features.h"
311/*#define SLEEP_DONT_CARE_DBG_INFO */
312#include "dma_hw.h"
313#include "drv_comm.h"
314#if !defined(DRV_UART_OFF)
315/*UART1 MMP address, UART1_base = 0x80130000, UART2_base = 0x80180000,, UART3_base = 0x801b0000*/
316/*used in Task or normal function*/
317#define UART_RBR(_baseaddr) (_baseaddr+0x0) /* Read only */
318#define UART_THR(_baseaddr) (_baseaddr+0x0) /* Write only */
319#define UART_IER(_baseaddr) (_baseaddr+0x4)
320#define UART_IIR(_baseaddr) (_baseaddr+0x8) /* Read only */
321#define UART_FCR(_baseaddr) (_baseaddr+0x8) /* Write only */
322#define UART_LCR(_baseaddr) (_baseaddr+0xc)
323#define UART_MCR(_baseaddr) (_baseaddr+0x10)
324#define UART_LSR(_baseaddr) (_baseaddr+0x14)
325#define UART_MSR(_baseaddr) (_baseaddr+0x18)
326#define UART_SCR(_baseaddr) (_baseaddr+0x1c)
327#define UART_DLL(_baseaddr) (_baseaddr+0x0)
328#define UART_DLH(_baseaddr) (_baseaddr+0x4)
329#define UART_EFR(_baseaddr) (_baseaddr+0x8) /* Only when LCR = 0xbf */
330#define UART_XON1(_baseaddr) (_baseaddr+0x10) /* Only when LCR = 0xbf */
331#define UART_XON2(_baseaddr) (_baseaddr+0x14) /* Only when LCR = 0xbf */
332#define UART_XOFF1(_baseaddr) (_baseaddr+0x18) /* Only when LCR = 0xbf */
333#define UART_XOFF2(_baseaddr) (_baseaddr+0x1c) /* Only when LCR = 0xbf */
334#define UART_FRACDIV_L(_baseaddr) (_baseaddr+0x54)
335#define UART_FRACDIV_M(_baseaddr) (_baseaddr+0x58)
336
337#if defined(DRV_UART_FCR_RD)
338#define UART_FCR_RD(_baseaddr) (_baseaddr+0x5C) /* Read only */
339#endif
340
341#if defined(DRV_UART_TX_ACTIVE)
342#define UART_TX_ACTIVE_EN(_baseaddr) (_baseaddr+0x5C)
343#endif
344
345#ifdef DRV_UART_6205B_REG
346 #define UART_RATE_STEP(_baseaddr) (_baseaddr+0x20)
347 #define UART_STEP_COUNT(_baseaddr) (_baseaddr+0x24)
348 #define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr+0x28)
349#endif /*DRV_UART_6205B_REG*/
350#if 0
351#ifdef MT6217/*TY add this 10/01/2004,*/
352/* under construction !*/
353/* under construction !*/
354/* under construction !*/
355/* under construction !*/
356/* under construction !*/
357/* under construction !*/
358/* under construction !*/
359#endif /*MT6217*/
360#endif
361#if defined(DRV_UART_BASIC_REG)
362 #define UART_AUTOBAUD_EN(_baseaddr) (_baseaddr+0x20)
363 #define UART_RATE_STEP(_baseaddr) (_baseaddr+0x24)
364 #define UART_STEP_COUNT(_baseaddr) (_baseaddr+0x28)
365 #define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr+0x2c)
366 #define UART_AUTOBAUD_REG(_baseaddr) (_baseaddr+0x30)
367 #define UART_RATE_FIX_REG(_baseaddr) (_baseaddr+0x34)
368 #define UART_AUTO_BAUDSAMPLE(_baseaddr) (_baseaddr+0x38)
369 #define UART_GUARD(_baseaddr) (_baseaddr+0x3C)
370 #define UART_ESCAPE_DAT(_baseaddr) (_baseaddr+0x40)
371 #define UART_ESCAPE_EN(_baseaddr) (_baseaddr+0x44)
372 #define UART_SLEEP_EN(_baseaddr) (_baseaddr+0x48)
373#endif /*DRV_UART_BASIC_REG*/
374#if defined(DRV_UART_VFIFO_EN_REG)
375 #define UART_RXDMA(_baseaddr) (_baseaddr+0x4c)
376#endif
377#define UART_RXTRI(_baseaddr) (_baseaddr+0x50)
378
379
380//IER
381#if defined(DRV_UART_FIFO_FLOW_CONTROL)
382#define UART_IER_ERBFI 0x0001
383#define UART_IER_ETBEI 0x0002
384#define UART_IER_ELSI 0x0004
385#define UART_IER_EDSSI 0x0008
386#define UART_IER_VFF_FC_EN 0x0010
387#define UART_IER_XOFFI 0x0020
388#define UART_IER_RTSI 0x0040
389#define UART_IER_CTSI 0x0080
390
391#ifdef DRV_UART_6208_REG
392 #define UART1_IER_HW_NORMALINTS 0x001d
393 #define UART1_IER_HW_ALLINTS 0x001f
394 #define UART1_IER_SW_NORMALINTS 0x003d
395 #define UART1_IER_SW_ALLINTS 0x003f
396 /*Disable MSR interrupt*/
397 #define UART2_IER_HW_NORMALINTS 0x0015
398 #define UART2_IER_HW_ALLINTS 0x0017
399 #define UART2_IER_SW_NORMALINTS 0x0035
400 #define UART2_IER_SW_ALLINTS 0x0037
401#endif /*DRV_UART_6208_REG*/
402#if defined(DRV_UART_6205_REG) || defined(DRV_UART_6205B_REG) || defined(FPGA)|| defined(DRV_UART_BASIC_REG)
403 #define IER_HW_NORMALINTS 0x001d
404 #define IER_HW_ALLINTS 0x001f
405 #define IER_SW_NORMALINTS 0x003d
406 #define IER_SW_ALLINTS 0x003f
407#endif /*DRV_UART_6205_REG, DRV_UART_6205B_REG, FPGA, DRV_UART_BASIC_REG*/
408#define UART_IER_ALLOFF 0x0010 //because of UART_IER_VFF_FC_EN not one of interrupt masks
409#define UART_IER_VFIFO 0x0011
410#else //#if defined(DRV_UART_FIFO_FLOW_CONTROL)
411#define UART_IER_ERBFI 0x0001
412#define UART_IER_ETBEI 0x0002
413#define UART_IER_ELSI 0x0004
414#define UART_IER_EDSSI 0x0008
415#define UART_IER_VFF_FC_EN 0x0010
416#define UART_IER_XOFFI 0x0020
417#define UART_IER_RTSI 0x0040
418#define UART_IER_CTSI 0x0080
419
420#ifdef DRV_UART_6208_REG
421 #define UART1_IER_HW_NORMALINTS 0x000d
422 #define UART1_IER_HW_ALLINTS 0x000f
423 #define UART1_IER_SW_NORMALINTS 0x002d
424 #define UART1_IER_SW_ALLINTS 0x002f
425 /*Disable MSR interrupt*/
426 #define UART2_IER_HW_NORMALINTS 0x0005
427 #define UART2_IER_HW_ALLINTS 0x0007
428 #define UART2_IER_SW_NORMALINTS 0x0025
429 #define UART2_IER_SW_ALLINTS 0x0027
430#endif /*DRV_UART_6208_REG*/
431#if defined(DRV_UART_6205_REG) || defined(DRV_UART_6205B_REG) || defined(FPGA)|| defined(DRV_UART_BASIC_REG)
432 #define IER_HW_NORMALINTS 0x000d
433 #define IER_HW_ALLINTS 0x000f
434 #define IER_SW_NORMALINTS 0x002d
435 #define IER_SW_ALLINTS 0x002f
436#endif /*DRV_UART_6205_REG, DRV_UART_6205B_REG, FPGA, DRV_UART_BASIC_REG*/
437
438#define UART_IER_ALLOFF 0x0000
439#define UART_IER_VFIFO 0x0001
440#endif //#if defined(DRV_UART_FIFO_FLOW_CONTROL)
441
442
443
444
445
446
447#if defined(DRV_UART_6205B_REG) || defined(DRV_UART_BASIC_REG)
448 #define UART_RATE_STEP_16 0x0000 /* baud = clock/UART_RATE_STEP/divisor */
449 #define UART_RATE_STEP_8 0x0001
450 #define UART_RATE_STEP_4 0x0002
451 #define UART_RATE_STEP_COUNT 0x0003 /* baud = clock/UART_RATE_STEP_COUNT */
452 #define UART_STEP_COUNT_MASK 0x00ff
453 #define UART_SAMPLE_COUNT_MASK 0x00ff
454#endif /*DRV_UART_6205B_REG, DRV_UART_BASIC_REG*/
455
456//FCR
457#define UART_FCR_FIFOEN 0x0001
458#define UART_FCR_CLRR 0x0002
459#define UART_FCR_CLRT 0x0004
460#define UART_FCR_FIFOINI 0x0007
461#define UART_FCR_RX1Byte_Level 0x0000
462#define UART_FCR_RX16Byte_Level 0x0040
463#define UART_FCR_RX32Byte_Level 0x0080
464#define UART_FCR_RX62Byte_Level 0x00c0
465
466#define UART_FCR_TX1Byte_Level 0x0000
467#define UART_FCR_TX16Byte_Level 0x0010
468#define UART_FCR_TX32Byte_Level 0x0020
469#define UART_FCR_TX62Byte_Level 0x0030
470#if ( (defined(SLEEP_DONT_CARE_DBG_INFO)) || (!defined(__MTK_INTERNAL__)) )
471 #if defined(DRV_UART_6205_REG) || defined(FPGA)
472 #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX1Byte_Level | UART_FCR_FIFOINI)
473 #define UART_FCR_RX_Normal (UART_FCR_RX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
474 #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
475 #define UART1_TxFIFO_DEPTH 16
476 #define UART1_RxFIFO_DEPTH 16
477 #define UART2_TxFIFO_DEPTH 4
478 #define UART2_RxFIFO_DEPTH 16
479 #endif /*DRV_UART_6205B_REG,FPGA*/
480
481 #if defined(DRV_UART_BASIC_REG)
482 #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI)
483 #define UART_FCR_RX_Normal (UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
484 #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
485 #define UART1_TxFIFO_DEPTH 16
486 #define UART1_RxFIFO_DEPTH 24
487 #define UART2_TxFIFO_DEPTH 4
488 #define UART2_RxFIFO_DEPTH 24
489 #if defined(DRV_UART_FIFO_FLOW_CONTROL) //Use larger size of RX FIFO, because it can trigger flow control
490 #define UART_VFIFO_DEPTH (UART_FCR_FIFOINI | UART_FCR_RX16Byte_Level)
491 #else
492 #define UART_VFIFO_DEPTH 7
493 #endif
494 #endif /*DRV_UART_BASIC_REG*/
495
496 #ifdef DRV_UART_6205B_REG
497 #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI)
498 #define UART_FCR_RX_Normal (UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
499 #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
500 #define UART1_TxFIFO_DEPTH 16
501 #define UART1_RxFIFO_DEPTH 24
502 #define UART2_TxFIFO_DEPTH 4
503 #define UART2_RxFIFO_DEPTH 24
504 #endif /*DRV_UART_6205B_REG*/
505
506 #ifdef DRV_UART_6208_REG
507 #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX32Byte_Level | UART_FCR_FIFOINI)
508 #define UART_FCR_RX_Normal (UART_FCR_RX32Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
509 #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
510 #define UART_TxFIFO_DEPTH 64
511 #define UART_RxFIFO_DEPTH 32
512 #endif /*DRV_UART_6208_REG*/
513#else /*!SLEEP_DONT_CARE_DBG_INFO*/
514 #if defined(DRV_UART_6205_REG) || defined(FPGA)
515 #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX1Byte_Level | UART_FCR_FIFOINI)
516 #define UART_FCR_RX_Normal (UART_FCR_RX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
517 #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
518 #define UART1_TxFIFO_DEPTH 16
519 #define UART1_RxFIFO_DEPTH 16
520 #define UART2_TxFIFO_DEPTH 4
521 #define UART2_RxFIFO_DEPTH 16
522 #endif /*DRV_UART_6205_REG,FPGA*/
523
524 #if defined(DRV_UART_BASIC_REG)
525 #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI)
526 #define UART_FCR_RX_Normal (UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
527 #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
528 #define UART1_TxFIFO_DEPTH 16
529 #define UART1_RxFIFO_DEPTH 24
530 #define UART2_TxFIFO_DEPTH 4
531 #define UART2_RxFIFO_DEPTH 24
532 #if defined(DRV_UART_FIFO_FLOW_CONTROL) //Use larger size of RX FIFO, because it can trigger flow control
533 #define UART_VFIFO_DEPTH (UART_FCR_FIFOINI | UART_FCR_RX16Byte_Level)
534 #else
535 #define UART_VFIFO_DEPTH 7
536 #endif
537 #endif /*DRV_UART_BASIC_REG*/
538
539 #ifdef DRV_UART_6205B_REG
540 #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI)
541 #define UART_FCR_RX_Normal (UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
542 #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
543 #define UART1_TxFIFO_DEPTH 16
544 #define UART1_RxFIFO_DEPTH 24
545 #define UART2_TxFIFO_DEPTH 4
546 #define UART2_RxFIFO_DEPTH 24
547 #endif /*DRV_UART_6205B_REG*/
548
549 #ifdef DRV_UART_6208_REG
550 #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX32Byte_Level | UART_FCR_FIFOINI)
551 #define UART_FCR_RX_Normal (UART_FCR_RX32Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
552 #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
553 #define UART_TxFIFO_DEPTH 64
554 #define UART_RxFIFO_DEPTH 32
555 #endif /*DRV_UART_6208_REG*/
556#endif /*SLEEP_DONT_CARE_DBG_INFO*/
557
558//IIR,RO
559#define UART_IIR_INT_INVALID 0x0001
560#define UART_IIR_RLS 0x0006 // Receiver Line Status
561#define UART_IIR_RDA 0x0004 // Receive Data Available
562#define UART_IIR_CTI 0x000C // Character Timeout Indicator
563#define UART_IIR_THRE 0x0002 // Transmit Holding Register Empty
564#define UART_IIR_MS 0x0000 // Check Modem Status Register
565#define UART_IIR_SWFlowCtrl 0x0010 // Receive XOFF characters
566#define UART_IIR_HWFlowCtrl 0x0020 // CTS or RTS Rising Edge
567#define UART_IIR_FIFOS_ENABLED 0x00c0
568#define UART_IIR_NO_INTERRUPT_PENDING 0x0001
569#define UART_IIR_INT_MASK 0x001f
570
571//===============================LCR================================
572//WLS
573#define UART_WLS_8 0x0003
574#define UART_WLS_7 0x0002
575#define UART_WLS_6 0x0001
576#define UART_WLS_5 0x0000
577#define UART_DATA_MASK 0x0003
578
579//Parity
580#define UART_NONE_PARITY 0x0000
581#define UART_ODD_PARITY 0x0008
582#define UART_EVEN_PARITY 0x0018
583#define UART_MARK_PARITY 0x0028
584#define UART_SPACE_PARITY 0x0038
585#define UART_PARITY_MASK 0x0038
586
587//Stop bits
588#define UART_1_STOP 0x0000
589#define UART_1_5_STOP 0x0004 // Only valid for 5 data bits
590#define UART_2_STOP 0x0004
591#define UART_STOP_MASK 0x0004
592
593#define UART_LCR_DLAB 0x0080
594#define UART_LCR_BREAK 0x0040
595//===============================LCR================================
596
597//MCR
598#define UART_MCR_DTR 0x0001
599#define UART_MCR_RTS 0x0002
600#define UART_MCR_LOOPB 0x0010
601#define UART_MCR_IRE 0x0040 //Enable IrDA modulation/demodulation
602#define UART_MCR_XOFF 0x0080
603#define UART_MCR_Normal (UART_MCR_DTR | UART_MCR_RTS)
604#define UART_MCR_DCM_EN 0x0020
605
606
607//LSR
608#define UART_LSR_DR 0x0001
609#define UART_LSR_OE 0x0002
610#define UART_LSR_PE 0x0004
611#define UART_LSR_FE 0x0008
612#define UART_LSR_BI 0x0010
613#define UART_LSR_THRE 0x0020
614#define UART_LSR_TEMT 0x0040
615#define UART_LSR_FIFOERR 0x0080
616
617//MSR
618#define UART_MSR_DCTS 0x0001
619#define UART_MSR_DDSR 0x0002
620#define UART_MSR_TERI 0x0004
621#define UART_MSR_DDCD 0x0008
622#define UART_MSR_CTS 0x0010
623#define UART_MSR_DSR 0x0020
624#define UART_MSR_RI 0x0040
625#define UART_MSR_DCD 0x0080
626
627//DLL
628//DLM
629//EFR
630#define UART_EFR_AutoCTS 0x0080
631#define UART_EFR_AutoRTS 0x0040
632#define UART_EFR_Enchance 0x0010
633#define UART_EFR_SWCtrlMask 0x000f
634#define UART_EFR_NoSWFlowCtrl 0x0000
635#define UART_EFR_ALLOFF 0x0000
636#define UART_EFR_AutoRTSCTS 0x00c0
637
638#if defined(DRV_UART_FIFO_FLOW_CONTROL) //add 0x10 RX FIFO flow control in all values.
639//Tx/Rx XON1/Xoff1 as flow control word
640#define UART_EFR_SWFlowCtrlX1 0x001a
641//Tx/Rx XON2/Xoff2 as flow control word
642#define UART_EFR_SWFlowCtrlX2 0x0015
643//Tx/Rx XON1&XON2/Xoff1&Xoff2 as flow control word
644#define UART_EFR_SWFlowCtrlXAll 0x001f
645#else //#if defined(DRV_UART_FIFO_FLOW_CONTROL)
646#define UART_EFR_SWFlowCtrlX1 0x000a
647#define UART_EFR_SWFlowCtrlX2 0x0005
648#define UART_EFR_SWFlowCtrlXAll 0x000f
649#endif//#if defined(DRV_UART_FIFO_FLOW_CONTROL)
650
651/*AutoBaud*/
652#if defined(DRV_UART_BASIC_REG)
653#define AUTOBAUD_EN 0x1
654#define AUTOBAUDSAMPLE_13M 0x6
655#define AUTOBAUDSAMPLE_26M 0xd
656#define AUTOBAUDSAMPLE_52M 0x1b
657#define AUTOBAUDSAMPLE_15_36M 0x7
658#define AUTOBAUDSAMPLE_30_72M 0xf
659#define AUTOBAUDSAMPLE_61_44M 0x1f
660#endif /*MDRV_UART_BASIC_REG*/
661
662#if defined(DRV_UART_VFIFO_EN_REG)
663 #if defined(DRV_UART_DMA_EXTEND)
664#define UART_RX_DMA_EN 0x0001
665#define UART_TX_DMA_EN 0x0002
666#define UART_TO_CNT_AUTORST 0x0004
667#if defined(DRV_UART_DMA_INTERNAL_BUFFER_WORKAROUND) || defined( DRV_UART_NEW_UART_AND_OLG_DMA )
668#define UART_TXRXDMA_ON 0x0003
669#else
670#define UART_TXRXDMA_ON 0x0007
671#endif
672 #else
673#define UART_TXRXDMA_ON 0x0001
674 #endif
675#define UART_TXRXDMA_OFF 0x0000
676#endif /*DRV_UART_VFIFO_EN_REG*/
677
678
679#if defined(DRV_UART_AUTOBAUD_61M)
680 #if defined(MCU_650M) || defined(MCU_611M) || defined(MCU_520M)||defined(MCU_416M)//add 416M for 76M
681#define UART_RATE_FIX 0x1f
682#define UART_RATE_UNFIX 0x10
683 #else
684#define UART_RATE_FIX 0xf
685#define UART_RATE_UNFIX 0x0
686 #endif
687#else
688#define UART_RATE_FIX 0xf
689#define UART_RATE_UNFIX 0x0
690#endif
691
692
693
694#define UART_RXTRI_VALUE 0x12
695#if defined(DRV_UART_VFIFO_V2)
696
697#ifdef DMA_POP
698#undef DMA_POP
699#endif
700
701#ifdef DMA_PUSH
702#undef DMA_PUSH
703#endif
704
705#define DMA_POP(_n) DRV_Reg8(DRV_Reg(DMA_VFF_RPT(_n))+DRV_Reg32(DMA_SRC(_n)));\
706 if(DRV_Reg(DMA_VFF_RPT(_n)) == (DRV_Reg(DMA_VFF_SIZE(_n))-1))\
707 DRV_WriteReg32(DMA_VFF_RPT(_n), (~DRV_Reg32(DMA_VFF_RPT(_n)))&0x10000);\
708 else \
709 DRV_WriteReg32(DMA_VFF_RPT(_n), DRV_Reg32(DMA_VFF_RPT(_n))+1);
710
711#define DMA_PUSH(_n,_data) while(DRV_Reg(DMA_W_INT_BUF_SIZE(_n))>=64);*(volatile kal_uint8*)DMA_VPORT(_n) = (kal_uint8)_data;
712#define DMA_PUSH32(_n,_data) while(DRV_Reg(DMA_W_INT_BUF_SIZE(_n))>60);*(volatile kal_uint32*)DMA_VPORT(_n) = (kal_uint32)_data;
713
714#endif //#if defined(DRV_UART_VFIFO_V2)
715
716#if defined(DRV_UART_VFIFO_V3)
717
718#ifdef DMA_POP
719#undef DMA_POP
720#endif
721
722#ifdef DMA_PUSH
723#undef DMA_PUSH
724#endif
725
726#define DMA_POP(_n) DRV_Reg8(DRV_Reg(DMA_VFF_RPT(_n))+DRV_Reg32(DMA_SRC(_n)));\
727 if(DRV_Reg(DMA_VFF_RPT(_n)) == (DRV_Reg(DMA_VFF_SIZE(_n))-1))\
728 DRV_WriteReg32(DMA_VFF_RPT(_n), (~DRV_Reg32(DMA_VFF_RPT(_n)))&0x10000);\
729 else \
730 DRV_WriteReg32(DMA_VFF_RPT(_n), DRV_Reg32(DMA_VFF_RPT(_n))+1);
731
732#define DMA_PUSH(_n,_data) \
733 DRV_WriteReg8(DRV_Reg(DMA_VFF_WPT(_n))+DRV_Reg32(DMA_SRC(_n)),_data);\
734 if(DRV_Reg(DMA_VFF_WPT(_n)) == (DRV_Reg(DMA_VFF_SIZE(_n))-1))\
735 DRV_WriteReg32(DMA_VFF_WPT(_n), (~DRV_Reg32(DMA_VFF_WPT(_n)))&0x10000);\
736 else \
737 DRV_WriteReg32(DMA_VFF_WPT(_n), DRV_Reg32(DMA_VFF_WPT(_n))+1);
738
739#endif //#if defined(DRV_UART_VFIFO_V3)
740
741
742
743#endif /*#if !defined(DRV_UART_OFF)*/
744#endif /*UART_HW_H*/
745
746