| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2016 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | #ifndef _CPH_COMMON_TXCRP_H_ |
| 36 | #define _CPH_COMMON_TXCRP_H_ |
| 37 | |
| 38 | typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| 39 | typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| 40 | typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| 41 | typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| 42 | typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| 43 | typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| 44 | typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| 45 | typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| 46 | typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| 47 | |
| 48 | #if defined(__MD93__)||defined(__MD95__) |
| 49 | #define TXCRP_INTERNAL_REG_BASE (0xA8170000) |
| 50 | #else |
| 51 | #define TXCRP_INTERNAL_REG_BASE (0xA8970000) |
| 52 | #endif |
| 53 | |
| 54 | #define MODE_SEL ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0000)) |
| 55 | #define CRC_EN ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0004)) |
| 56 | #define CRC_LENGTH ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0008)) |
| 57 | #define CRC_OUT ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x000C)) |
| 58 | #define CRC_MOD_SEL ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0010)) |
| 59 | #define TD_SW_TIMER_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0014)) |
| 60 | #define TD_SW_TIMER_CON ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0018)) |
| 61 | #define FDD_SW_TIMER_GTXCRP_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x001C)) |
| 62 | #define FDD_SW_TIMER_WTXHCH_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0020)) |
| 63 | #define FDD_SW_TIMER_WTXCQI_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0024)) |
| 64 | #define FDD_SW_TTR_GTXCRP_STR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0028)) |
| 65 | #define FDD_SW_TTR_WTXHCH_STR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x002C)) |
| 66 | #define FDD_SW_TTR_WTXCQI_STR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0030)) |
| 67 | #define FDD_SW_TTR_SLOT_CNT ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0034)) |
| 68 | #define C1X_SW_TIMER_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0038)) |
| 69 | #define C1X_SW_TIMER_CON ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x003C)) |
| 70 | #define WRBRPMEM_TEST_START ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0040)) |
| 71 | #define WRBRPMEM_TEST_NUM ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0044)) |
| 72 | #define DO_TRIGGER_SELECT ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x004C)) |
| 73 | #define DO_TIMER_TRIGGER ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0050)) |
| 74 | #define DO_KS_TRIGGER ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0054)) |
| 75 | #define DO_TX_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0058)) |
| 76 | #define TESTMODE_NUM ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x005C)) |
| 77 | #define TESTMODE_START ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0060)) |
| 78 | #define KS_SEL_CONFIG ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0064)) |
| 79 | #define MODE_SEL_ADDR_MIS ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0068)) |
| 80 | #define IRQ_MODE_SEL_ADDR_MIS_CLR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x006C)) |
| 81 | #define IRQ_MODE_CHANGE_CLR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0070)) |
| 82 | #define TXCRP_MODE_SETERR_CLR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0074)) |
| 83 | #define TXCRP_IRQ_STATUS ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0078)) |
| 84 | #define TXCRP_IRQ_MASK ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x007C)) |
| 85 | #define INFO_BRP_RU1_ADDR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0080)) |
| 86 | #define INFO_BRP_RU1 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0084)) |
| 87 | #define INFO_BRP_RU2_ADDR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x008C)) |
| 88 | #define INFO_BRP_RU2 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0090)) |
| 89 | #define DBG_BUS_SEL ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0094)) |
| 90 | #define DUMMY_CRP ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0098)) |
| 91 | #define RAKE_LOG_COUNTER ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x009C)) |
| 92 | #define RAKELOG_0 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00A0)) |
| 93 | #define RAKELOG_1 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00A4)) |
| 94 | #define RAKELOG_2 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00A8)) |
| 95 | #define RAKELOG_3 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00AC)) |
| 96 | #define RAKELOG_4 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00B0)) |
| 97 | #if defined(__MD97__) |
| 98 | #define TXCRP_KS0_TO_TPC ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x010C)) |
| 99 | #define TXCRP_KS1_TO_TPC ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0110)) |
| 100 | #endif |
| 101 | |
| 102 | #define MODE_SEL_LSB (0) |
| 103 | #define MODE_SEL_WIDTH (5) |
| 104 | #define MODE_SEL_MASK (0x0000001F) |
| 105 | |
| 106 | #define MODE_SEL_ADDR_MIS_LSB (0) |
| 107 | #define MODE_SEL_ADDR_MIS_WIDTH (1) |
| 108 | #define MODE_SEL_ADDR_MIS_MASK (0x00000001) |
| 109 | #define MODE_SEL_ADDR_MIS_BIT (0x00000001) |
| 110 | |
| 111 | #define MODE_SEL_ADDR_MIS_CLR_LSB (0) |
| 112 | #define MODE_SEL_ADDR_MIS_CLR_WIDTH (1) |
| 113 | #define MODE_SEL_ADDR_MIS_CLR_MASK (0x00000001) |
| 114 | #define MODE_SEL_ADDR_MIS_CLR_BIT (0x00000001) |
| 115 | |
| 116 | #define CRC_EN_LSB (0) |
| 117 | #define CRC_EN_WIDTH (1) |
| 118 | #define CRC_EN_MASK (0x00000001) |
| 119 | #define CRC_EN_BIT (0x00000001) |
| 120 | |
| 121 | #define CRC_LENGTH_LSB (0) |
| 122 | #define CRC_LENGTH_WIDTH (20) |
| 123 | #define CRC_LENGTH_MASK (0x000FFFFF) |
| 124 | |
| 125 | #define CRC_OUT_LSB (0) |
| 126 | #define CRC_OUT_WIDTH (32) |
| 127 | #define CRC_OUT_MASK (0xFFFFFFFF) |
| 128 | |
| 129 | #define INFO_RU1_ADDR_LSB (0) |
| 130 | #define INFO_RU1_ADDR_WIDTH (13) |
| 131 | #define INFO_RU1_ADDR_MASK (0x00001FFF) |
| 132 | |
| 133 | #define RU1_ADDR0_DATA_LSB (24) |
| 134 | #define RU1_ADDR0_DATA_WIDTH (8) |
| 135 | #define RU1_ADDR0_DATA_MASK (0xFF000000) |
| 136 | |
| 137 | #define RU1_ADDR1_DATA_LSB (16) |
| 138 | #define RU1_ADDR1_DATA_WIDTH (8) |
| 139 | #define RU1_ADDR1_DATA_MASK (0x00FF0000) |
| 140 | |
| 141 | #define RU1_ADDR2_DATA_LSB (8) |
| 142 | #define RU1_ADDR2_DATA_WIDTH (8) |
| 143 | #define RU1_ADDR2_DATA_MASK (0x0000FF00) |
| 144 | |
| 145 | #define RU1_ADDR3_DATA_LSB (0) |
| 146 | #define RU1_ADDR3_DATA_WIDTH (8) |
| 147 | #define RU1_ADDR3_DATA_MASK (0x000000FF) |
| 148 | |
| 149 | #define INFO_RU2_ADDR_LSB (0) |
| 150 | #define INFO_RU2_ADDR_WIDTH (13) |
| 151 | #define INFO_RU2_ADDR_MASK (0x00001FFF) |
| 152 | |
| 153 | #define RU2_ADDR0_DATA_LSB (24) |
| 154 | #define RU2_ADDR0_DATA_WIDTH (8) |
| 155 | #define RU2_ADDR0_DATA_MASK (0xFF000000) |
| 156 | |
| 157 | #define RU2_ADDR1_DATA_LSB (16) |
| 158 | #define RU2_ADDR1_DATA_WIDTH (8) |
| 159 | #define RU2_ADDR1_DATA_MASK (0x00FF0000) |
| 160 | |
| 161 | #define RU2_ADDR2_DATA_LSB (8) |
| 162 | #define RU2_ADDR2_DATA_WIDTH (8) |
| 163 | #define RU2_ADDR2_DATA_MASK (0x0000FF00) |
| 164 | |
| 165 | #define RU2_ADDR3_DATA_LSB (0) |
| 166 | #define RU2_ADDR3_DATA_WIDTH (8) |
| 167 | #define RU2_ADDR3_DATA_MASK (0x000000FF) |
| 168 | |
| 169 | #define DBG_BUS_SEL_LSB (0) |
| 170 | #define DBG_BUS_SEL_WIDTH (4) |
| 171 | #define DBG_BUS_SEL_MASK (0x0000000F) |
| 172 | |
| 173 | #define CRP_LSB (0) |
| 174 | #define CRP_WIDTH (32) |
| 175 | #define CRP_MASK (0xFFFFFFFF) |
| 176 | |
| 177 | #endif //#ifndef _CPH_COMMON_TXCRP_H_ |