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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / interface / l1 / gl1 / external / l1d_public.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
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14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
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22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
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24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
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28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
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32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*******************************************************************************
37 *
38 * Filename:
39 * ---------
40 * l1d_public.h
41 *
42 * Project:
43 * --------
44 * TK6291 Project
45 *
46 * Description:
47 * ------------
48 * The structure definition of L1 calibration data
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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183 *------------------------------------------------------------------------------
184 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
185 *============================================================================
186 ****************************************************************************/
187#ifndef L1D_PUBLIC_H
188#define L1D_PUBLIC_H
189
190#include "l1d_cid.h"
191#include "l1cal.h"
192#include "l1d_rf_common.h"
193#include "l1_types_public.h"
194
195
196/* ------------------------------------------------------------------------- */
197
198/* moved from l1d_data_l1core.h */
199#if IS_AST_B2S_SUPPORT
200#define TQ_AFC_READY 245
201#define TQ_AFC_READY_RX 213
202#else
203#define TQ_AFC_READY 256
204#define TQ_AFC_READY_RX TQ_AFC_READY
205#endif
206
207#if L1D_PM_ENHANCE
208#define TQ_PM_WIN_OFF_MARGIN 8
209#endif
210
211/* ------------------------------------------------------------------------- */
212/* moved from l1d_custom_rf.h */
213#define SECONDS2FRAME(n) ((int)((n)*1000000/4615))
214#define VOLT2UVOLT(n) ((int)((n)*1000000))
215#define TEMP2MTEMP(n) ((int)((n)*1000))
216
217/* ------------------------------------------------------------------------- */
218 /* !!important: please align the setting in L1_const.h */
219#define RSSI_RESOLUTION_BITS 3 /* 0.125 dB resolution */
220#define RSSI_FACTOR (1<<RSSI_RESOLUTION_BITS)
221
222// moved from m12190_l1core.h
223#ifndef _L1D_DATA_L1CORE_H_
224#define PWRRES_BIT RSSI_RESOLUTION_BITS
225#define PWRRES RSSI_FACTOR
226#endif
227
228#define PWROFFSET(n) ((signed char)((n)*(1<<2))) /* rx power offset resolution = 0.25 dB */
229#define GAINLOSS( n ) ((signed char)((n)*PWRRES))
230#define WEIGHT(n) ((unsigned short)((n)*(1<<14)))
231#define TABLE_END (unsigned short)0xFFFF
232/* ------------------------------------------------------------------------- */
233/* moved from m12197_l1core.h */
234#define RFDEF 0xABCD
235#define RFDEF_short 0xAB
236
237/* ------------------------------------------------------------------------- */
238
239extern intx afc_inv_slope;
240
241#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
242extern int32 afc_dac_default;
243extern const int32 afc_dac_initial;
244#else
245extern int16 afc_dac_default;
246
247extern const int16 afc_dac_initial;
248#endif /* IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT */
249
250extern long XO_CapID;
251
252extern sAGCGAINOFFSET* AGC_PATHLOSS_TABLE[FrequencyBandCount];
253
254extern sLNAGAINOFFSET* LNA_PATHLOSS_TABLE[FrequencyBandCount];
255
256#if IS_2G_RXD_SUPPORT
257extern sAGCGAINOFFSET* AGC_PATHLOSS_RXD_TABLE[FrequencyBandCount];
258
259extern sLNAGAINOFFSET* LNA_PATHLOSS_RXD_TABLE[FrequencyBandCount];
260extern L1D_CUSTOM_RAS_NVRAM_T L1_RAS_Custom_NVRAM;
261#endif
262
263extern sRAMPDATA* RampData[FrequencyBandCount];
264
265#if IS_EPSK_TX_SUPPORT
266extern sRAMPDATA* RampData_EPSK[FrequencyBandCount];
267#endif
268
269extern sMIDRAMPDATA* InterRampData[FrequencyBandCount];
270
271#if IS_EPSK_TX_SUPPORT
272extern sMIDRAMPDATA** EPSK_InterRampData[5];
273#endif
274
275extern sBBTXParameters BBTXParameters;
276
277#if IS_GPRS
278extern sTX_POWER_ROLLBACK* tx_power_rollback_gmsk[FrequencyBandCount];
279 #if IS_EGPRS
280extern sTX_POWER_ROLLBACK* tx_power_rollback_epsk[FrequencyBandCount];
281 #endif
282#endif
283
284#if IS_TX_POWER_CONTROL_SUPPORT
285extern char is_txpc_calibrated;
286 #if IS_TXPC_CL_AUXADC_SUPPORT || IS_TXPC_CL_BSI_SUPPORT
287extern sTXPC_ADCDATA* TXADC_Data[FrequencyBandCount];
288extern sTXPC_TEMPDATA* TXTEMP_Data[FrequencyBandCount];
289 #if IS_EPSK_TX_SUPPORT
290extern sTXPC_ADCDATA* TXADC_Data_EPSK[FrequencyBandCount];
291extern sTXPC_TEMPDATA* TXTEMP_Data_EPSK[FrequencyBandCount];
292 #endif
293 #endif /* IS_TXPC_CL_AUXADC_SUPPORT || IS_TXPC_CL_BSI_SUPPORT */
294 #if IS_TXPC_OL_BSI_SUPPORT || IS_TXPC_OL_AUXADC_SUPPORT
295extern short ref_temperature;
296 #endif
297#endif /* IS_TX_POWER_CONTROL_SUPPORT */
298
299extern sTXPC_TEMPDATA TEMP_DAC;
300
301#if IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2
302extern sL1D_RF_CUSTOM_INPUT_DATA l1d_rf_custom_input_data;
303#endif
304
305extern sTXGAIN_RFDATA* GAIN_RF_TABLE[FrequencyBandCount];
306
307#if IS_CHIP_MT6297_AND_LATTER_VERSION
308//none
309#elif IS_MIPI_SUPPORT
310 #if IS_2G_TAS_SUPPORT
311extern sGGE_TAS_MIPI_RTXCTRL_TABLE* GGE_TAS_MIPI_CTRL_TABLE[FrequencyBandCount][L1D_TAS_STATE_NUM];
312 #endif
313
314 #if IS_2G_DAT_SUPPORT
315extern sGGE_DAT_MIPI_RTXCTRL_TABLE* GGE_DAT_MIPI_CTRL_TABLE[FrequencyBandCount][L1D_DAT_STATE_NUM];
316 #endif
317
318extern sGGE_MIPI_CTRL_TABLE_BAND* GGE_MIPI_CTRL_TABLE[FrequencyBandCount];
319extern sGGE_MIPIEVENT* GGE_MIPI_CTRL_TABLE_RX_EVENT[FrequencyBandCount];
320extern sGGE_MIPIEVENT* GGE_MIPI_CTRL_TABLE_TX_EVENT[FrequencyBandCount];
321extern sGGE_MIPIEVENT* GGE_MIPI_CTRL_TABLE_TXMID_EVENT[FrequencyBandCount];
322extern sGGE_MIPIDATA_SUBBAND* GGE_MIPI_CTRL_TABLE_RX_DATA[FrequencyBandCount];
323extern sGGE_MIPIDATA_SUBBAND* GGE_MIPI_CTRL_TABLE_TX_DATA[FrequencyBandCount];
324extern sGGE_MIPIPADATA* GGE_MIPI_CTRL_TABLE_PA_DATA[FrequencyBandCount];
325extern sGGE_MIPIDATA_SUBBAND* GGE_MIPI_CTRL_TABLE_TXMID_DATA[FrequencyBandCount];
326#endif
327
328#if IS_TX_POWER_OFFSET_SUPPORT
329
330extern sTX_POWER_OFFSET* Tx_Power_Offset_GMSK[FrequencyBandCount];
331extern sTX_POWER_OFFSET* Tx_Power_Offset_EPSK[FrequencyBandCount];
332#endif
333
334#if IS_RX_POWER_OFFSET_SUPPORT
335extern s2G_RF_RX_PARAMETER_EXT* AGCLNA_PL_OFFSET_SETTING;
336extern sAGCLNAGAINOFFSET* AGCLNA_PATHLOSS_OFFSET[FrequencyBandCount];
337 #if IS_2G_RXD_SUPPORT
338extern sAGCLNAGAINOFFSET* AGCLNA_PATHLOSS_RXD_OFFSET[FrequencyBandCount];
339 #endif
340#endif/*IS_RX_POWER_OFFSET_SUPPORT*/
341
342#if IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT
343extern sNSFT_ADJUST_TPO* Adjust_TPO_GMSK[FrequencyBandCount];
344 #if IS_EPSK_ADJUST_TPO_SUPPORT
345extern sNSFT_ADJUST_TPO* Adjust_TPO_EPSK[FrequencyBandCount];
346 #endif//IS_EPSK_ADJUST_TPO_SUPPORT
347#endif//IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT
348
349#if (IS_2G_TAS_SUPPORT || IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT)
350extern L1D_CUSTOM_TAS_NVRAM_T L1_TAS_Custom_NVRAM;
351 #if IS_2G_TAS_SUPPORT || IS_2G_Gen95_UTAS_SUPPORT /*Not supported for Gen97*/
352extern L1D_CUSTOM_TAS_FE_NVRAM_T L1_TAS_Custom_FE_NVRAM;
353 #endif
354 #if (IS_2G_TAS_INHERIT_4G_ANT)
355extern L1D_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_T L1_TAS_Custom_InheritLteAntTable;
356 #endif
357#endif
358
359#if IS_2G_DAT_SUPPORT || IS_2G_Gen95_UDAT_SUPPORT || IS_2G_Gen97_UDAT_SUPPORT
360extern L1D_CUSTOM_DAT_FE_ROUTE_NVRAM_T L1_DAT_Custom_FE_ROUTE_NVRAM;
361 #if IS_2G_DAT_SUPPORT
362extern L1D_CUSTOM_DAT_FE_CAT_A_NVRAM_T L1_DAT_Custom_FE_CAT_A_NVRAM;
363extern L1D_CUSTOM_DAT_FE_CAT_B_NVRAM_T L1_DAT_Custom_FE_CAT_B_NVRAM;
364 #endif
365#endif
366
367#if IS_ANT_RXPWR_OFFSET_SUPPORT
368extern sL1D_ANT_RxPWR_Offset_T L1D_ANT_RxPWR_Offset_NVRAM;
369#endif
370
371#if IS_2G_DYNAMIC_HW_CLOCK_SUPPORT
372extern L1D_RF_INTERFERENCE_ARFCN_INDICATION_T L1_Custom_HW_CLK_NVRAM;
373#endif
374
375extern sl1CustomBandSupport l1d_custom_band_support;
376
377#if IS_SAR_TX_POWER_BACKOFF_SUPPORT
378extern L1D_CUSTOM_SAR_TX_BACKOFF_DB_NVRAM_T L1_Custom_SAR_TX_BACKOFF_DB_NVRAM;
379#endif
380
381/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
382#endif /* End of L1D_PUBLIC_H */