| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | #ifndef _IDC_L5_ENUM_H |
| 2 | #define _IDC_L5_ENUM_H |
| 3 | |
| 4 | #if defined(CHIP10992) || defined(__NANO_UT__) |
| 5 | |
| 6 | typedef enum |
| 7 | { |
| 8 | |
| 9 | IDC_LAA_RESTRICTED_POSSIBLE = 0, |
| 10 | IDC_LAA_RESTRICTED_IMPOSSIBLE = 1, |
| 11 | IDC_LAA_RESTRICTED_INVALID = 2 |
| 12 | }idc_laa_restricted_enum; |
| 13 | |
| 14 | typedef enum |
| 15 | { |
| 16 | IDC_DYNAMIC_SET_MODE_DISABLE = 0, //disable unsolicited ntf |
| 17 | IDC_DYNAMIC_SET_MODE_ENABLE = 1, //enable unsolicited ntf |
| 18 | IDC_DYNAMIC_SET_MODE_CONFIG = 2, //config mode via MBIM (Intel) |
| 19 | IDC_DYNAMIC_SET_MODE_CONFIG_BY_MIPC = 3, //config mode via MIPC (Quanta) |
| 20 | IDC_DYNAMIC_SET_MODE_INVALID = 0x7FFFFFFF |
| 21 | }idc_dynamic_set_mode_enum; |
| 22 | |
| 23 | typedef enum |
| 24 | { |
| 25 | IDC_FILTER_TYPE_RX = 0, |
| 26 | IDC_FILTER_TYPE_TX = 1, |
| 27 | IDC_FILTER_TYPE_NUM = 2 |
| 28 | }idc_filter_type_enum; |
| 29 | |
| 30 | typedef enum |
| 31 | { |
| 32 | IDC_CNF_STATUS_SUCCESS = 0, |
| 33 | IDC_CNF_STATUS_FAILURE = 1, |
| 34 | IDC_CNF_STATUS_INVALID = 2 |
| 35 | } idc_cnf_status_enum; |
| 36 | |
| 37 | typedef enum |
| 38 | { |
| 39 | IDC_MBIM_CFG_TYPE_DEFAULT = 0, |
| 40 | IDC_MBIM_CFG_TYPE_SET = 1, |
| 41 | IDC_MBIM_CFG_TYPE_QUERY = 2, |
| 42 | IDC_MBIM_CFG_TYPE_NTF = 3, |
| 43 | IDC_MBIM_CFG_TYPE_NUM = 4 |
| 44 | } l5_idc_mbim_cfg_type_enum; |
| 45 | |
| 46 | #endif |
| 47 | #endif |