rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | #ifndef _IDC_NL1RX_STR_H |
| 2 | #define _IDC_NL1RX_STR_H |
| 3 | |
| 4 | #include "kal_general_types.h" |
| 5 | #include "kal_public_defs.h" |
| 6 | #include "global_type.h" |
| 7 | #include "idc_nr_def.h" |
| 8 | #include "idc_nl1rx_enum.h" |
| 9 | #include "nl1_comm_internal_inter_core_public.h" |
| 10 | |
| 11 | typedef struct _idc_nr_time_struct |
| 12 | { |
| 13 | kal_uint64 absTime; |
| 14 | kal_uint32 sfbdTime; |
| 15 | kal_uint16 sfn; |
| 16 | kal_uint8 sf; |
| 17 | }idc_nr_time_struct; |
| 18 | |
| 19 | typedef struct _nl1_idc_rx_quality_rpt_struct |
| 20 | { |
| 21 | NL1_SIM_IDX_E sim_index; |
| 22 | kal_uint8 cc_valid_bmp; |
| 23 | kal_int16 os_snr[IDC_NR_CC_NUM]; |
| 24 | kal_int16 ar_snr[IDC_NR_CC_NUM]; |
| 25 | kal_int16 ma_rsrp[IDC_NR_CC_NUM]; |
| 26 | }nl1_idc_rx_quality_rpt_struct; |
| 27 | |
| 28 | typedef struct _nl1_ctrl_idc_freq_ntf_struct |
| 29 | { |
| 30 | LOCAL_PARA_HDR |
| 31 | |
| 32 | nl1_ctrl_idc_duplex_mode_enum duplexMode[IDC_NR_CC_NUM]; |
| 33 | |
| 34 | kal_uint8 srvNum; |
| 35 | kal_uint16 band[IDC_NR_CC_NUM]; |
| 36 | #if ((defined(__IDC_ENABLED__)) && (defined (__IDC_NRTC_ENABLE__))) |
| 37 | nl1_idc_power_class_enum powerclass[IDC_NR_CC_NUM]; |
| 38 | #endif |
| 39 | kal_uint32 dlBw[IDC_NR_CC_NUM][MAX_BWP_NUM]; |
| 40 | kal_uint32 ulBw[IDC_NR_CC_NUM][MAX_BWP_NUM]; |
| 41 | kal_uint32 dlFreq[IDC_NR_CC_NUM][MAX_BWP_NUM]; |
| 42 | kal_uint32 ulFreq[IDC_NR_CC_NUM][MAX_BWP_NUM]; |
| 43 | kal_uint32 dlARFCN[IDC_NR_CC_NUM][MAX_BWP_NUM]; |
| 44 | kal_uint32 ulARFCN[IDC_NR_CC_NUM][MAX_BWP_NUM]; |
| 45 | }nl1_ctrl_idc_freq_ntf_struct; |
| 46 | |
| 47 | typedef struct _nl1_ctrl_idc_frame_cfg_ntf_struct |
| 48 | { |
| 49 | LOCAL_PARA_HDR |
| 50 | |
| 51 | kal_uint8 srv_num; |
| 52 | kal_uint8 frame_cfg_num[IDC_NR_CC_NUM]; |
| 53 | kal_uint16 dlSlots[IDC_NR_CC_NUM][NR_MAX_FRAME_CFG]; |
| 54 | kal_uint16 flexibleSymbols[IDC_NR_CC_NUM][NR_MAX_FRAME_CFG]; |
| 55 | kal_uint16 ulSlots[IDC_NR_CC_NUM][NR_MAX_FRAME_CFG]; |
| 56 | kal_uint16 period[IDC_NR_CC_NUM][NR_MAX_FRAME_CFG]; |
| 57 | }nl1_ctrl_idc_frame_cfg_ntf_struct; |
| 58 | |
| 59 | typedef struct _nl1_ctrl_idc_sch_ntf_struct |
| 60 | { |
| 61 | LOCAL_PARA_HDR |
| 62 | |
| 63 | kal_bool enterSch; |
| 64 | }nl1_ctrl_idc_sch_ntf_struct; |
| 65 | |
| 66 | typedef struct _nl1_ctrl_idc_bwp_ntf_struct |
| 67 | { |
| 68 | LOCAL_PARA_HDR |
| 69 | |
| 70 | kal_uint8 dl_actv_bwp_index[IDC_NR_CC_NUM]; |
| 71 | kal_uint8 ul_actv_bwp_index[IDC_NR_CC_NUM]; |
| 72 | }nl1_ctrl_idc_bwp_ntf_struct; |
| 73 | |
| 74 | typedef struct _nl1_sched_idc_scell_actv_ntf_struct |
| 75 | { |
| 76 | LOCAL_PARA_HDR |
| 77 | |
| 78 | kal_uint32 srvActvBmp; |
| 79 | }nl1_sched_idc_scell_actv_ntf_struct; |
| 80 | |
| 81 | typedef struct _nl1_ctrl_idc_drx_config_ntf_struct |
| 82 | { |
| 83 | LOCAL_PARA_HDR |
| 84 | |
| 85 | kal_bool isNoDRX; |
| 86 | kal_uint32 onDuration; |
| 87 | kal_uint32 startOffst; |
| 88 | kal_uint32 shortDRXCycle; |
| 89 | kal_uint32 longDRXCycle; |
| 90 | nl1_ctrl_idc_drx_type_enum drxType; |
| 91 | }nl1_ctrl_idc_drx_config_ntf_struct; |
| 92 | |
| 93 | typedef struct _nl1_ctrl_idc_ho_ntf_struct |
| 94 | { |
| 95 | LOCAL_PARA_HDR |
| 96 | |
| 97 | kal_bool isHO; |
| 98 | }nl1_ctrl_idc_ho_ntf_struct; |
| 99 | |
| 100 | typedef struct _idc_nl1_sched_rx_protect_status_struct |
| 101 | { |
| 102 | NL1_SIM_IDX_E sim_index; |
| 103 | kal_bool active; |
| 104 | kal_uint8 ccIndex; |
| 105 | kal_uint32 freq; |
| 106 | idc_nl1_sched_rx_protect_type_enum type; |
| 107 | }idc_nl1_sched_rx_protect_status_struct; |
| 108 | |
| 109 | typedef struct _nl1_sched_idc_psim_swap_req_struct |
| 110 | { |
| 111 | LOCAL_PARA_HDR |
| 112 | |
| 113 | kal_uint8 new_psim_index; |
| 114 | }nl1_sched_idc_psim_swap_req_struct; |
| 115 | |
| 116 | typedef struct _idc_nl1_sched_rx_gap_req_struct |
| 117 | { |
| 118 | NL1_SIM_IDX_E sim_idx; |
| 119 | kal_uint8 seq_num; |
| 120 | idc_nl1_sched_rx_status_enum rx_status[IDC_NR_CC_NUM]; |
| 121 | }idc_nl1_sched_rx_gap_req_struct; |
| 122 | |
| 123 | typedef struct _nl1_sched_idc_rx_gap_susp_cnf_struct |
| 124 | { |
| 125 | LOCAL_PARA_HDR |
| 126 | |
| 127 | kal_uint8 ack_num; |
| 128 | nl1_sched_idc_cnf_status_enum cnf_status; |
| 129 | }nl1_sched_idc_rx_gap_susp_cnf_struct; |
| 130 | |
| 131 | typedef struct _nl1_ctrl_idc_actv_ntf_struct |
| 132 | { |
| 133 | LOCAL_PARA_HDR |
| 134 | |
| 135 | nl1_rat_status_enum nr_rat_status; |
| 136 | nl1_rat_set_cause_enum cause; |
| 137 | }nl1_ctrl_idc_actv_ntf_struct; |
| 138 | |
| 139 | typedef struct _idc_nl1_sched_psim_swap_cnf_struct |
| 140 | { |
| 141 | LOCAL_PARA_HDR |
| 142 | |
| 143 | kal_uint8 sim_index; |
| 144 | }idc_nl1_sched_psim_swap_cnf_struct; |
| 145 | |
| 146 | #if ((defined(__IDC_ENABLED__)) && (defined (__IDC_NRTC_ENABLE__))) |
| 147 | typedef struct _idc_nl1_nrtc_tx_power_breach_threshold_ind_struct |
| 148 | { |
| 149 | LOCAL_PARA_HDR |
| 150 | kal_uint8 cc_idx; |
| 151 | kal_bool breachThreshold; |
| 152 | }idc_nl1_nrtc_tx_power_breach_threshold_ind_struct; |
| 153 | #endif |
| 154 | |
| 155 | #endif |