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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / interface / l1 / tl1 / tl1_cnst.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2009
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
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32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
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34*****************************************************************************/
35
36/******************************************************************************
37 * Filename:
38 * --------------------------------------------------------
39 * tl1_cnst.h
40 *
41 * Project:
42 * --------------------------------------------------------
43 *
44 *
45 * Description:
46 * --------------------------------------------------------
47 *
48 *
49 * Author:
50 * --------------------------------------------------------
51 * -------
52 *
53 * --------------------------------------------------------
54 * $Log$
55 *
56 * 10 31 2018 xiaochi.zhang
57 * [MOLY00361478] [Gen97] Gemini Compile Option Clean Up
58 *
59 * .
60 *
61 * 05 23 2018 cruze.yu
62 * [MOLY00285698] [93/95 re-arch][TL1] tl1 option clean
63 *
64 * .
65 *
66 * 04 12 2017 weimin.zeng
67 * [MOLY00240270] [6293][Gemini][T+W] Phase 1: Common Interface Changes Check in
68 *
69 * , 3G TDD UMAC PCH buffer.
70 *
71 * 01 13 2017 weimin.zeng
72 * [MOLY00224780] [MT6293][UMOLYA][UMAC] memory shrink.
73 *
74 * .
75 *
76 * 04 29 2015 rong.yang
77 * [MOLY00109047] [UMOLY][new feature] Pich false alarm Optimization
78 * .
79 *
80 * 03 11 2015 marco.zhang
81 * [MOLY00086950] UMOLY TL1 MAINTAIN
82 * __MAC_EHS_SUPPORT__ update to __TDD_MAC_EHS_SUPPORT__.
83 *
84 * 03 04 2015 chengwei.liu
85 * [MOLY00093594] [TK6291][3G TDD][FPGA DVT][MD8470][UPA.001.001]PING ²»Í¨
86 * .
87 *
88 * 12 29 2014 marco.zhang
89 * [MOLY00086950] UMOLY TL1 MAINTAIN
90 * build error.
91 *
92 * 12 29 2014 marco.zhang
93 * [MOLY00086950] UMOLY TL1 MAINTAIN
94 * .
95 *
96 * 12 23 2014 marco.zhang
97 * [MOLY00086950] UMOLY TL1 MAINTAIN
98 * .
99 *
100 * 12 21 2014 marco.zhang
101 * [MOLY00086950] UMOLY TL1 MAINTAIN
102 * prefix.
103 *
104 * 12 11 2014 rong.yang
105 * [MOLY00086950] UMOLY TL1 MAINTAIN
106 * .revise umac part about shared memory on tl1_ps_shared_mem.h/.c
107 *
108 * 12 10 2014 rong.yang
109 * [MOLY00087194] [3G UMAC] merge 6291 code from MOLY.U3G.90IT.DEV
110 * .
111 *
112 * 09 17 2013 shouzhu.zhang
113 * [MOLY00037556] remove compile option __ADD_MEAS_FREQ_NUM__
114 * <saved by Perforce>
115 *
116 * 04 01 2013 shouzhu.zhang
117 * [MOLY00013249] MM TL1 Code check in
118 * [TL1] Merge lastes WR8 + R9 + MM code to MOLY..
119 *
120 * 09 24 2012 xiaoyun.mao
121 * [MOLY00004069] [MOLY]TDD_R9_DEV Patch back to MOLY
122 * TDD_R9_DEV patch back to MOLY
123 *
124 * 09 19 2012 xiaoyun.mao
125 * [MOLY00002766]
126 * warning remove about CFN_IMMEIDATE: oxFFFF changed to -1
127 *
128 * 05 03 2012 wcpuser_integrator
129 * removed!
130 * .
131 *
132 * 03 02 2012 shuyang.yin
133 * removed!
134 * .
135 * (TL1 SAP)
136 *
137 * 02 24 2012 shuyang.yin
138 * removed!
139 * .
140 *
141 * 01 18 2011 xinqiu.wang
142 * removed!
143 * Add RHR feature to tl1 interface files.
144 *
145 * 12 01 2010 popcafa.shih
146 * removed!
147 * .
148 *
149 * 11 04 2010 xinqiu.wang
150 * removed!
151 * 1. Add ul_mac_event to cphy_dch_setup/modify/release_req
152 * 2. Add two ticks and structs for mac-tl1 interface.
153 * 3. Add two simulation structs according to MAC's requeset.
154 *
155 * 11 03 2010 xinqiu.wang
156 * removed!
157 * 1.SLCE-TL1 SAP Modify for R7
158 * 2. MAC-TL1 SAP Modify for UPA
159 *
160 * 08 24 2010 popcafa.shih
161 * removed!
162 * .
163 *
164 * 08 02 2010 qing.zhang
165 * removed!
166 * 1. Change the value of MAX_UL_TB from 16 to 32, change the value of MAX_DL_DATA from 953 to 1187, and change the value of MAX_UL_DATA from 829 to 1187 according to the requirement of UMAC.
167 *
168 * removed!
169 * removed!
170 * 1.Modify the description of MAX_HSDSCH_SIZE.
171 * 2.Modify BLER_INVALID to -64 according to the discussion result with SLCE.
172 *
173 * removed!
174 * removed!
175 * 1.Add max and min value of tm, off, rssi, rscp, iscp, sir, tx_power, tadv, doff, cpid, meas_id, bler.
176 *
177 * removed!
178 * removed!
179 *
180 *
181 * removed!
182 * removed!
183 * 1.Add HSUPA related cnst (MAX_EAGCH_NUM, MAX_EHICH_NUM, MAX_REF_BETA_NUM,MAX_EDCH_HARQ_PROC_PER_MODE )
184 *
185 * removed!
186 * removed!
187 * Add MAX_PREFERRED_PSC to solve tempory build error.
188 *
189 * removed!
190 * removed!
191 * 1.Add MAX_NUM_MEAS_CELL to solve tempory build error.
192 *
193 * removed!
194 * removed!
195 * 1.Delete pre-declare check of __UMTS_TDD128_MODE__
196 *
197 * removed!
198 * removed!
199 * Add check out history comments of last check in.
200 * 1.add check pre-declare of __UMTS_TDD128_MODE__
201 * 2.delete macro define of MAX_NUM_MEAS_CELL and MAX_PREFERRED_PSC
202 *
203 * removed!
204 * removed!
205 *
206 *
207 * removed!
208 * removed!
209 *
210 *
211 * removed!
212 * removed!
213 *
214 *
215 * removed!
216 * removed!
217 *
218 *
219 * removed!
220 * removed!
221 * Add TM_VALID and OFF_VALID in
222 *
223 * removed!
224 * removed!
225 * Rename __UMTS_TDD128_RAT__ to __UMTS_TDD128_MODE__
226 *
227 * removed!
228 * removed!
229 * correct the file name in the file header
230 *
231 * removed!
232 * removed!
233 * add log section for tl1interface header files
234 *
235 *******************************************************************************/
236
237#ifndef _TL1_CNST_H
238#define _TL1_CNST_H
239
240/*-------- BCH related constant ----------------------*/
241#define TDD_MAX_SIB_PATTERN (28) /* The maximum number of BCH SIB blocks */
242#define TDD_MAX_SIB_SEG_COUNT (16) /* The maximum number of segments in 1 BCH SIB */
243
244/*-------- TrCH related constant (For UL/DL 384Kbps capability) ----------------------*/
245#define TDD_MAX_TRCH_NUM (8) /* Maximum Simultaneous TrCHs of any kind (DL or UL).For 384kbps capability*/
246#define TDD_MAX_DL_TB (32) /* Maximum simultaneous DL TBs, For 384kbps capability.*/
247#define TDD_MAX_DL_TFC (128) /* Maximum number of TFCs per DL CCTrCH, For 384kbps capability */
248#define TDD_MAX_DL_TFs (64) /* Maximum numbre of TFs per DL CCTrCH,For 384kbps capability */
249#define TDD_MAXTF (32) /* Maximum number of TF per UL or DL TrCH TFS */
250#define TDD_MAXFACHPCH (8) /* Maximum number of FACHs and PCHs mapped onto one S-CCPCHs */
251#define TDD_MAX_UL_TFC (64) /* Maximum number of TFCs per UL CCTrCH,For 384kbps capability*/
252#define TDD_MAX_UL_TB (32) /* Maximum simultaneous DUL TBs */
253#define TDD_MAX_UL_TFs (32) /* Maximum numbre of TFs per UL CCTrCH, For 384kbps capability. */
254#define TDD_MAX_UL_TRCH (8) /* Maximum number of UL TrCH,UE declared capability. */
255#define TDD_MAX_DL_TRCH (8) /* Maximum number of DL TrCH,UE declared capability.*/
256
257/*(336/8)*24+(144+4)/8+80*2 = 1187*/
258#define TDD_MAX_DL_DATA (1187) /* Maximum DL transport block array size. */
259#define TDD_MAX_UL_DATA (1187) /* Maximum UL transport block array size. */
260
261
262
263/*-------- FS/Measurement related constant ----------------------*/
264#ifdef __GEMINI__
265#define TDD_MAX_FREQ_RANGE (36)
266#else
267#define TDD_MAX_FREQ_RANGE (8) /* Max size of frequency ranges for frequency scan. */
268#endif
269#define TDD_MAX_FREQ_LIST (33) /* Max size of stored frequency list for frequency scan */
270#define TDD_MAX_PREFERRED_CELL (96) /* Max number of preferred cells on 1 frequency for frequency scan */
271#define TDD_MAX_PREFERRED_PSC (96) /* Max number of preferred cells on 1 frequency for frequency scan */
272#define TDD_MAX_NUM_REPORT_CELL (32) /* Max number of reported cells in the CPHY_MEASUREMENT_CELL_IND */
273#define TDD_MAX_NUM_MEASURED_CELL (64) /* Max number of monitored cells in the CPHY_MEASUREMENT_CONFIG_CELL_REQ*/
274#define TDD_MAX_NUM_MEAS_CELL (64) /* Max number of monitored cells in the measurement cell request primitive */
275#define TDD_MAX_MEAS_EVENT (8) /* Maximum number of measurement events */
276#define TDD_MAX_UMTS_FREQ (13) /* Maximum number of DPCH radio links in TDD128 */
277#define TDD_MAX_NUM_MEAS_ID (16) /* Maximum number of "Measurement Identity" */
278#define TDD_REPORT_INFINITY (0xFF) /* Tx_power measurement report number infinity*/
279
280#define TDD_MAX_RSSI_SNIFFER_SCAN_LIST (36) /*Maximum number of RSSI SNIFFER UARFCN (Add by Janet) */
281
282/*-------- Magic value related constant ----------------------*/
283#define TDD_TM_INVALID (-1) /* Default value representing Tm unknown. */
284#define TDD_TM_VALID (6400*8) /* Default value representing Tm known. */
285#define TDD_MAX_TM (6400*8-1) /* Maximum effective value of tm.*/
286#define TDD_MIN_TM (0) /* Minimum effective value of tm.*/
287#define TDD_OFF_INVALID (-1) /* Default value representing OFF unknown. */
288#define TDD_OFF_VALID (8192) /* Default value representing Tm known. 8192 */
289#define TDD_MAX_OFF (8191) /* Maximum effective value of off.*/
290#define TDD_MIN_OFF (0) /* Minimum effective value of off.*/
291#define TDD_RSSI_INVALID (-32768) /* Default value representing RSSI unknown. */
292#define TDD_MAX_RSSI (-100) /* Maximum effective value of rssi.*/
293#define TDD_MIN_RSSI (-400) /* Minimum effective value of rssi.*/
294#define TDD_RSCP_INVALID (0) /* Default value representing RSCP unknown. */
295#define TDD_MAX_RSCP (-100) /* Maximum effective value of rscp.*/
296#define TDD_MIN_RSCP (-500) /* Minimum effective value of rscp.*/
297#define TDD_ISCP_INVALID (0) /* Default value representing ISCP unknown. */
298#define TDD_MAX_ISCP (-100) /* Maximum effective value of iscp.*/
299#define TDD_MIN_ISCP (-480) /* Minimum effective value of iscp.*/
300#define TDD_SIR_INVALID (-32768) /* Default value representing SIR unknown. */
301#define TDD_MAX_SIR (40) /* Maximum effective value of sir.*/
302#define TDD_MIN_SIR (-28) /* Minimum effective value of sir.*/
303#define TDD_TX_POWER_INVALID (-32768) /* Default value representing UE TX POWER unknown. */
304#define TDD_MAX_TX_POWER (136) /* Maximum effective value of UE tx_power.*/
305#define TDD_MIN_TX_POWER (-200) /* Minimum effective value of UE tx_power.*/
306#define TDD_TADV_INVALID (-1) /* Default value representing tadv unknown. */
307#define TDD_MAX_TADV (8191) /* Maximum effective value of tadv.*/
308#define TDD_MIN_TADV (0) /* Minimum effective value of tadv.*/
309#define TDD_UARFCN_INVALID (65535) /* Invalid UARFCN for setting empty freq. entry in meas. config req. */
310#define TDD_DOFF_INVALID (-1) /* Default value representing DOFF unknown. */
311#define TDD_MAX_DOFF (7) /* Maximum effective value of doff.*/
312#define TDD_MIN_DOFF (0) /* Minimum effective value of doff.*/
313#define TDD_CPID_INVALID (255) /* Default value representing CELL_PARAM_ID unknown. */
314#define TDD_MAX_CPID (127) /* Maximum effective value of CPID.*/
315#define TDD_MIN_CPID (0) /* Minimum effective value of CPID.*/
316#define TDD_MEAS_ID_INVALID (0) /* Default value representing MEAS_ID unknown.Valid value range from 1 to 16. */
317#define TDD_MAX_MEAS_ID (16) /* Maximum effective value of meas_id.*/
318#define TDD_MIN_MEAS_ID (1) /* Minimum effective value of meas_id.*/
319#define TDD_BLER_INVALID (-64) /* Default value representing BLER unknown. */
320#define TDD_MAX_BLER (0) /* Maximum effective value of bler.*/
321#define TDD_MIN_BLER (-63) /* Minimum effective value of bler.*/
322#define TDD_PCCPCH_TX_POWER_INVALID (0) /* Default value representing PCCPCH TX POWER unknown. */
323#define TDD_MAX_PCCPCH_TX_POWER (43) /* Maximum effective value of PCCPCH tx_power.*/
324#define TDD_MIN_PCCPCH_TX_POWER (6) /* Minimum effective value of PCCPCH tx_power.*/
325
326
327/*-------- Activation time related constant ----------------------*/
328#define TDD_CFN_IMMEDIATE (-1) /* Immediate CFN activation time. */
329#define TDD_SFN_IMMEDIATE (-1) /* Immediate SFN activation time. */
330
331/*-------- PhyCh related constant ---------------------*/
332#define TDD_MAX_ASC (8) /* Maximum access service class number */
333#define TDD_MAX_RL (1) /* Maximum number of DPCH radio links in TDD128 */
334#define TDD_MAX_TIMESLOT_PER_SUBFRAME (7) /* Maximum number of noraml timeslosts(TS0 ~ TS6) in a subframe in TDD128 */
335#define TDD_MAX_DL_TIMESLOT_PER_SUBFRAME (5) /*Max downlink timeslot in one subframe, only noraml timeslot is count*/
336#define TDD_MAX_UL_TIMESLOT_PER_SUBFRAME (5) /*Max uplink timeslot in one subframe,only noraml timeslot is count */
337#define TDD_MAX_UL_PHYCH_PER_SLOT (2) /*Max physical channel in one slot in uplink*/
338#define TDD_MAX_DL_PHYCH_PER_SLOT (16) /* Max physical channel in one slot in downlink*/
339#define TDD_MAX_DL_PHYCH_PER_SUBFRAME (48) /*Max physical channel in one subframe in downlink*/
340#define TDD_MAX_PRACH_FPACH_NUM (8) /*Maximum number of PRACH / FPACH pairs in a cell (1.28 Mcps TDD)*/
341
342/*-------- HSDPA related constant ---------------------*/
343#define TDD_MAX_HSSCCH_NUM (4) /*The maximum number of HSSCCH assigned to UE by NW*/
344#define TDD_MAX_HARQ_PROCESS_NUM (8) /*Maximum number of HARQ process supported in R5.*/
345#define TDD_MAX_HSDSCH_QUEUE (8) /*Maximum number of HS-DSCH queue supported in R5*/
346#define TDD_MAX_HSDSCH_SIZE (8) /*Maximum number of HS-DSCH size per queue supported in R5*/
347
348#ifdef __HSUPA_SUPPORT__
349#define TDD_MAX_EAGCH_NUM (4) /*Maximum number of E-AGCH assigned to UE by NW.*/
350#define TDD_MAX_EHICH_NUM (4) /*Maximum number of E-HICH assigned to UE by NW.*/
351#define TDD_MAX_REF_BETA_NUM (8) /*Maximum number of reference Beta informationto UE by NW.*/
352#define TDD_MAX_EDCH_HARQ_PROC_PER_MODE (4) /*Maximum number of allocated E-DCH HARQ processes per granting mode.*/
353#define TDD_MAX_EHICH_RESULT_NUM (6) /*Maximum number of E-HICH results can be sent to MAC at one time.*/
354#define TDD_MAX_ETFCI_BITMAP_SIZE (16) /*supported_etfci_bitmap array size. TDD_MAX_ETFCI_BITMAP_SIZE=64/4*/
355#endif
356
357
358/*#define TDD_MAX_ERUCCH (256) max number of ERUCCH*/
359#define TDD_MAX_ERUCCH (8) /*max number of ERUCCH*/
360#define TDD_maxEDCHTxPattern_TDD128 (4) /*max number of EDCH TX pattern for SPS*/
361//#endif
362//#if defined( __UMTS_R9__ ) && defined ( __AST3002__ )
363#define TDD_MAX_DMO_PATTERN_NUM (5)
364//#endif
365
366//replace enums temporarily
367//#ifdef __PS_L1_DC_ARCH__
368#define TDD_T_W_DEDICATED_PCH_BUFFER 1
369#define TDD_gRxPchBuffQueueSize (2)
370#define TDD_gRxDchBuffQueueSize (8)
371#define TDD_gRxDschBuffQueueSize (12)
372
373#define TDD_MAX_NUM_OF_EDCH_HARQ_PROCESS (8)
374#define TDD_MAC_E_PDU_MEMORY_SIZE (1408) // maximum 11160 for TDD128,1400->1408 for 64B Allign
375
376//for HSDPA
377// MAX_MAC_HS_PDU_NUM = MAX_MAC_PDP_SUPPORT * 32(MAX_MAC_HS_WINDOW_SIZE)+MAC_HS_PDU_NUM_MARGIN
378// When support<3 PDP, we leave MAC_HS_PDU_NUM_MARGIN=20, 10 for UL1 pre-get MAC-hs PDU, 10 for margin
379#define TDD_MAX_MAC_PDP_SUPPORT GPRS_MAX_PDP_SUPPORT
380#if TDD_MAX_MAC_PDP_SUPPORT<3
381#define TDD_MAC_HS_PDU_NUM_MARGIN 20
382#else
383#define TDD_MAC_HS_PDU_NUM_MARGIN 0
384#endif
385
386#define TDD_MAX_MAC_HS_PDU_NUM ((TDD_MAX_MAC_PDP_SUPPORT * 32) + TDD_MAC_HS_PDU_NUM_MARGIN)
387
388#define TDD_mBYTE_SIZE_TO_32_BYTE_ALIGN_INC(byteSize) (((byteSize) + 31) & 0xFFE0)
389
390#define TDD_MAX_HS_PDU_SIZE_IN_BYTES (((TDD_MAX_HS_PDU_SIZE_IN_BITS+32+31)/32)*4)
391
392#define TDD_MAX_HS_PDU_SIZE_IN_BITS 14043
393
394#define TDD_DL_ADR_OFFSET (4)
395
396//for RX
397//@review code, TDD_gRxDchBuffQueueSize defined as 8, so we simply redefine TDD_MAX_MAC_DCH_PDU_NUM as 8 + 1
398#if 0
399/* under construction !*/
400#else
401#define TDD_MAX_MAC_DCH_PDU_NUM (6+1+2)
402#define TDD_MAX_MAC_PCH_PDU_NUM (TDD_gRxPchBuffQueueSize+1) /*mac buffer should > tl1 pch buffer, or fator. When receive PCH msg, lumac will alloc new buff if no more will fatal.*/
403#endif
404#define TDD_MAX_MAC_DCH_PDU_SIZE (1472)
405#define TDD_MAX_MAC_PCH_PDU_SIZE (1472)
406//#endif
407
408#define TDD_MAX_MAC_HS_PDU_SIZE 1804 // Category 6 : 14411 bits and need 4-byte alignment
409
410
411
412#endif