| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * ul1_def.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * WCDMA_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file contains common typedef, definition prototypes exported by L1 |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
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| 682 | *------------------------------------------------------------------------------ |
| 683 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 684 | *============================================================================ |
| 685 | ****************************************************************************/ |
| 686 | |
| 687 | #ifndef _UL1_DEF_H |
| 688 | #define _UL1_DEF_H |
| 689 | |
| 690 | /* auto add by kw_check begin */ |
| 691 | #include "ul1_cnst.h" |
| 692 | #include "kal_general_types.h" |
| 693 | /* auto add by kw_check end */ |
| 694 | |
| 695 | #include "gmss_public.h" |
| 696 | #include "ul1_protected_def.h" |
| 697 | |
| 698 | |
| 699 | /* ---------------------- L+W Gemini ----------------------*/ |
| 700 | typedef enum _UL1_SIM_INDEX_E |
| 701 | { |
| 702 | UL1_SIM_1 = 0, |
| 703 | #ifdef __GEMINI_WCDMA__ |
| 704 | UL1_SIM_2, |
| 705 | #if (GEMINI_PLUS_WCDMA >= 3) |
| 706 | UL1_SIM_3, |
| 707 | #if (GEMINI_PLUS_WCDMA >= 4) |
| 708 | UL1_SIM_4, |
| 709 | #endif /* GEMINI_PLUS_WCDMA >= 4 */ |
| 710 | #endif /* GEMINI_PLUS_WCDMA >= 3 */ |
| 711 | #endif /* __GEMINI_WCDMA__ */ |
| 712 | UL1_SIM_NUM |
| 713 | } UL1_SIM_INDEX_E; |
| 714 | |
| 715 | #if (GEMINI_PLUS_WCDMA > 4) |
| 716 | #error "The number of SIM can't be over than 4 pieces." |
| 717 | #endif |
| 718 | |
| 719 | /*-------------------- ADT -----------------------*/ |
| 720 | typedef enum _FDD_ADT_Mode_E |
| 721 | { |
| 722 | FDD_ADT_NONE = 0, |
| 723 | FDD_ADT_NORMAL, |
| 724 | FDD_ADT_TALKING |
| 725 | } FDD_ADT_Mode_E; |
| 726 | |
| 727 | /*-------- TGPS related definition ----------------------*/ |
| 728 | typedef enum _FDD_tgps_act_E |
| 729 | { |
| 730 | FDD_TGPS_ACTIVATE, /* Activate the TGPS */ |
| 731 | FDD_TGPS_DEACTIVATE /* Deactivate the TGPS */ |
| 732 | } FDD_tgps_act_E; |
| 733 | |
| 734 | typedef enum _FDD_tg_mode_E |
| 735 | { |
| 736 | FDD_TG_UL, /* UL only */ |
| 737 | FDD_TG_DL, /* DL only */ |
| 738 | FDD_TG_UL_DL /* Both UL and DL */ |
| 739 | } FDD_tg_mode_E; |
| 740 | |
| 741 | typedef enum _FDD_tgmp_E |
| 742 | { |
| 743 | FDD_TG_FDD_MEASURE, /* Inter-frequency measurement */ |
| 744 | FDD_TG_GSM_RSSI, /* GSM RSSI measurement */ |
| 745 | FDD_TG_GSM_BSIC_INIT, /* GSM initial BSIC */ |
| 746 | FDD_TG_GSM_BSIC_CNF, /* GSM BSIC confirm */ |
| 747 | FDD_TG_EUTRA, /* E-UTRA */ |
| 748 | FDD_TG_TGMP_UNDEFINED |
| 749 | } FDD_tgmp_E; |
| 750 | |
| 751 | typedef enum _FDD_tg_method_E |
| 752 | { |
| 753 | FDD_TG_PUNCT, /* Puncturing. only for DL */ |
| 754 | FDD_TG_HLS, /* Higher layer scheduling */ |
| 755 | FDD_TG_SF_2, /* SF/2 */ |
| 756 | FDD_TG_NONE /* None */ |
| 757 | } FDD_tg_method_E; |
| 758 | |
| 759 | typedef struct _FDD_tgps_info_T |
| 760 | { |
| 761 | kal_uint8 tgpsi; /* TGPSI. 1 ~ 6 */ |
| 762 | kal_uint8 tgcfn; /* TGCFN. 0 ~ 255 */ |
| 763 | FDD_tgps_act_E status; /* Action applied to TGPS */ |
| 764 | kal_bool tgps_para_valid; /* indicate if following parameter should be modifed */ |
| 765 | FDD_tgmp_E purpose; /* TGMP. TGPS purpose */ |
| 766 | FDD_tg_mode_E mode; /* TG mode */ |
| 767 | FDD_tg_method_E ul_method; /* UL TG method */ |
| 768 | FDD_tg_method_E dl_method; /* DL TG method */ |
| 769 | kal_uint8 rpp; /* RPP. 0 or 1 */ |
| 770 | kal_uint8 itp; /* ITP. 0 or 1 */ |
| 771 | kal_uint8 dl_frame_type; /* DL TG frame type. 0 : type A. 1 : type B */ |
| 772 | kal_uint8 sir1; /* DeltaSIR1. 0 ~ 30. true value is sir1/10 */ |
| 773 | kal_uint8 sir_after1; /* DeltaSIRafter1. 0 ! 10. true value is sir_after1/10 */ |
| 774 | kal_uint8 sir2; /* DeltaSIR1. 0 ~ 30. true value is sir2/10 */ |
| 775 | kal_uint8 sir_after2; /* DeltaSIRafter1. 0 ! 10. true value is sir_after2/10 */ |
| 776 | kal_uint16 tgprc; /* TGPRC. 0 ~ 511. 0 for infinity*/ |
| 777 | kal_uint8 tgsn; /* TGSN. 0 ~ 14 */ |
| 778 | kal_uint8 tgl1; /* TGL1. 1 ~ 14 slts */ |
| 779 | kal_uint8 tgl2; /* TGL2. 1 ~ 14 slts */ |
| 780 | kal_uint16 tgd; /* TGD. 15 ~ 270. 270 means TGD is undefed (only 1 TG) */ |
| 781 | kal_uint8 tgpl1; /* TGPL1. 1 ~ 144 */ |
| 782 | kal_uint8 tgpl2; /* TGPL2. 1 ~ 144 */ |
| 783 | kal_uint8 ident_abort; /* N_IDENTIFY_ABORT. 1 ~ 128 */ |
| 784 | kal_uint8 reconf_abort; /* Treconfirm_abort. 1 ~ 20. true value is divided by 2 */ |
| 785 | kal_bool freq_specific_compressed_mode; /* [R10] true: tgps is not applied on serving band. */ |
| 786 | } FDD_tgps_info_T; |
| 787 | |
| 788 | typedef enum _FDD_tgps_status_E |
| 789 | { |
| 790 | FDD_TGPS_ACTIVE, |
| 791 | FDD_TGPS_DEACTIVE |
| 792 | } FDD_tgps_status_E; |
| 793 | |
| 794 | typedef struct _FDD_tgps_status_T |
| 795 | { |
| 796 | kal_uint8 tgpsi; /* TGPS index */ |
| 797 | kal_uint8 tgcfn; /* TGCFN. 0 ~ 255 */ |
| 798 | FDD_tgps_status_E status; /* Status to be applied to TGPS */ |
| 799 | kal_bool freq_specific_compressed_mode; /* [R10] true: tgps is not applied on serving band. */ |
| 800 | } FDD_tgps_status_T; |
| 801 | |
| 802 | typedef struct _FDD_tgps_status_info_T |
| 803 | { |
| 804 | kal_uint8 num_tgps; /* # of TGPS status pattern */ |
| 805 | kal_int16 reconf_time; /* TGPS reconfiguration CFN. -1 ~ 255. -1 means immediate */ |
| 806 | FDD_tgps_status_T tgps_status[FDD_MAX_TGPS]; /* TGPS status information */ |
| 807 | } FDD_tgps_status_info_T; |
| 808 | |
| 809 | |
| 810 | typedef struct _FDD_tgps_config_T |
| 811 | { |
| 812 | kal_uint8 tgpsi; /* tgpsi */ |
| 813 | FDD_tgmp_E tgmp; /* purpose of this tgpsi */ |
| 814 | FDD_tgps_status_E status; /*tgps status at the activation time*/ |
| 815 | } FDD_tgps_config_T; |
| 816 | |
| 817 | typedef struct _FDD_p_tgps_config_T |
| 818 | { |
| 819 | kal_int16 sfn; /* reconfig time of this pending tgps configuration*/ |
| 820 | kal_uint8 tgps_num; /* number of tgps in this pneding tgps */ |
| 821 | FDD_tgps_config_T tgps[FDD_MAX_TGPS]; /* tgps config (tgpsi, tgmp, status) */ |
| 822 | } FDD_p_tgps_config_T; |
| 823 | |
| 824 | typedef struct _FDD_tgps_config_by_tgmp_T |
| 825 | { |
| 826 | kal_uint8 tgpsi; /* tgpsi for the tgmp */ |
| 827 | kal_uint8 p_tgps_config_num; /* pending tgps_config num of this tgpsi */ |
| 828 | kal_bool c_tgps_config_valid; /* existence of current tgps_config of this tgpsi, |
| 829 | if false, c_tgps_config is meaningless */ |
| 830 | FDD_tgps_config_T c_tgps_config; /* current tgps_config of this tgpsi */ |
| 831 | FDD_tgps_config_T p_tgps_config[FDD_MAX_PENDING_TGPS_NUM]; /* pending tgps config of this tgpsi */ |
| 832 | } FDD_tgps_config_by_tgmp_T; |
| 833 | |
| 834 | typedef enum _FDD_tgps_time_relationship_E |
| 835 | { |
| 836 | FDD_TGPS_BEFORE, |
| 837 | FDD_TGPS_EQUAL, |
| 838 | FDD_TGPS_AFTER |
| 839 | } FDD_tgps_time_relationship_E; |
| 840 | |
| 841 | typedef enum _FDD_tgps_complete_status_E |
| 842 | { |
| 843 | FDD_TGPS_COMPLETE_OR_INACTIVE, |
| 844 | FDD_TGPS_NOT_COMPLETE |
| 845 | } FDD_tgps_complete_status_E; |
| 846 | |
| 847 | typedef struct _FDD_tgps_complete_status_by_tgmp_T |
| 848 | { |
| 849 | kal_int16 sfn; /*activation time or TGPS reconfiguration SFN, |
| 850 | range: -1-4095, -1 means immediate(only used in current tgps config)*/ |
| 851 | |
| 852 | FDD_tgps_complete_status_E tgps_complete_status; /* tgps complete status for that tgpsi*/ |
| 853 | } FDD_tgps_complete_status_by_tgmp_T; |
| 854 | |
| 855 | typedef struct _FDD_tgps_status_by_tgmp_T |
| 856 | { |
| 857 | kal_uint8 tgmp_num; /* num of valid tgmp in the structure */ |
| 858 | FDD_tgmp_E tgmp[FDD_MAX_TGMP_NUM]; /* tgmp queried */ |
| 859 | kal_bool status[FDD_MAX_TGMP_NUM]; /* TRUE: if there is current or pending active and incompleted tgps for that tgmp */ |
| 860 | } FDD_tgps_status_by_tgmp_T; |
| 861 | |
| 862 | |
| 863 | /* U3G */ |
| 864 | typedef struct _FDD_tgps_info_share_memory_T |
| 865 | { |
| 866 | kal_uint8 tgpsi; /* tgpsi */ |
| 867 | FDD_tgmp_E tgmp; /* purpose of this tgpsi */ |
| 868 | FDD_tgps_status_E status; /* tgps status at the activation time*/ |
| 869 | FDD_tgps_complete_status_E complete_status; |
| 870 | } FDD_tgps_info_share_memory_T; |
| 871 | |
| 872 | typedef struct _FDD_tgps_param_share_memory_T |
| 873 | { |
| 874 | kal_int16 sfn; /* reconfig time of this pending tgps configuration*/ |
| 875 | kal_uint8 tgps_info_num; /* number of tgps in this pneding tgps */ |
| 876 | FDD_tgps_info_share_memory_T tgps_info[FDD_MAX_TGPS]; /* tgps config (tgpsi, tgmp, status) */ |
| 877 | } FDD_tgps_param_share_memory_T; |
| 878 | |
| 879 | typedef struct _FDD_tgps_status_share_memory_T |
| 880 | { |
| 881 | kal_uint8 tgps_param_num; |
| 882 | FDD_tgps_param_share_memory_T tgps_param[FDD_MAX_TGPS]; |
| 883 | } FDD_tgps_status_share_memory_T; |
| 884 | /* U3G */ |
| 885 | |
| 886 | /*-------- PhyCH related definition ----------------------*/ |
| 887 | typedef struct _FDD_pich_drx_T |
| 888 | { |
| 889 | kal_uint8 pch_drx; /* DRX cycle length coefficient. 3 ~ 9 */ |
| 890 | kal_uint8 pi_num; /* # of PI per frame. 18, 36, 72, 144 */ |
| 891 | kal_uint8 pi; /* Paging Indicator index. */ |
| 892 | kal_uint16 sfn_po; /* SFN of the frame containing start of PICH for the first paging occasion. */ |
| 893 | } FDD_pich_drx_T; |
| 894 | |
| 895 | #ifdef __SMART_PAGING_3G_FDD__ |
| 896 | typedef struct _FDD_pich_smartpaging_T |
| 897 | { |
| 898 | kal_bool support_repeat; /* If true: RRCE has detected that current NW can support smart paging (has repeated paging pattern) */ |
| 899 | kal_uint16 sfn_po; /* DRX parameters for PICH.(when smartpging active) */ |
| 900 | } FDD_pich_smartpaging_T; |
| 901 | #endif |
| 902 | |
| 903 | typedef enum _FDD_pich_reconfig_type_E |
| 904 | { |
| 905 | FDD_PCH_MODIFY, /* traditionaly PCH modify */ |
| 906 | FDD_PCH_SMARTPAGE, /* to inform UL1 enable/disable SmartPaging*/ |
| 907 | } FDD_pich_reconfig_type_E; |
| 908 | |
| 909 | typedef struct _FDD_pich_info_T |
| 910 | { |
| 911 | kal_bool sttd; /* If STTD is used. */ |
| 912 | kal_int8 cpich_tx_power; /* CPICH TX power. -10~50 dBm */ |
| 913 | kal_int8 power_offset; /* PICH power offset to CPICH. -10 ~ 5 dB */ |
| 914 | kal_uint8 ovsf; /* Channelization code. 0 ~ 255 */ |
| 915 | FDD_pich_drx_T pich_drx; /* DRX parameters for PICH. */ |
| 916 | #ifdef __SMART_PAGING_3G_FDD__ |
| 917 | FDD_pich_smartpaging_T smartpaging_info; |
| 918 | #endif |
| 919 | #ifdef __UMTS_R7__ |
| 920 | FDD_pich_drx_T pich_drx_cycle2; /* DRX parameters 2 for PICH. */ |
| 921 | kal_uint16 drx_cycle2_time; /* if it's not 0. UL1 shall use pich_drx_2 for PICH receptin, else shall directly use pich_drx for PICH reception. 0~5120 ms */ |
| 922 | #endif /* __UMTS_R7__ */ |
| 923 | } FDD_pich_info_T; |
| 924 | |
| 925 | typedef struct _FDD_ctch_drx_level1_T |
| 926 | { |
| 927 | kal_uint8 m_tti; |
| 928 | kal_uint8 start_off; /* Offset of the start of first block set k. */ |
| 929 | kal_uint16 repe_period; /* Block set repetition period. */ |
| 930 | kal_uint16 bmc_sm_period; /*[R6] Period of BMC scheduling message (P) |
| 931 | [Value] 1, 8, 16, 32, 64, 128, 256 |
| 932 | If this value is set to 1, UL1 will receive CTCH in all CTCH allocation. |
| 933 | For R5 and R99, or for R6 but this field is not configured by the network, this value should be set to 1 */ |
| 934 | } FDD_ctch_drx_level1_T; |
| 935 | |
| 936 | typedef struct _FDD_ctch_drx_level2_T |
| 937 | { |
| 938 | // kal_uint8 bs_mask[32]; |
| 939 | // kal_uint16 bs_mask_len; /* 1 ~ 256 */ |
| 940 | kal_uint8 level2_bitmap[FDD_BMC_MAX_BITMAP_SIZE]; |
| 941 | kal_uint16 lenOfBitmap; |
| 942 | kal_uint8 bitmapOffset; |
| 943 | kal_uint16 sfnOfLastScheduleMsg; |
| 944 | kal_bool flush_l2; |
| 945 | } FDD_ctch_drx_level2_T; |
| 946 | |
| 947 | typedef union _FDD_ctch_drx_level |
| 948 | { |
| 949 | FDD_ctch_drx_level1_T drx_level1; /* CTCH DRX Level 1 information. */ |
| 950 | FDD_ctch_drx_level2_T drx_level2; /* CTCH DRX Level 2 information. */ |
| 951 | } FDD_ctch_drx_level; |
| 952 | |
| 953 | typedef struct _FDD_ctch_drx_T |
| 954 | { |
| 955 | kal_bool level1_Ind; /* True: CTCH level 1 parameters is used. */ |
| 956 | FDD_ctch_drx_level ctch_drx_level; /* CTCH DRX level parameters */ |
| 957 | } FDD_ctch_drx_T; |
| 958 | |
| 959 | typedef union _FDD_pich_ctch_info_T |
| 960 | { |
| 961 | FDD_ctch_drx_T ctch_drx; /* CTCH DRX information */ |
| 962 | FDD_pich_info_T pich_info; /* PICH information */ |
| 963 | } FDD_pich_ctch_info_T; |
| 964 | |
| 965 | typedef struct _FDD_sccpch_info_T |
| 966 | { |
| 967 | kal_uint8 ssc; /* Secondary scrambling code. 0 ~ 15 */ |
| 968 | /* This value will not be used, if SCCPCH is used to carrying PCH */ |
| 969 | /* if the value is equal to 0, it means primary scrambling code is used */ |
| 970 | kal_bool sttd; /* True if STTD is used */ |
| 971 | kal_bool pilot_exit; /* If pilot symbol exists */ |
| 972 | kal_bool tfci_exit; /* If TFCI is used. */ |
| 973 | kal_bool fixed_pos_ind; /* If Fixed or flexible position is used. True means Fixed */ |
| 974 | kal_uint16 timing_offset; /* Frame boundary to P-CCPCH. 0 ~ 38144 by step of 256. */ |
| 975 | kal_uint16 sf; /* Spreading Factor. 4 ~ 256 */ |
| 976 | kal_uint16 ovsf; /* Channelization code. 0 ~ sf-1 */ |
| 977 | } FDD_sccpch_info_T; |
| 978 | |
| 979 | typedef enum _FDD_access_status_E |
| 980 | { |
| 981 | FDD_AI_ACK, /* Network ACK in AICH */ |
| 982 | FDD_AI_NACK, /* Network NACK in AICH */ |
| 983 | FDD_AI_NOACK, /* Network no response in AICH*/ |
| 984 | FDD_AI_ABORT, /* Aborted by higher layer */ |
| 985 | FDD_AI_PARAMERROR, /* Access request without preliminary Data request */ |
| 986 | FDD_AI_NESTEDREQUEST /* Access request before previous one finished */ |
| 987 | } FDD_access_status_E; |
| 988 | |
| 989 | typedef struct _FDD_aich_info_T |
| 990 | { |
| 991 | kal_int8 power_offset; /* Power offset to CPICH. -22 ~ 5 dB */ |
| 992 | kal_uint8 ovsf; /* OVSF code. 0 ~ 255*/ |
| 993 | kal_bool sttd; /* Indicate if STTD is used */ |
| 994 | kal_uint8 tx_timing; /* AICH transmission timie. 0 or 1 */ |
| 995 | } FDD_aich_info_T; |
| 996 | |
| 997 | typedef struct _FDD_asc_T |
| 998 | { |
| 999 | kal_uint8 avail_sig_start; /* Available signature start index */ |
| 1000 | kal_uint8 avail_sig_end; /* Available signature end index */ |
| 1001 | kal_uint8 assigned_subchannel; /* Assigned subchannel number */ |
| 1002 | /* Bit0 represent bit b0, only 4 rightmost bit is valid */ |
| 1003 | } FDD_asc_T; |
| 1004 | |
| 1005 | typedef struct _FDD_prach_info_T |
| 1006 | { |
| 1007 | kal_uint16 min_sf; /* Min allowed SF. 32,64,128,256 */ |
| 1008 | kal_uint8 punc_limit; /* Puncturing limit. 40 ~ 100 */ |
| 1009 | kal_uint8 asc_num; /* # of valid ASC information in asc[]. 1 ~ 8 */ |
| 1010 | kal_uint8 pream_psc; /* Preamble scrambling code. 0 ~ 15 */ |
| 1011 | kal_uint16 avail_signature; /* Available signature. Bit string (16) */ |
| 1012 | /* Bit0 represent signature 0 */ |
| 1013 | kal_uint16 avail_subchannel; /* Available subchannels. Bit string (12)*/ |
| 1014 | /* Bit0 represent sub-channel 0 */ |
| 1015 | FDD_asc_T asc[FDD_MAX_ASC]; /* ASC information */ |
| 1016 | } FDD_prach_info_T; |
| 1017 | |
| 1018 | typedef struct _FDD_prach_power_T |
| 1019 | { |
| 1020 | kal_int8 max_tx_power; /* Max allowed TX power. -50 ~ 33dBm */ |
| 1021 | kal_int8 umts_power_class; /* UE capability*/ |
| 1022 | kal_int8 init_power_offset; /* SUM of "P-CPICH TX power" and "constant value" */ |
| 1023 | /* L1 will use this offste - CPICH_RSCP - UL_INTERFERENCE */ |
| 1024 | kal_uint8 power_step; /* Preamble power ramping step. 1 ~ 8dB */ |
| 1025 | kal_uint8 retrans_max; /* Max preamble retrans. 1 ~ 64 */ |
| 1026 | } FDD_prach_power_T; |
| 1027 | |
| 1028 | typedef struct _FDD_ul_pc_info_T |
| 1029 | { |
| 1030 | kal_uint8 pc_pream; /* Power control Preamble. 0 ~ 7 frames */ |
| 1031 | kal_uint8 pc_algo; /* Power control algorithm. 1 or 2; inherited from primary for secondary ul freq */ |
| 1032 | kal_uint8 tpc_step; /* Power control step size. 1 or 2dB */ |
| 1033 | /* This is only valid for pc_algo = 1; inherited from primary for secondary ul freq */ |
| 1034 | kal_int16 dpcch_power_offset; /* DPCCH initial power offset. -164 ~ 6 dBm */ |
| 1035 | } FDD_ul_pc_info_T; |
| 1036 | |
| 1037 | typedef enum _FDD_sc_type_E |
| 1038 | { |
| 1039 | FDD_SC_SHORT, /* Short type scrambling code */ |
| 1040 | FDD_SC_LONG /* Long type scrambling code */ |
| 1041 | } FDD_sc_type_E; |
| 1042 | |
| 1043 | typedef struct _FDD_ul_dpch_info_T |
| 1044 | { |
| 1045 | FDD_ul_pc_info_T ul_pc; /* UL power control info */ |
| 1046 | FDD_sc_type_E sc_type; /* Type of scrambling code */ |
| 1047 | kal_uint32 sc_code; /* Scrambling code #. 0 ~ 16777215 */ |
| 1048 | kal_uint8 ul_dpch_num; /* # of UL DPDCH. 0 ~ FDD_MAX_ULDPCH; ignored by secondary ul freq */ |
| 1049 | kal_uint16 min_sf; /* Min SF. 4,8,16,32,64,128,256; ignored by secondary ul freq */ |
| 1050 | kal_bool tfci_exist; /* Indicate if TFCI exists; inherited from primary for secondary ul freq */ |
| 1051 | kal_uint8 fbi_num; /* # of FBI bits. 0, 1, 2; inherited from primary for secondary ul freq */ |
| 1052 | kal_uint8 punc_limit; /* Puncture limit. 40 ~ 100 in step 4; ignored by secondary ul freq */ |
| 1053 | /* The acture PM = punc_limit/100; ignored by secondary ul freq */ |
| 1054 | #ifdef __UMTS_R7__ |
| 1055 | kal_uint8 tpc_bit_num; /* # of TPC bits. 2, 4; inherited from primary for secondary ul freq */ |
| 1056 | #endif /* __UMTS_R7__ */ |
| 1057 | } FDD_ul_dpch_info_T; |
| 1058 | |
| 1059 | /*-------- TFS related definition ----------------------*/ |
| 1060 | typedef enum _FDD_cc_type_T |
| 1061 | { |
| 1062 | FDD_CC_NONE, |
| 1063 | FDD_CC_CONV12, |
| 1064 | FDD_CC_CONV13, |
| 1065 | FDD_CC_TURBO, |
| 1066 | FDD_CC_TOTAL |
| 1067 | } FDD_cc_type_T; |
| 1068 | |
| 1069 | typedef struct _FDD_tfs_static_T |
| 1070 | { |
| 1071 | kal_uint8 tti; /* TTI. # of frames, 1, 2, 4, 8 */ |
| 1072 | FDD_cc_type_T channel_coding; /* Coding type */ |
| 1073 | kal_uint8 rm_attr; /* RM attribute */ |
| 1074 | kal_uint8 crc_size; /* # of CRC bits. 0,8,12,16,24 */ |
| 1075 | } FDD_tfs_static_T; |
| 1076 | |
| 1077 | typedef struct _FDD_tfs_dyn_T |
| 1078 | { |
| 1079 | kal_uint8 tb_num; /* # of TB */ |
| 1080 | kal_uint16 tb_size; /* # of bibts in a TB */ |
| 1081 | } FDD_tfs_dyn_T; |
| 1082 | |
| 1083 | typedef struct _FDD_tfs_T |
| 1084 | { |
| 1085 | kal_uint8 tf_num; /* # of TF in this TFS */ |
| 1086 | FDD_tfs_dyn_T tfs_dynamic[FDD_MAXTF]; /* TFS dynamic part */ |
| 1087 | FDD_tfs_static_T tfs_static; /* TFS static part */ |
| 1088 | } FDD_tfs_T; |
| 1089 | |
| 1090 | typedef enum _FDD_tx_diversity_E |
| 1091 | { |
| 1092 | FDD_DL_TX_NONE = 0, /* No TX diversity */ |
| 1093 | FDD_DL_TX_STTD = 1, /* STTD */ |
| 1094 | FDD_DL_TX_CLM1 = 2, /* Closed loop mode 1 */ |
| 1095 | FDD_DL_TX_CLM2 = 3 /* Closed loop mode 2 */ |
| 1096 | |
| 1097 | } FDD_tx_diversity_E; |
| 1098 | |
| 1099 | typedef enum _FDD_cws_len_E |
| 1100 | { |
| 1101 | FDD_SSDT_LONG, /* Long code word */ |
| 1102 | FDD_SSDT_MEDIUM, /* Medium code word */ |
| 1103 | FDD_SSDT_SHORT, /* Short code word */ |
| 1104 | FDD_SSDT_OFF /* SSDT is off */ |
| 1105 | |
| 1106 | } FDD_cws_len_E; |
| 1107 | |
| 1108 | typedef struct _FDD_ssdt_conf_T |
| 1109 | { |
| 1110 | kal_uint8 s_field; /* # of s bits. 1 or 2 */ |
| 1111 | FDD_cws_len_E cws_len; /* Code word set length */ |
| 1112 | } FDD_ssdt_conf_T; |
| 1113 | |
| 1114 | typedef enum _FDD_dpch_type_E |
| 1115 | { |
| 1116 | FDD_DPCH_TYPE = 0, |
| 1117 | FDD_FDPCH_TYPE = 1, |
| 1118 | /* __UMTS_R7__ BEGIN */ |
| 1119 | FDD_NO_DPCH_TYPE |
| 1120 | /* __UMTS_R7__ END */ |
| 1121 | } FDD_dpch_type_E; |
| 1122 | |
| 1123 | typedef struct _FDD_dl_dpch_rla_T |
| 1124 | { |
| 1125 | kal_uint8 dpc_mode; /* DL Power control mode. 0 or 1 or 2 */ |
| 1126 | kal_uint8 pilot_power_offset; /* Ppilot - Pdpdch. 0 ~ 24dB */ /*[R6] For F-DPCH, UL1 doesn't care this value */ |
| 1127 | kal_uint16 sf; /* SF. 4,8,16,32,64,128,256,512 */ /*[R6] For F-DPCH, UL1 doesn't care this value */ |
| 1128 | kal_bool fixed_pos; /* Fixed or flexible position. True = Fixed */ /*[R6] For F-DPCH, UL1 doesn't care this value */ |
| 1129 | kal_bool tfci_exist; /* Indicate if TFCI exist */ /* [R6] For F-DPCH, UL1 doesn't care this value */ |
| 1130 | kal_uint8 pilot_num; /* # of pilot bits. 2,4,8,16 */ /* [R6] For F-DPCH, UL1 doesn't care this value */ |
| 1131 | kal_uint8 tgps_num; /* # of TGPS in the list. 0 ~ 6 */ |
| 1132 | FDD_tgps_info_T tgps_info[FDD_MAX_TGPS]; /* TGPS list */ |
| 1133 | FDD_tx_diversity_E tx_diversity; /* TX diversity mode */ /* [R6] For F-DPCH, UL1 doesn't care this value */ |
| 1134 | FDD_ssdt_conf_T ssdt_conf; /* SSDT configuration */ /* [R6] For F-DPCH, UL1 doesn't care this value */ |
| 1135 | kal_int32 doff; /* Default DPCH offset value. -1 ~ 306688 */ |
| 1136 | /* -1 is an invalid value */ |
| 1137 | |
| 1138 | FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */ |
| 1139 | /* This value should be consistent with the dpch_type field in dl_dpch_rl */ |
| 1140 | kal_uint8 tpc_target; /* [R6] F-DPCH only, range: 1~10, the actual TPC command error rate target is tpc_target/100 */ |
| 1141 | } FDD_dl_dpch_rla_T; |
| 1142 | |
| 1143 | typedef struct _FDD_dldpch_code_T |
| 1144 | { |
| 1145 | kal_uint8 ssc; /* Scrambling code # for this code channel */ |
| 1146 | /* 0 ~ 15. 0 for "the same scrambling code for the P-CPICH */ |
| 1147 | kal_uint16 sf; /* 4,8,16,32,64,128,256,512 */ |
| 1148 | kal_uint16 ovsf; /* OVSF code. 0 ~ SF-1 */ |
| 1149 | kal_bool sc_change; /* True : Changed scrambling code is used */ |
| 1150 | } FDD_dldpch_code_T; |
| 1151 | |
| 1152 | typedef struct _FDD_dl_dpch_rl_T |
| 1153 | { |
| 1154 | kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */ |
| 1155 | kal_bool sttd; /* Indicate if STTD is used for P-CPICH for this RL */ |
| 1156 | /* If the value of tm is not equal to -1, UL1 will use this value */ |
| 1157 | /* If the value of tm is equal to -1, UL1 will not use this value */ |
| 1158 | kal_int32 tm; /* Cell boundary to LST. -1 ~ 38400*8-1 */ |
| 1159 | kal_int16 off; /* FN offset. -1 ~ 4095 : -1 means unknown timing */ |
| 1160 | kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell */ |
| 1161 | kal_bool pcpich_usage; /* Indicate if P-CPICH can be used for channel estimation */ |
| 1162 | /* KAL_TRUE means P-CPICH could be used */ |
| 1163 | kal_int8 scpich_ssc; /* Scrambling code of S-CPICH. */ |
| 1164 | /* -1 ~ 15. 0 means use primary scramblign code */ |
| 1165 | /* -1 means there is not S-CPICH */ |
| 1166 | kal_uint8 scpich_ovsf; /* OVSF code. 0 ~ 255 */ |
| 1167 | kal_bool tx_diversity_disable; /* Indicate if TX diversity is used */ /* [R6] For F-DPCH, UL1 doesn't care this value */ |
| 1168 | /* True means TX diversity is disabled. */ /* [R6] For F-DPCH, UL1 doesn't care this value */ |
| 1169 | kal_uint8 closedlooptimingadj_mode; /* 0 : CLTD timing adjust mode 0 */ /* [R6] For F-DPCH, UL1 doesn't care this value */ |
| 1170 | /* 1 : CLTD timing adjust mode 1 */ |
| 1171 | kal_uint8 ssdt_id; /* 0 ~ 8. 1 for 'A'. 8 for not applicable*/ |
| 1172 | kal_uint8 tpc_index; /* TPC combination index. 0 ~ 5 */ |
| 1173 | kal_int8 tpc_power_offset; /* Power offset between TPC and DPDCH,-1 means INVALID, range 0~24 dB (actual 0:0.25:6) [R5 only] */ |
| 1174 | /* [R6] For F-DPCH, UL1 doesn't care this value */ |
| 1175 | |
| 1176 | /* [R6] F-DPCH: dl_dpch_num must be 1 and the index of the F-DPCH info must be 0 in dl_dpch_info list */ |
| 1177 | kal_uint8 dl_dpch_num; /* # of DPDCH on the RL */ |
| 1178 | FDD_dldpch_code_T dl_dpch_info[FDD_MAX_DLDPCH]; /* Information for each code channel */ |
| 1179 | |
| 1180 | FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */ |
| 1181 | /* This value should be consistent with the dpch_type field in dl_dpch_rla */ |
| 1182 | kal_uint8 fdpch_slot_format; /* [R7] F-DPCH only, range: 0~9. For R6 and previous version, this value should be 0 */ |
| 1183 | kal_bool fdpch_sttd_ind; /* [R6] F-DPCH only, TRUE when STTD is used. FALSE, otherwise */ |
| 1184 | |
| 1185 | kal_bool hsdsch_serving_rl_ind; /* [R5] The value "TRUE" indicates that this radio link is the serving HS-DSCH radio link. FALSE, otherwise */ |
| 1186 | kal_bool edch_serving_rl_ind; /* [R6] The value "TRUE" indicates that this radio link is the serving E-DCH radio link. FALSE, otherwise */ |
| 1187 | kal_bool sttd_valid; /* To judge if sttd value can be used by UL1 when doing SCS */ |
| 1188 | } FDD_dl_dpch_rl_T; |
| 1189 | |
| 1190 | typedef struct _FDD_dl_establish_T |
| 1191 | { |
| 1192 | kal_uint8 t312; /* T312 */ |
| 1193 | kal_uint16 n312; /* N312 */ |
| 1194 | kal_uint8 n313; /* N313 */ |
| 1195 | kal_uint8 t313; /* T313 */ |
| 1196 | kal_uint16 n315; /* N315 */ |
| 1197 | } FDD_dl_establish_T; |
| 1198 | |
| 1199 | #ifdef __UMTS_R7__ |
| 1200 | /* [R7] Determine whether UL1 need to store HS-SCCH order when release DCH channel */ |
| 1201 | typedef enum _FDD_dpch_release_type_E |
| 1202 | { |
| 1203 | FDD_DCH_RELEASE = 0, /* Don't need to store HS-SCCH order */ |
| 1204 | FDD_DCH_TRHHO_RELEASE, /* Need to store HS-SCCH order */ |
| 1205 | FDD_DCH_TRHHO_REVERT_RELEASE, /* Don't need to store HS-SCCH order */ |
| 1206 | FDD_DCH_TMHHO_RELEASE, /* Need to store HS-SCCH order */ |
| 1207 | FDD_DCH_TMHHO_REVERT_RELEASE, /* Don't need to store HS-SCCH order */ |
| 1208 | FDD_DCH_IRAT_RELEASE, /* Need to store HS-SCCH order */ |
| 1209 | FDD_DCH_ALL_RL_TIMING_MODIFY_RELEASE /* Need to store HS-SCCH order */ |
| 1210 | } FDD_dpch_release_type_E; |
| 1211 | #endif /* __UMTS_R7__ */ |
| 1212 | |
| 1213 | /*-------- TFCS related definition ----------------------*/ |
| 1214 | typedef struct _FDD_sig_gain_T |
| 1215 | { |
| 1216 | kal_uint8 beta_c; /* Bc. 0 ~ 15 */ |
| 1217 | kal_uint8 beta_d; /* Bd. 0 ~ 15 */ |
| 1218 | kal_int8 ref_tfc_id; /* Reference TFC ID. -1 ~ 3. */ |
| 1219 | /* 0 ~ 3 : This TFCI is a referenced id for other computed TFC. */ |
| 1220 | /* -1 : It is an invalid value. Means it will not be referenced by other TFC. */ |
| 1221 | } FDD_sig_gain_T; |
| 1222 | |
| 1223 | typedef union _FDD_gain_factor |
| 1224 | { |
| 1225 | kal_int8 computed_gain_id; /* For computed gain factor using reference TFC id. 0 ~ 3 */ |
| 1226 | FDD_sig_gain_T sig_gain; /* The signaled gain factor. */ |
| 1227 | } FDD_gain_factor; |
| 1228 | |
| 1229 | typedef struct _FDD_ul_dpch_tfc_T |
| 1230 | { |
| 1231 | kal_uint8 tfi_list[FDD_MAX_TRCH_NUM]; /* The list of TFI for this TFCI for UL DCH TrCH */ |
| 1232 | kal_bool sig_gain_ind; /* True: Gain factor is siganled. False: Gain factor is computed from reference TFCI */ |
| 1233 | FDD_gain_factor gain_factor; /* Gain factor */ |
| 1234 | } FDD_ul_dpch_tfc_T, FDD_ul_tfc_T; |
| 1235 | //} FDD_ul_dpch_tfc_T; |
| 1236 | |
| 1237 | typedef struct _FDD_rach_tfc_T |
| 1238 | { |
| 1239 | kal_uint8 tfi_list; /* The list of TFI for this TFCI. The number of TrCH for PRACH is 1. */ |
| 1240 | kal_bool sig_gain_ind; /* True: Gain factor is siganled. False: Gain factor is computed from reference TFCI */ |
| 1241 | kal_int8 msg_pwr_offset; /* Power offset between the last preamble and the control part of RACH */ |
| 1242 | FDD_gain_factor gain_factor; /* Gain factor */ |
| 1243 | } FDD_ul_rach_tfc_T; |
| 1244 | |
| 1245 | typedef struct _FDD_dl_tfc_T |
| 1246 | { |
| 1247 | kal_uint8 tfi_list[FDD_MAX_TRCH_NUM]; /* The list of TFI for this TFCI for DL TrCH */ |
| 1248 | } FDD_dl_tfc_T; |
| 1249 | |
| 1250 | /*-------- TrCH related definition ----------------------*/ |
| 1251 | |
| 1252 | #if 0 //Modify by Anthony Chin, for UL1D's convenience to maintain DB |
| 1253 | /* under construction !*/ |
| 1254 | /* under construction !*/ |
| 1255 | /* under construction !*/ |
| 1256 | /* under construction !*/ |
| 1257 | /* under construction !*/ |
| 1258 | /* under construction !*/ |
| 1259 | /* under construction !*/ |
| 1260 | /* under construction !*/ |
| 1261 | /* under construction !*/ |
| 1262 | /* under construction !*/ |
| 1263 | /* under construction !*/ |
| 1264 | /* under construction !*/ |
| 1265 | /* under construction !*/ |
| 1266 | /* under construction !*/ |
| 1267 | /* under construction !*/ |
| 1268 | /* under construction !*/ |
| 1269 | /* under construction !*/ |
| 1270 | #else |
| 1271 | typedef struct _FDD_trch_T |
| 1272 | { |
| 1273 | kal_uint8 trch_id; /* TrCH ID 1 ~ 32 */ |
| 1274 | kal_uint8 bit_offset; /* Bit offset. 0 ~ 7 */ |
| 1275 | FDD_tfs_T tfs; /* TFS of this TrCH */ |
| 1276 | kal_int8 target_bler; /* Diving the value of this field to 10 get the real BLER. -63 ~ 0 */ |
| 1277 | } FDD_trch_T, |
| 1278 | FDD_ul_rach_trch_T, |
| 1279 | FDD_ul_dch_trch_T, |
| 1280 | FDD_dl_fachpch_trch_T, |
| 1281 | FDD_dl_dch_trch_T; |
| 1282 | #endif |
| 1283 | |
| 1284 | /*-------- CCTrCH related definition ----------------------*/ |
| 1285 | typedef enum _FDD_cctrch_type_E |
| 1286 | { |
| 1287 | FDD_CCTRCH_UL_RACH, /* UL RACH CCTrCH */ |
| 1288 | FDD_CCTRCH_UL_DCH, /* UL DCH CCTrCH */ |
| 1289 | FDD_CCTRCH_DL_DCH, /* DL DCH CCTrCH */ |
| 1290 | FDD_CCTRCH_DL_PCH, /* DL PCH CCTrCH */ |
| 1291 | FDD_CCTRCH_DL_FACH, /* DL FACH CCTrCH */ |
| 1292 | FDD_CCTRCH_DL_BCH, /* DL BCH CCTrCH */ |
| 1293 | FDD_CCTRCH_DL_FDPCH, /* DL FDPCH, only for UL1 use */ |
| 1294 | /* __UMTS_R7__ BEGIN */ |
| 1295 | FDD_CCTRCH_DL_EPCH, /* DL EPCH CCTrCH */ |
| 1296 | /* __UMTS_R7__ END */ |
| 1297 | /* __UMTS_R8__ BEGIN */ |
| 1298 | FDD_CCTRCH_UL_EDCH /* UL EDCH CCTrCH */ |
| 1299 | /* __UMTS_R8__ END */ |
| 1300 | } FDD_cctrch_type_E; |
| 1301 | |
| 1302 | typedef struct _FDD_FACH_PCH_Info_T |
| 1303 | { |
| 1304 | kal_uint16 psc; /* Primary scrambling code */ |
| 1305 | kal_bool sttd; /* Indicate if STTD is used for P-CPICH for this RL */ |
| 1306 | /* If the value of tm is not equal to -1, UL1 will use this value */ |
| 1307 | /* If the value of tm is equal to -1, UL1 will not use this value */ |
| 1308 | kal_int16 rscp; /* Serving cell RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/ |
| 1309 | FDD_sccpch_info_T sccpch_info; /* Physical channel for PCH/FACH to be carried over */ |
| 1310 | kal_bool sccpch_optimization; /* True if FACH and PCH use the same S-CCPCH. valid only for configuring CTCH */ |
| 1311 | kal_uint16 tfc_num; /* # of TFC in TFCS */ |
| 1312 | FDD_dl_tfc_T tfcs[FDD_MAX_DL_TFC]; /* TFCS */ |
| 1313 | kal_uint8 active_dl_trch_list; /* Active TrCHs by bit string. MSB is the lowest numbered TrCH ID */ |
| 1314 | kal_uint8 trch_num; /* # of TrCHs carried on this CCTrCH */ |
| 1315 | FDD_dl_fachpch_trch_T trch_list[FDD_MAXFACHPCH]; /* List of TrCHs carried on this CCTrCH */ |
| 1316 | kal_bool pich_ctch_valid; /* True means "pich_ctch_info" is valid. */ |
| 1317 | FDD_pich_ctch_info_T pich_ctch_info; /* PICH or CTCH information */ |
| 1318 | } FDD_FACH_PCH_Info_T; |
| 1319 | |
| 1320 | /*-------- BCH related definition ----------------------*/ |
| 1321 | typedef struct _FDD_sib_info_T |
| 1322 | { |
| 1323 | kal_uint8 seg_count; /* SEG_COUNT 1 ~ 16 */ |
| 1324 | kal_uint16 sib_rep; /* SIB_REP 2^2 ~ 2^12 */ |
| 1325 | kal_uint16 sib_pos; /* SIB_POS 0 ~ sib_rep-2 */ |
| 1326 | kal_uint8 sib_off[FDD_MAX_SIB_SEG_COUNT]; /* SIB_OFF 2 ~ 32 The # of elements of this field is equal to seg_count-1 */ |
| 1327 | } FDD_sib_info_T; |
| 1328 | |
| 1329 | typedef enum _FDD_bch_priority_E |
| 1330 | { |
| 1331 | FDD_BCH_PRIOHIGH, /* Priority High */ |
| 1332 | FDD_BCH_PRIOMEDIUM, /* Priority Medium */ |
| 1333 | FDD_BCH_PRIOLOW, /* Priority Low */ |
| 1334 | FDD_BCH_PRIORR, /* Priority for SIB round robin */ |
| 1335 | } FDD_bch_priority_E; |
| 1336 | |
| 1337 | /*------- PHY_POST_TX_IND related ---------*/ |
| 1338 | typedef struct _FDD_tPhyPostTxMemInfo |
| 1339 | { |
| 1340 | kal_uint8 RbId; |
| 1341 | kal_uint8 *pContainer; |
| 1342 | } FDD_tPhyPostTxMemInfo; |
| 1343 | |
| 1344 | typedef struct _FDD_tPhyPostTxElement |
| 1345 | { |
| 1346 | kal_uint8 Num; |
| 1347 | FDD_tPhyPostTxMemInfo TxMemInfo[FDD_MAX_UL_TB]; |
| 1348 | #if defined(__GEMINI__) && defined(__UMTS_RAT__) |
| 1349 | kal_bool is_tx_suspend; /* This flag is only used for ULDCH when Gemini2.0. For RACH, this flag is always false. |
| 1350 | It indicates if there is SIM2 gap in the minTTI period of the released ul data, and UL1D will set this flag. */ |
| 1351 | kal_uint8 cfn; /* This value is only used for ULDCH when Gemini2.0. |
| 1352 | It indicates the cfn value that UL1C gets the ul data from UMAC. */ |
| 1353 | #endif |
| 1354 | } FDD_tPhyPostTxElement; |
| 1355 | |
| 1356 | typedef enum _FDD_tPhyPostTxType |
| 1357 | { |
| 1358 | FDD_POST_TX_RACH, |
| 1359 | FDD_POST_TX_DCH |
| 1360 | } FDD_tPhyPostTxType; |
| 1361 | |
| 1362 | /*-------- Data related definition ----------------------*/ |
| 1363 | typedef struct _FDD_dlTrchData |
| 1364 | { |
| 1365 | kal_bool valid_fpch; /* Raymond,20070327 Eric/Anthony add this, already notify UMAC */ |
| 1366 | kal_bool is_dual_TF; /* Andrew/Sean: For MAC to identify BTFD_DUAL_TF TrCh */ |
| 1367 | kal_int8 crc_status; /* Jay: For DUAL-TF TrCH power control*/ |
| 1368 | kal_uint8 trchId; /* TrCH ID */ |
| 1369 | kal_uint16 tb_size; /* TB size in bit. 0 ~ 4992 */ |
| 1370 | kal_uint16 num_tb; /* # of TB. 0 ~ 512 */ |
| 1371 | kal_uint16 addi_crc_size; /*Indicate additional crc size for MT6290E1 RXBRP DOB issue workaround*/ |
| 1372 | kal_bool is_hw_out_extra; /*L1 internal: Indicate whether HW output extra bytes for MT6290E1 RXBRP DOB issue workaround*/ |
| 1373 | } FDD_dlTrchData; |
| 1374 | |
| 1375 | typedef struct _FDD_ulTrchData |
| 1376 | { |
| 1377 | kal_uint8 trchId; /* TrCH ID */ |
| 1378 | kal_uint16 tb_size; /* TB size in bit. 0 ~ 4992 */ |
| 1379 | kal_uint16 num_tb; /* # of TB. 0 ~ 512 */ |
| 1380 | } FDD_ulTrchData; |
| 1381 | |
| 1382 | /*-------- Measurement related definition ----------------------*/ |
| 1383 | typedef struct _FDD_preferred_cell_list_T |
| 1384 | { |
| 1385 | kal_uint8 uarfcn_index; /* Frequency index */ |
| 1386 | /* Freq. array is contained in Frequency scan message */ |
| 1387 | kal_uint16 psc; /* Primary Scrambling code */ |
| 1388 | } FDD_preferred_cell_list_T; |
| 1389 | |
| 1390 | typedef enum _FDD_measured_type_E |
| 1391 | { |
| 1392 | FDD_INTRA_FREQENCY_MEASURED, |
| 1393 | FDD_INTER_FREQENCY_MEASURED, |
| 1394 | FDD_FREQ_SCAN_DETECTED, |
| 1395 | FDD_INTRA_SEC_FREQENCY_MEASURED /* [R9]Secondary intra-freq measurement */ |
| 1396 | } FDD_measured_type_E; |
| 1397 | |
| 1398 | |
| 1399 | typedef enum _FDD_cell_type_E |
| 1400 | { |
| 1401 | FDD_MONITORED, |
| 1402 | FDD_DETECTED, |
| 1403 | FDD_SPECIFIC_CELL_SEARCH, |
| 1404 | FDD_MONITORED_CELL_FOUND, |
| 1405 | FDD_DETECTED_CELL_FOUND |
| 1406 | } FDD_cell_type_E; |
| 1407 | |
| 1408 | typedef enum _FDD_meas_status_E |
| 1409 | { |
| 1410 | FDD_MS_INCLUDED, |
| 1411 | FDD_MS_NOTINCLUDED |
| 1412 | } FDD_meas_status_E; |
| 1413 | |
| 1414 | typedef enum _FDD_meas_tm_off_type_E |
| 1415 | { |
| 1416 | FDD_TM_OFF_RST, |
| 1417 | FDD_TM_OFF_DCH, |
| 1418 | FDD_TM_OFF_COMMON, |
| 1419 | FDD_TM_OFF_NA |
| 1420 | } FDD_meas_tm_off_type_E; |
| 1421 | |
| 1422 | typedef struct _FDD_measured_cell_T |
| 1423 | { |
| 1424 | kal_bool sttd; /* Indicate if STTD is used */ |
| 1425 | kal_int16 ec_no; /* Ec/No. Range: -100~0 means (-25~0) dB in 0.25 dB step */ |
| 1426 | kal_int16 rscp; /* RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/ |
| 1427 | kal_uint16 psc; /* Primary scrambling code */ |
| 1428 | kal_uint16 freq; /* DL UARFCN */ |
| 1429 | FDD_meas_tm_off_type_E tm_off_type; /*Indicate which field is applicable in this report*/ |
| 1430 | kal_int16 sfn; /* SFN in BCH. -1 ~ 4095 : -1 means unknown SFN */ |
| 1431 | kal_int16 off; /* FN offset. -1 ~ 4095 : -1 means unknown timing */ |
| 1432 | kal_int32 tm; /* Cell boundary. -1 ~ 38400*8-1 : -1 means unknown timing*/ |
| 1433 | kal_uint32 meas_sfn_diff; /* SFN_SFN difference in chips*/ |
| 1434 | FDD_meas_status_E meas_status; /* Indicate whether this cell is measured in this time */ |
| 1435 | FDD_cell_type_E cell_type; /* AS, MS or DS cell */ |
| 1436 | kal_bool update_timing; /* Indicates if it is recommended by UL1 for MEME to update cell timing based on FS result */ |
| 1437 | } FDD_measured_cell_T; |
| 1438 | |
| 1439 | typedef enum _FDD_meas_type_E |
| 1440 | { |
| 1441 | FDD_MT_INTRA_FREQ, /* Intra-frequency measurement */ |
| 1442 | FDD_MT_INTER_FREQ, /* Inter-frequency measurement */ |
| 1443 | FDD_MT_GSM_RAT /* GSM-RAT measurement */ |
| 1444 | } FDD_meas_type_E; |
| 1445 | |
| 1446 | typedef enum _FDD_sfn_priority_E |
| 1447 | { |
| 1448 | FDD_SFN_HIGH, |
| 1449 | FDD_SFN_MEDIUM, |
| 1450 | FDD_SFN_LOW, |
| 1451 | FDD_SFN_OFF |
| 1452 | } FDD_sfn_priority_E; |
| 1453 | |
| 1454 | typedef struct _FDD_meas_spec_T |
| 1455 | { |
| 1456 | kal_bool ds_meas_intra; /* Indicate if measure on intra-freq (and R9 secondary intra-freq) detected set*/ |
| 1457 | kal_bool ds_sfn_intra; /* Indicate if reading SFN of detected set */ |
| 1458 | #ifdef __UMTS_R10__ |
| 1459 | kal_bool ds_meas_inter; /* Indicate if measure on inter-freq detected set*/ |
| 1460 | #endif |
| 1461 | kal_int8 nc_nbr_dch; /* # of best cells to read SFN in DCH. -1 ~ 32 |
| 1462 | -1 means L1 should not read SFN for any cell |
| 1463 | 0 means L1 should read SFN for cells which have stronger CPICH measurement |
| 1464 | Other values means L1 should read FN for nc_nbr_dch cells from active set, monitored set and detected set. |
| 1465 | */ |
| 1466 | FDD_sfn_priority_E serving_prio; /* The priority of reading SFN of cells in active set. |
| 1467 | Only used when L1 is in DCH state and nc_nbr_dch > 0 */ |
| 1468 | FDD_sfn_priority_E monitor_prio; /* The priority of reading SFN of cells in monitored set. |
| 1469 | Only used when L1 is in DCH state and nc_nbr_dch > 0 */ |
| 1470 | FDD_sfn_priority_E detect_prio; /* The priority of reading SFN of cells in detected set. |
| 1471 | Only used when L1 is in DCH state and nc_nbr_dch > 0 */ |
| 1472 | kal_uint8 nc_nbr_rach; /* # of best cells to read SFN in non-DCH state. 0 ~ 32 */ |
| 1473 | } FDD_meas_spec_T; |
| 1474 | |
| 1475 | #ifdef __UMTS_R8__ |
| 1476 | typedef enum _FDD_higher_prio_search_support_E /* [Rel8][Absolute Priority Search] absolute priority search type */ |
| 1477 | { |
| 1478 | FDD_REGULAR_MEAS_ONLY, |
| 1479 | FDD_HIGHER_PRIORITY_ONLY, |
| 1480 | FDD_HIGHER_PRIORITY_AND_REGULAR_MEAS |
| 1481 | } FDD_higher_prio_search_support_E; |
| 1482 | #endif |
| 1483 | |
| 1484 | typedef struct _FDD_cell_info_list_T |
| 1485 | { |
| 1486 | kal_uint8 freq_index; /* UARFCN index */ |
| 1487 | kal_uint16 psc; /* Primary scrambling code */ |
| 1488 | kal_bool sttd; /* Indicate if STTD is used */ |
| 1489 | kal_bool read_sfn_ind; /* Indicate if read SFN */ |
| 1490 | kal_int16 ref_timing; /* Cell boundary. -1 ~ 38400-1 : -1 means unknown timing*/ |
| 1491 | kal_bool ref_timing_sib; /* Indicate if the reference timing comes from SIB or Meas. Control */ |
| 1492 | kal_int32 tm; /* Cell boundary. -1 ~ 38400*8-1 : -1 means unknown timing*/ |
| 1493 | kal_int16 off; /* FN offset. -1 ~ 4095 : -1 means unknown timing */ |
| 1494 | #ifdef __UMTS_R8__ |
| 1495 | FDD_higher_prio_search_support_E prio_search_control; /* [Rel8] Higher priority search control */ |
| 1496 | #endif |
| 1497 | } FDD_cell_info_list_T; |
| 1498 | |
| 1499 | typedef enum _FDD_event_cond_E |
| 1500 | { |
| 1501 | FDD_COND_ABOVE, /* Above threshold */ |
| 1502 | FDD_COND_ABOVE_EQUAL, /* Above or equal to threshold */ |
| 1503 | FDD_COND_BELOW, /* Below threshold */ |
| 1504 | FDD_COND_BELOW_EQUAL, /* Below or equal to threshold */ |
| 1505 | FDD_COND_EVENT_6C, /* [R6] Reporting event 6C: The UE Tx power reaches its minimum value */ |
| 1506 | FDD_COND_EVENT_6D /* [R6] Reporting event 6D: The UE Tx power reaches its maximum value */ |
| 1507 | } FDD_event_cond_E; |
| 1508 | |
| 1509 | typedef struct _FDD_meas_event_T |
| 1510 | { |
| 1511 | kal_uint8 event_id; /* Measurement event ID */ |
| 1512 | kal_uint8 measurement_id; /* Measurement ID */ |
| 1513 | kal_int16 threshold; |
| 1514 | kal_uint16 delay; /* Time to Triggered. 0 ~ 500 frames */ |
| 1515 | FDD_event_cond_E condition; /* Event triggered condition */ |
| 1516 | } FDD_meas_event_T; |
| 1517 | |
| 1518 | typedef struct _FDD_rl_meas_result_T |
| 1519 | { |
| 1520 | kal_uint8 rl_status; /* RL status */ |
| 1521 | /* 0 : Not detected */ |
| 1522 | /* 1 : Detected not used */ |
| 1523 | /* 2 : Detected and demodulated */ |
| 1524 | kal_uint16 psc; /* Scrambling code of this RL */ |
| 1525 | kal_uint32 time_diff; /* RX-TX Timd diff. 0 ~ 38400*8-1 */ |
| 1526 | } FDD_rl_meas_result_T; |
| 1527 | |
| 1528 | typedef enum _FDD_meas_act_E |
| 1529 | { |
| 1530 | FDD_MEAS_UNCHANGE, /* Unchange a cell list */ |
| 1531 | #ifndef __MTK_UL1_FDD__ /* 20080305: For Venus, still use old I/F */ |
| 1532 | FDD_MEAS_MODIFY, /* Modify an existed cell list */ |
| 1533 | #endif |
| 1534 | FDD_MEAS_DELETE, /* Delete an existed cell list */ |
| 1535 | FDD_MEAS_UPDATE /* Update the configuration of an existed cell list */ |
| 1536 | } FDD_meas_act_E; |
| 1537 | |
| 1538 | typedef enum _FDD_triggering_cause_E |
| 1539 | { |
| 1540 | FDD_REGULAR_REPORT, |
| 1541 | FDD_ONE_SHOT_MEASUREMENT, |
| 1542 | FDD_T_RESELECTION_EXPIRY |
| 1543 | } FDD_triggering_cause_E; |
| 1544 | |
| 1545 | typedef enum |
| 1546 | { |
| 1547 | FDD_CPHY_MEAS_STOP_CAUSE_NONE, /* none: fill when none stop */ |
| 1548 | FDD_CPHY_MEAS_STOP_CAUSE_REGULAR, /* normal stop */ |
| 1549 | FDD_CPHY_MEAS_STOP_CAUSE_4G3IRHO /* stop triggered by 4G3 IRHO */ |
| 1550 | } FDD_CPHY_MEASUREMENT_STOP_CAUSE_E; |
| 1551 | |
| 1552 | typedef struct _FDD_supplementary_meas_parameter_T |
| 1553 | { |
| 1554 | kal_bool intra_meas_one_shot_ind; /* When intra-F cell list is updated,to notify if UL1 needs to do one-shot measurement on intra-F or not */ |
| 1555 | kal_bool inter_meas_one_shot_ind; /* When inter-F cell list is updated,to notify if UL1 needs to do one-shot measurement on inter-F or not */ |
| 1556 | } FDD_supplementary_meas_parameter_T; |
| 1557 | |
| 1558 | typedef struct _FDD_supplementary_report_info_T |
| 1559 | { |
| 1560 | FDD_triggering_cause_E triggering_cause; /* The triggering cause of this meas tick */ |
| 1561 | kal_bool evaluate_req; /* To notify if L3 need to trigger cell evaluattion */ |
| 1562 | #ifdef __UMTS_R7__ |
| 1563 | kal_bool is_cycle2; /* Indicate whether the current DRX is cycle2 or not */ |
| 1564 | #endif /* __UMTS_R7__ */ |
| 1565 | } FDD_supplementary_report_info_T; |
| 1566 | |
| 1567 | /*-------- FACH MO related definition ----------------------*/ |
| 1568 | typedef struct _FDD_fach_mo_info_T |
| 1569 | { |
| 1570 | kal_uint8 n; /* # of frames in max TTI. 1,2,4,8 */ |
| 1571 | kal_uint8 k; /* MO cycle length coefficient. M_REP=2^k */ |
| 1572 | kal_bool inter_freq_ind; /* Indicate if inter-frequency meas in MO */ |
| 1573 | kal_bool inter_rat_ind; /* Indicate if inter-RAT meas in MO */ |
| 1574 | kal_bool inter_freq_cell_exist; /* Indicate if inter-freq cell in BA lsit is existed */ |
| 1575 | kal_bool inter_rat_cell_exist; /* Indicate if inter-rat cell in BA list is existed */ |
| 1576 | kal_uint16 start_off; /* C_RNTI % M_REP. 0 ~ 4095 */ |
| 1577 | } FDD_fach_mo_info_T; |
| 1578 | |
| 1579 | /*-------- Operation-Mode related definition ----------------------*/ |
| 1580 | typedef enum _FDD_mode_type_E |
| 1581 | { |
| 1582 | FDD_OM_SINGLE, /* Single Mode */ |
| 1583 | FDD_OM_MULTI /* Dual Mode */ |
| 1584 | } FDD_mode_type_E; |
| 1585 | |
| 1586 | typedef enum _FDD_rat_type_E |
| 1587 | { |
| 1588 | FDD_UL1_RAT_UMTS_ACTIVE, /* UMTS_Active */ |
| 1589 | FDD_UL1_RAT_UMTS_INACTIVE /* UMTS_Inactive */ |
| 1590 | } FDD_rat_type_E; |
| 1591 | |
| 1592 | typedef struct _FDD_duplex_mode_info_T |
| 1593 | { |
| 1594 | umts_duplex_mode_type source_umts_duplex_mode; |
| 1595 | umts_duplex_mode_type target_umts_duplex_mode; |
| 1596 | lte_duplex_mode_type source_lte_duplex_mode; |
| 1597 | lte_duplex_mode_type target_lte_duplex_mode; |
| 1598 | } FDD_duplex_mode_info_T; |
| 1599 | |
| 1600 | /*-------- Message(Primitive) related definition ----------------------*/ |
| 1601 | typedef enum _FDD_dch_setup_msg_type_E |
| 1602 | { |
| 1603 | FDD_DCH_SETUP, /* Used when DCH is established first time */ |
| 1604 | FDD_DCH_TRHHO, /* Used when timing reinitialized hard hand over */ |
| 1605 | FDD_DCH_TRHHO_REVERT, /* Used when timing reinitialized HHO revert */ |
| 1606 | FDD_DCH_TMHHO, /* Used when timing maintained hard hand over */ |
| 1607 | FDD_DCH_TMHHO_REVERT, /* Used when timing maintained HHO revert */ |
| 1608 | FDD_DCH_IRAT_REVERT, /* Used when Inter-RAT HHO revert */ |
| 1609 | FDD_DCH_ALL_RL_TIMING_MODIFY /* Used when all dpch rl timing offset is modified.*/ |
| 1610 | } FDD_dch_setup_msg_type_E; |
| 1611 | |
| 1612 | |
| 1613 | typedef enum _FDD_dch_modify_msg_type_E |
| 1614 | { |
| 1615 | FDD_DCH_RECONFIG, /* Used when DCH is reconfigured */ |
| 1616 | FDD_DCH_ASU, /* Used when active set update */ |
| 1617 | FDD_DCH_LOOP_MODE_2 /* Used when DCH loop back mode 2 */ |
| 1618 | } FDD_dch_modify_msg_type_E; |
| 1619 | |
| 1620 | |
| 1621 | typedef enum _FDD_msg_container_error_E /* Error cause of message container, MA only*/ |
| 1622 | { |
| 1623 | FDD_NONE, |
| 1624 | FDD_DCH_SETUP_FAIL |
| 1625 | } FDD_msg_container_error_E; |
| 1626 | |
| 1627 | typedef enum _FDD_TGPS_Action_E |
| 1628 | { |
| 1629 | FDD_TGPS_ACT_START, |
| 1630 | FDD_TGPS_ACT_STOP, |
| 1631 | FDD_TGPS_ACT_SUSPEND, |
| 1632 | FDD_TGPS_ACT_RESUME, |
| 1633 | FDD_TGPS_ACT_CONTINUE, |
| 1634 | FDD_TGPS_ACT_DELETE |
| 1635 | } FDD_TGPS_Action_E; |
| 1636 | |
| 1637 | typedef struct _FDD_TGPS_Action_T |
| 1638 | { |
| 1639 | kal_uint8 tgpsi; /* TGPIS of the TGPS on which the action and apply flag should be applied */ |
| 1640 | kal_bool apply_current; |
| 1641 | kal_bool apply_suspend; |
| 1642 | FDD_TGPS_Action_E action; |
| 1643 | } FDD_TGPS_Action_T; |
| 1644 | |
| 1645 | typedef enum _FDD_meas_control_E |
| 1646 | { |
| 1647 | FDD_MEAS_CTRL_INVALID, /* No meas. control action in current MSG_CONTAINER */ |
| 1648 | FDD_MEAS_CM_STOP, /* For inter-RAT HHO, stop CM measurement when receiving DCH release msg */ |
| 1649 | FDD_MAX_MEAS_CONTROL = FDD_MEAS_CM_STOP |
| 1650 | } FDD_meas_control_E; |
| 1651 | |
| 1652 | /*Add for improving full band FS efficiency -- by excluding some UARFCN or some frequency range*/ |
| 1653 | typedef enum _FDD_full_band_option_E |
| 1654 | { |
| 1655 | FDD_FULL_BAND_ONLY, /*Normal full band FS*/ |
| 1656 | FDD_FULL_BAND_AND_EXCLUDE /*Full band FS but the indicated frequency list/range will be excluded in the full band FS procedure*/ |
| 1657 | } FDD_full_band_option_E; |
| 1658 | #if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ ) |
| 1659 | typedef enum _FDD_uas_gemini_conflict_cause_enum |
| 1660 | { |
| 1661 | FDD_URR_NO_CONFLICT, |
| 1662 | FDD_URR_CONFLICT_WITH_GSM_BCCH, |
| 1663 | FDD_URR_CONFLICT_WITH_GSM_NBCCH, |
| 1664 | FDD_URR_CONFLICT_WITH_GSM_PCH, |
| 1665 | FDD_URR_CONFLICT_WITH_GSM_OTHERS, |
| 1666 | FDD_URR_CONFLICT_WITH_WCDMA_BCH_HIGH, |
| 1667 | FDD_URR_CONFLICT_WITH_WCDMA_BCH_LOW, |
| 1668 | FDD_URR_CONFLICT_WITH_WCDMA_PICH, |
| 1669 | FDD_URR_CONFLICT_WITH_WCDMA_OTHERS, |
| 1670 | FDD_URR_CONFLICT_WITH_LTE_BCCH, |
| 1671 | FDD_URR_CONFLICT_WITH_LTE_NBCCH_HIGH, |
| 1672 | FDD_URR_CONFLICT_WITH_LTE_NBCCH_MIDDLE, |
| 1673 | FDD_URR_CONFLICT_WITH_LTE_NBCCH_LOW, |
| 1674 | FDD_URR_CONFLICT_WITH_LTE_PCH, |
| 1675 | FDD_URR_CONFLICT_WITH_LTE_OTHERS |
| 1676 | } FDD_uas_gemini_conflict_cause_enum; |
| 1677 | |
| 1678 | #ifdef __MODIFY_CTCH_RECEPTION_PRIO__ |
| 1679 | typedef enum _FDD_rrce_gemini_priority_adjust_E |
| 1680 | { |
| 1681 | FDD_GEMINI_PRIORITY_ADJUST_ALL_NORMAL, /* Currently only used in Gemini2.0, to raise all rx/tx/BCH channel priority for RRC connection establishment or DL sync procedure. */ |
| 1682 | FDD_GEMINI_PRIORITY_ADJUST_ALL_HIGH, |
| 1683 | FDD_GEMINI_PRIORITY_ADJUST_CTCH_NORMAL, |
| 1684 | FDD_GEMINI_PRIORITY_ADJUST_CTCH_IMPRV, /* Added as a part of CBS improvement, to raise one SIM CTCH priority over other SIM CTCH*/ |
| 1685 | FDD_GEMINI_PRIORITY_ADJUST_CTCH_ETWS /* R8 ETWS feature, used for receiving ETWS CB. */ |
| 1686 | } FDD_rrce_gemini_priority_adjust_E; |
| 1687 | #else |
| 1688 | typedef enum _FDD_rrce_gemini_priority_adjust_E |
| 1689 | { |
| 1690 | FDD_GEMINI_PRIORITY_ADJUST_ALL, /* Currently only used in Gemini2.0, to raise all rx/tx/BCH channel priority for RRC connection establishment or DL sync procedure. */ |
| 1691 | FDD_GEMINI_PRIORITY_ADJUST_CTCH /* R8 ETWS feature, used for receiving ETWS CB. */ |
| 1692 | } FDD_rrce_gemini_priority_adjust_E; |
| 1693 | #endif |
| 1694 | |
| 1695 | #endif |
| 1696 | /*-------- [R5R6] HS-DSCH related ----------------------*/ |
| 1697 | typedef enum _FDD_hs_cqi_k_E |
| 1698 | { |
| 1699 | FDD_CQI_K_0, |
| 1700 | FDD_CQI_K_2, |
| 1701 | FDD_CQI_K_4, |
| 1702 | FDD_CQI_K_8, |
| 1703 | FDD_CQI_K_10, |
| 1704 | FDD_CQI_K_20, |
| 1705 | FDD_CQI_K_40, |
| 1706 | FDD_CQI_K_80, |
| 1707 | FDD_CQI_K_160, |
| 1708 | /* __UMTS_R7__ BEGIN */ |
| 1709 | FDD_CQI_K_16, |
| 1710 | FDD_CQI_K_32, |
| 1711 | FDD_CQI_K_64 |
| 1712 | /* __UMTS_R7__ END */ |
| 1713 | } FDD_hs_cqi_k_E; |
| 1714 | |
| 1715 | #ifdef __UMTS_R7__ |
| 1716 | /* [R7] FDD_UE_OWN_CATEGORY or FDD_CATEGORY_12. According to 25.331 CR#4159, UE should use the number of soft channel bits |
| 1717 | according to this category to decode HS-PDSCH TB. */ |
| 1718 | typedef enum _FDD_hs_harq_ir_type_E |
| 1719 | { |
| 1720 | FDD_UE_OWN_CATEGORY = 0, |
| 1721 | FDD_CATEGORY_12 |
| 1722 | } FDD_hs_harq_ir_type_E; |
| 1723 | |
| 1724 | typedef enum |
| 1725 | { |
| 1726 | FDD_E_SCELL_PRI = 0, |
| 1727 | FDD_E_SCELL_SEC, |
| 1728 | FDD_E_SCELL_TOTAL, /* 0:primary, 1: secondary */ |
| 1729 | FDD_E_SCELL_BOTH = FDD_E_SCELL_TOTAL, |
| 1730 | } FDD_edch_scell_E; |
| 1731 | |
| 1732 | typedef struct _FDD_hs_tb_size_list_T |
| 1733 | { |
| 1734 | kal_int8 tbs_index; /* [Range] 1~90, -1 if this is invalid */ |
| 1735 | kal_bool second_code_support; /* Indicates whether the second HS-PDSCH code is used for this TB size. |
| 1736 | If TRUE, the HS-PDSCH second code index value is the value of IE 'HSPDSCH Code Index' incremented by 1. */ |
| 1737 | } FDD_hs_tb_size_list_T; |
| 1738 | |
| 1739 | /* [R7] MAC entity types for handling HS-DSCH */ |
| 1740 | typedef enum _FDD_hs_mac_entity_type_E |
| 1741 | { |
| 1742 | FDD_HS_MAC_HS_ENTITY = 0, |
| 1743 | FDD_HS_MAC_EHS_ENTITY, |
| 1744 | FDD_HS_MAC_EHS_ENTITY_DC |
| 1745 | } FDD_hs_mac_entity_type_E; |
| 1746 | #endif /* __UMTS_R7__ */ |
| 1747 | |
| 1748 | typedef struct _FDD_hs_scch_info_T |
| 1749 | { |
| 1750 | kal_uint8 ssc; /* DL scrambling code to be applied for HS-DSCH and HS-SCCH */ |
| 1751 | kal_uint8 ovsf_code_num; /* Number of HS-SCCH to be received. Range:1~4 */ |
| 1752 | kal_uint8 ovsf[FDD_MAX_HS_SCCH_NUM]; /* OVSF code of HS-SCCH to be received */ |
| 1753 | } FDD_hs_scch_info_T; |
| 1754 | |
| 1755 | typedef struct _FDD_hs_meas_fb_info_T |
| 1756 | { |
| 1757 | kal_int8 meas_po; /* Measurement power offset. Range: -12~26 */ |
| 1758 | FDD_hs_cqi_k_E cqi_k; /* Measurement feedback cycle */ |
| 1759 | kal_uint8 cqi_repe_factor; /* CQI repetition factor. Range: 1~4 */ |
| 1760 | kal_uint8 delta_cqi; /* DeltaCQI. Range: 0~8 */ |
| 1761 | } FDD_hs_meas_fb_info_T; |
| 1762 | |
| 1763 | typedef struct _FDD_hs_harq_info_T |
| 1764 | { |
| 1765 | kal_uint8 process_num; /* Number of HARQ process. Range: 1~8 */ |
| 1766 | kal_bool explicit_partition; /* TRUE indicates explicit memory partition. FALSE indicates implicit memory partition */ |
| 1767 | kal_uint8 process_mem_size[FDD_MAX_HS_PROCESS_NUM]; /* index of HARQ memory size. range: 0~60, only valid when memory partition is explicit */ |
| 1768 | #ifdef __UMTS_R7__ |
| 1769 | FDD_hs_harq_ir_type_E harq_ir_type; /* FDD_UE_OWN_CATEGORY or FDD_CATEGORY_12. According to 25.331 CR#4159, UE should use the number of soft channel bits |
| 1770 | according to this category to decode HS-PDSCH TB. */ |
| 1771 | FDD_hs_mac_entity_type_E hs_mac_entity; /* enum for MAC-hs, MAC-ehs and MAC-ehs with DC */ |
| 1772 | #endif /* __UMTS_R7__ */ |
| 1773 | } FDD_hs_harq_info_T; |
| 1774 | |
| 1775 | typedef struct _FDD_hs_ulpc_info_T |
| 1776 | { |
| 1777 | kal_uint8 delta_ack; /* delta_ack. range: 0~8 */ |
| 1778 | kal_uint8 delta_nack; /* delta_nack. range: 0~8 */ |
| 1779 | kal_uint8 acknack_repe_factor; /* ack_nack_repetition_factor. range: 1~4 */ |
| 1780 | kal_uint8 harq_preamble_mode; /* [R6] range: 0~1, 1: indicates the preamble and postable are used |
| 1781 | for R5 and previous version, this value should be 0 */ |
| 1782 | } FDD_hs_ulpc_info_T; |
| 1783 | |
| 1784 | typedef enum |
| 1785 | { |
| 1786 | FDD_DSCH_NO_HRNTI_DETECTED = 0, /*HS-SCCH CRC check is failed*/ |
| 1787 | FDD_DSCH_D_HRNTI_DETECTED = 1, /*HS-PDSCH is indicated by HS-SCCH with dH-RNTI*/ |
| 1788 | FDD_DSCH_C_HRNTI_DETECTED = 2, /*HS-PDSCH is indicated by HS-SCCH with cH-RNTI*/ |
| 1789 | FDD_DSCH_B_HRNTI_DETECTED = 3, /*HS-PDSCH is indicated by HS-SCCH with bH-RNTI*/ |
| 1790 | FDD_DSCH_HRNTI_LESS = 4, /*HS-PDSCH is decoded blindly without HS-SCCH */ |
| 1791 | FDD_DSCH_NOT_RECEIVE = 5, /*This subframe is not received by HW */ |
| 1792 | |
| 1793 | } FDD_hs_dsch_decode_hrnti_E; |
| 1794 | |
| 1795 | typedef struct _FDD_hsdsch_data_T |
| 1796 | { |
| 1797 | kal_uint16 tb_size; /*[Range]: 137 ~ 27952 bits, MAC-hs PDU size */ |
| 1798 | kal_uint8 *p_data; /* The buffer contains MAC-hs data */ |
| 1799 | kal_uint8 *p_data_head; /* The address of the HDA buffer allocated by UMAC */ |
| 1800 | FDD_hs_dsch_decode_hrnti_E decode_hrnti; /*H-RNTI dectected info*/ |
| 1801 | kal_int8 pi_repeat_cycle; /* -1:invalid, -2:retransmission with CRC pass, 1~20:valid pi_repeat_cyle */ |
| 1802 | |
| 1803 | kal_uint8 decode_counter; /* For EM in UMAC */ |
| 1804 | } FDD_hsdsch_data_T; |
| 1805 | |
| 1806 | #ifdef __UMTS_R7__ |
| 1807 | typedef enum _FDD_mac_ehs_reset_cause_E |
| 1808 | { |
| 1809 | FDD_Treset_Expired |
| 1810 | } FDD_mac_ehs_reset_cause_E; |
| 1811 | #endif /* __UMTS_R7__ */ |
| 1812 | |
| 1813 | typedef enum _FDD_edch_tti_E |
| 1814 | { |
| 1815 | FDD_EDCH_TTI_2 = 0, |
| 1816 | FDD_EDCH_TTI_10 = 1, |
| 1817 | FDD_EDCH_TTI_TOTAL |
| 1818 | } FDD_edch_tti_E; |
| 1819 | |
| 1820 | typedef enum _FDD_edch_sf_E |
| 1821 | { |
| 1822 | FDD_EDCH_SF256 = 0, |
| 1823 | FDD_EDCH_SF128 = 1, |
| 1824 | FDD_EDCH_SF64 = 2, |
| 1825 | FDD_EDCH_SF32 = 3, |
| 1826 | FDD_EDCH_SF16 = 4, |
| 1827 | FDD_EDCH_SF8 = 5, |
| 1828 | FDD_EDCH_SF4 = 6, |
| 1829 | FDD_EDCH_ONE_PHCH = 6, |
| 1830 | FDD_EDCH_2SF4 = 7, |
| 1831 | FDD_EDCH_SF2 = 7, |
| 1832 | FDD_EDCH_2SF2 = 8, |
| 1833 | FDD_EDCH_2SF2AND2SF4 = 9, |
| 1834 | FDD_EDCH_2SF2AND2SF4_16QAM = 10, |
| 1835 | FDD_EDCH_SF_CNT = 11, |
| 1836 | FDD_EDCH_SF_NA = 12 |
| 1837 | } FDD_edch_sf_E; |
| 1838 | |
| 1839 | typedef enum |
| 1840 | { |
| 1841 | MPR_COMBO_BETA_D_ZERO_HS_ZERO = 0, |
| 1842 | MPR_COMBO_BETA_D_NON_ZERO_HS_ZERO, |
| 1843 | MPR_COMBO_BETA_D_ZERO_HS_NON_ZERO, |
| 1844 | MPR_COMBO_BETA_D_NON_ZERO_HS_NON_ZERO, |
| 1845 | MPR_COMBO_MAX |
| 1846 | } mpr_combo_E; |
| 1847 | |
| 1848 | typedef enum _FDD_edch_rv_config_E |
| 1849 | { |
| 1850 | FDD_EDCH_RV0 = 0, |
| 1851 | FDD_EDCH_RVTABLE = 1 |
| 1852 | } FDD_edch_rv_config_E; |
| 1853 | |
| 1854 | typedef struct _FDD_eagch_info_T |
| 1855 | { |
| 1856 | kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */ |
| 1857 | kal_uint8 ovsf; /* OVSF code. 0 ~ 255 */ |
| 1858 | kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell */ |
| 1859 | FDD_tx_diversity_E tx_diversity_mode; /* TX diversity mode of E-AGCH, and the value only can be FDD_DL_TX_NONE or FDD_DL_TX_STTD.*/ |
| 1860 | } FDD_eagch_info_T; |
| 1861 | |
| 1862 | typedef struct _FDD_ehich_info_T |
| 1863 | { |
| 1864 | kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */ |
| 1865 | kal_uint8 ovsf; /* OVSF code. 0 ~ 127 */ |
| 1866 | kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell (tauDPCH) */ |
| 1867 | FDD_tx_diversity_E tx_diversity_mode; /* TX diversity mode of E-HICH, and the value only can be FDD_DL_TX_NONE or FDD_DL_TX_STTD.*/ |
| 1868 | kal_uint8 signature_seq; /* E-HICH signature sequence 0~39*/ |
| 1869 | kal_uint8 tpc_index; /* TPC combination index. 0 ~ 5 */ |
| 1870 | } FDD_ehich_info_T; |
| 1871 | |
| 1872 | typedef struct _FDD_ergch_info_T |
| 1873 | { |
| 1874 | kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */ |
| 1875 | kal_uint8 ovsf; /* OVSF code. 0 ~ 127. Should be the same as E-HICH ovsf code */ |
| 1876 | kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell (tauDPCH) */ |
| 1877 | FDD_tx_diversity_E tx_diversity_mode; /* TX diversity mode of E-RGCH, and the value only can be FDD_DL_TX_NONE or FDD_DL_TX_STTD.*/ |
| 1878 | kal_uint8 signature_seq; /* E-RGCH signature sequence 0~39*/ |
| 1879 | kal_uint8 rg_comb_index; /* RG combination index. 0 ~ 5 */ |
| 1880 | } FDD_ergch_info_T; |
| 1881 | |
| 1882 | typedef struct _FDD_ref_etfci_T |
| 1883 | { |
| 1884 | kal_uint8 ref_etfci; /* Reference E-TFCI. 0~127 */ |
| 1885 | /* __UMTS_R7__ */ |
| 1886 | kal_uint8 ref_etfci_po; /* Reference E-TFCI PO. 0~31 */ |
| 1887 | } FDD_ref_etfci_T; |
| 1888 | |
| 1889 | #ifdef __UMTS_R8__ |
| 1890 | /* [R8] Minimum reduced E-DPDCH gain factor */ |
| 1891 | typedef enum _FDD_beta_ed_reduced_min_E |
| 1892 | { |
| 1893 | FDD_beta_ed_8_15 = 0, /* 8/15 */ |
| 1894 | FDD_beta_ed_11_15, /* 11/15 */ |
| 1895 | FDD_beta_ed_15_15, /* 15/15 */ |
| 1896 | FDD_beta_ed_21_15, /* 21/15 */ |
| 1897 | FDD_beta_ed_30_15, /* 30/15 */ |
| 1898 | FDD_beta_ed_42_15, /* 42/15 */ |
| 1899 | FDD_beta_ed_60_15, /* 60/15 */ |
| 1900 | FDD_beta_ed_84_15 /* 84/15 */ |
| 1901 | } FDD_beta_ed_reduced_min_E; |
| 1902 | #endif /* __UMTS_R8__ */ |
| 1903 | |
| 1904 | typedef struct _FDD_edpdch_info_T |
| 1905 | { |
| 1906 | /* __UMTS_R7__ */ |
| 1907 | kal_uint8 etfci_table_index; /* E-TFCI table index. 0~1. If the UE is operating in 16QAM, the value is increased by 2. 0~3. */ |
| 1908 | kal_uint8 num_of_ref_etfci; /* number of reference etfci. range:1~8 */ |
| 1909 | FDD_ref_etfci_T ref_etfci[FDD_MAX_REF_ETFCI_NUM]; /* reference E-TFCIs */ |
| 1910 | FDD_edch_sf_E max_ch_code; /* Max. channelisation code */ |
| 1911 | kal_uint8 ul_dpch_num; /* # of UL DPCH, range:0~FDD_MAX_ULDPCH*/ |
| 1912 | kal_uint8 pl_non_max; /* PLnon-max*100/4, range:11~25 */ |
| 1913 | #ifdef __UMTS_R8__ |
| 1914 | FDD_beta_ed_reduced_min_E beta_ed_reduced_min; /* Minimum reduced E-DPDCH gain factor */ |
| 1915 | #endif /* __UMTS_R8__ */ |
| 1916 | } FDD_edpdch_info_T; |
| 1917 | |
| 1918 | typedef struct _FDD_edpcch_info_T |
| 1919 | { |
| 1920 | kal_uint8 edpcch_po; /* E-DPCCH/DPCCH power offset. 0~8 */ |
| 1921 | #ifdef __UMTS_R7__ |
| 1922 | kal_uint8 etfci_boost; /* [Range] Integer(0..127)E-TFCI threshold beyond which boosting of EDPCCH is enabled */ |
| 1923 | kal_uint8 delta_t2tp; /* [Range] Integer (0..6)If E-TFCI-Boost is set to 127 this IE is not needed, otherwise it is mandatory. */ |
| 1924 | kal_bool edpdch_pwr_interpolation; /* True means EDPDCH power Interpolation formula is used, False means EDPDCH power |
| 1925 | Extrapolation formula is used for the computation of the gain factor £]ed */ |
| 1926 | #endif /* __UMTS_R7__ */ |
| 1927 | } FDD_edpcch_info_T; |
| 1928 | |
| 1929 | typedef struct _FDD_edch_harq_info_T |
| 1930 | { |
| 1931 | FDD_edch_rv_config_E edch_rv_config; /* RV config */ |
| 1932 | } FDD_edch_harq_info_T; |
| 1933 | |
| 1934 | |
| 1935 | /**********************************************************************************************************************/ |
| 1936 | /*********************************** UL1 Interface maintained by UL1D (Begin) *************************************/ |
| 1937 | /**********************************************************************************************************************/ |
| 1938 | /*UL1D*/typedef enum _FDD_hs_dsch_dc_data_source_E |
| 1939 | /*UL1D*/ |
| 1940 | { |
| 1941 | /*UL1D*/ FDD_PRIMARY_CELL = 0, /* data from primary cell, only hsdsch_data[] should be processed */ |
| 1942 | /*UL1D*/ FDD_SECONDARY_CELL = 1, /* data from secondary cell, only hsdsch_data2[] should be processed */ |
| 1943 | /*UL1D*/ FDD_DUAL_CELL = 2 /* data from dual cells, both hsdsch_data[] and hsdsch_data2[] should be processed*/ |
| 1944 | /*UL1D*/ |
| 1945 | } FDD_hs_dsch_dc_data_source_E; |
| 1946 | /*UL1D*/ |
| 1947 | /*UL1D*/typedef struct _FDD_uldch_data_req_T |
| 1948 | /*UL1D*/ |
| 1949 | { |
| 1950 | /*UL1D*/ kal_uint8 cfn; |
| 1951 | /*UL1D*/ kal_uint8 ul_mac_event; /* bit 0: UL DCH setup, */ |
| 1952 | /*UL1D*/ /* bit 1: UL DCH release */ |
| 1953 | /*UL1D*/ /* bit 2: UL DCH modify */ |
| 1954 | /*UL1D*/ kal_uint8 dpdch_num; |
| 1955 | /*UL1D*/ kal_bool restartSRB; |
| 1956 | /*UL1D*/ kal_bool tx_enable; |
| 1957 | /*UL1D*/ kal_bool tx_suspend; |
| 1958 | /*UL1D*/ kal_uint8 tfc_status[FDD_MAX_UL_TFC]; |
| 1959 | /*UL1D*/ |
| 1960 | } FDD_uldch_data_req_T; |
| 1961 | /*UL1D*/ |
| 1962 | /*UL1D*/ |
| 1963 | /*UL1D*/typedef struct _FDD_uldch_data_ind_T |
| 1964 | /*UL1D*/ |
| 1965 | { |
| 1966 | /*UL1D*/ kal_uint8 cfn; |
| 1967 | /*UL1D*/ kal_uint8 num_trch; |
| 1968 | /*UL1D*/ FDD_ulTrchData trchInfo[FDD_MAX_TRCH_NUM]; /* TrCH information including number of TB and TB size. Note that only 1 TRCH is included in RACH data. */ |
| 1969 | /*UL1D*/ kal_uint16 tfci; |
| 1970 | /*UL1D*/ kal_uint16 num_data[FDD_MAX_TRCH_NUM]; /* num_data[FDD_MAX_TRCH_NUM]. It means the total TB size on 1 TRCH. Value: 0 ~ FDD_MAX_UL_TB. */ |
| 1971 | /*UL1D*/ kal_uint8 *data[FDD_MAX_TRCH_NUM]; |
| 1972 | /*UL1D*/#ifdef UNIT_TEST |
| 1973 | /*UL1D*/ void *addr; |
| 1974 | /*UL1D*/#endif /* UNIT_TEST */ |
| 1975 | /*UL1D*/ |
| 1976 | } FDD_uldch_data_ind_T; |
| 1977 | /*UL1D*/ |
| 1978 | /*UL1D*//* Input parameters of FDD_umac_e_dch_tick_1() */ |
| 1979 | /*UL1D*/typedef struct _FDD_etfc_eval_info_req_T |
| 1980 | /*UL1D*/ |
| 1981 | { |
| 1982 | /*UL1D*/ kal_uint8 cfn; |
| 1983 | /*UL1D*/ kal_uint8 subframe; |
| 1984 | /*UL1D*/ kal_uint8 mac_event; /* bit0: setup; bit1: release; bit2: modify */ |
| 1985 | /*UL1D*/ FDD_edch_tti_E edch_tti; |
| 1986 | /*UL1D*/ kal_bool is_tx_suspend[FDD_E_SCELL_TOTAL]; |
| 1987 | /*UL1D*/#if defined( __GEMINI__ ) && defined( __UMTS_RAT__ ) |
| 1988 | /*UL1D*/ kal_bool is_gemini_tx_suspend; /* tx suspended due to Gemini */ |
| 1989 | /*UL1D*/#endif |
| 1990 | /*UL1D*/ kal_bool compressed_2ms; /* subframe overlaps TG (Refer this value only when 2ms TTI) */ |
| 1991 | /*UL1D*/ kal_uint8 num_of_non_dtx_slots_10ms; /* number of non-gap slots in the corresponding TTI (Refer this value only when 10ms TTI) */ |
| 1992 | /*UL1D*/ kal_uint8 e_agch_result[FDD_E_SCELL_TOTAL]; /* 0: Invalid 1:primary E-RNTI detected 2: secondary E-RNTI detected */ |
| 1993 | /*UL1D*/ kal_uint8 e_agch_data[FDD_E_SCELL_TOTAL]; |
| 1994 | /*UL1D*/ kal_uint8 e_hich_result_serving[FDD_E_SCELL_TOTAL]; /*0:DTX, 1:ACK, 2:invalid(shall ASSERT), 3:NACK */ |
| 1995 | /*UL1D*/ kal_uint8 e_hich_result_non_serving[FDD_E_SCELL_TOTAL]; /*0:DTX or NACK, 1:ACK, 2:invalid(shall ASSERT) , 3:invalid(shall ASSERT)*/ |
| 1996 | /*UL1D*/ kal_uint8 e_rgch_result_serving[FDD_E_SCELL_TOTAL]; /*0:HOLD or DTX, 1:UP, 2:invalid(shall ASSERT), 3:DOWN */ |
| 1997 | /*UL1D*/ kal_uint8 e_rgch_result_non_serving[FDD_E_SCELL_TOTAL]; /*0:HOLD or DTX, 1:invalid(shall ASSERT), 2:invalid(shall ASSERT), 3:DOWN */ |
| 1998 | /*UL1D*/ |
| 1999 | /*UL1D*/ kal_bool isTtiChangeSuspend; |
| 2000 | /*UL1D*/ kal_bool isServingCellChange[FDD_E_SCELL_TOTAL]; |
| 2001 | /*UL1D*/ kal_bool isServingCellChNotPartOfPrevEdchRls[FDD_E_SCELL_TOTAL]; |
| 2002 | /*UL1D*/ kal_uint16 mac_harq_event; /* bit 0: TTI change */ |
| 2003 | /*UL1D*/ /* bit 1: E-TFCI table index change */ |
| 2004 | /*UL1D*/ /* bit 2: HARQ RV ReConfiguration */ |
| 2005 | /*UL1D*/ /* bit 3: PLnon-max change */ |
| 2006 | /*UL1D*/ /* bit 4: Secondary cell activated */ |
| 2007 | /*UL1D*/ /* bit 5: Secondary cell deactivated */ |
| 2008 | /*UL1D*/ kal_bool insufficient_preamble[FDD_E_SCELL_TOTAL]; // Cannot transmit E-DCH due to insufficient UL DPCCH preamble. |
| 2009 | /*UL1D*/ kal_bool match_mac_dtx_cycle[FDD_E_SCELL_TOTAL]; // If the condition of last paragraph of 25.321 11.8.1.4 is fulfilled. |
| 2010 | /*UL1D*/ kal_bool is_dtx_cycle_2[FDD_E_SCELL_TOTAL]; // The DTX feature is configured by higher layers, and there has not been any E-DCH transmission for the last "Inactivity Threshold for UE DTX cycle 2" E-DCH TTIs. |
| 2011 | /*UL1D*/ kal_bool is_cedch; /*Notify UMAC if common EDCH or not*/ |
| 2012 | /*UL1D*/ kal_uint8 *sf_of_etfci; |
| 2013 | /*UL1D*/ kal_bool restartSRB; |
| 2014 | /*UL1D*/ kal_uint32 SlotTick_FRC; /* The absolute FRC (free-run counter) value of 1 slot ahead of Tx timing, the unit is micro-second (us) */ |
| 2015 | /*UL1D*/ /* Ex: FRC value of slot 8 will be provided if Tx on slot 9 */ |
| 2016 | /*UL1D*/ |
| 2017 | /*UL1D*/ |
| 2018 | } FDD_etfc_eval_info_req_T ; |
| 2019 | /*UL1D*/ |
| 2020 | /*UL1D*//* Output parameters of FDD_umac_e_dch_tick_1() */ |
| 2021 | /*UL1D*/typedef struct _FDD_etfc_eval_info_ind_T |
| 2022 | /*UL1D*/ |
| 2023 | { |
| 2024 | /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */ |
| 2025 | /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */ |
| 2026 | /*UL1D*/ kal_uint8 harq_id; /* 2ms TTI: 0..7, 10ms TTI: 0..3 */ |
| 2027 | /*UL1D*/ kal_bool tx_enable[FDD_E_SCELL_TOTAL]; /* true=on, false=off */ |
| 2028 | /*UL1D*/ kal_bool is_new_tx[FDD_E_SCELL_TOTAL]; |
| 2029 | /*UL1D*/ kal_uint8 delta_harq[FDD_E_SCELL_TOTAL]; |
| 2030 | /*UL1D*/ kal_bool collision_resolved; |
| 2031 | /*UL1D*/ kal_bool is_tebs_larger_than_0; |
| 2032 | /*UL1D*/ kal_uint8 serving_grant[FDD_E_SCELL_TOTAL]; |
| 2033 | /*UL1D*/ kal_uint8 non_scheduled_delta_harq; |
| 2034 | /*UL1D*/ kal_uint16 non_scheduled_data_size; |
| 2035 | /*UL1D*/ |
| 2036 | } FDD_etfc_eval_info_ind_T; |
| 2037 | /*UL1D*/ |
| 2038 | /*UL1D*//* Input parameters of FDD_umac_e_dch_tick_2() */ |
| 2039 | /*UL1D*/typedef struct _FDD_edch_data_req_T |
| 2040 | /*UL1D*/ |
| 2041 | { |
| 2042 | /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */ |
| 2043 | /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */ |
| 2044 | /*UL1D*/ FDD_edch_scell_E edch_cell; |
| 2045 | /*UL1D*/ FDD_edch_tti_E edch_tti; /* E-DCH TTI 2ms or 10ms */ |
| 2046 | /*UL1D*/ |
| 2047 | /*UL1D*/ kal_bool compressed_2ms; /* If the corresponding subframe overlaps TG (Refer this value only when 2ms TTI) */ |
| 2048 | /*UL1D*/ kal_uint8 num_of_non_dtx_slots_10ms; /* number of non-gap slots in the corresponding TTI (Refer this value only when 10ms TTI) */ |
| 2049 | /*UL1D*/ kal_uint8 *supported_etfci_bitmap; /* 2 LSB bits of [0] = etfci 0, 2 MSB bits of [31] = etfci 127. */ |
| 2050 | /*UL1D*/ /* 11=support, 10=power not support, 01=data size not support, 00=not support */ |
| 2051 | /*UL1D*/ kal_uint16 uph_in_dB; /*UE transmission power headroom reported by UL1(unit: dB)*/ |
| 2052 | /*UL1D*/ |
| 2053 | } FDD_edch_data_req_T ; |
| 2054 | /*UL1D*/ |
| 2055 | /*UL1D*//* Output parameters of FDD_umac_e_dch_tick_2() */ |
| 2056 | /*UL1D*/typedef struct _FDD_edch_data_ind_T |
| 2057 | /*UL1D*/ |
| 2058 | { |
| 2059 | /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */ |
| 2060 | /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */ |
| 2061 | /*UL1D*/ kal_bool tx_enable; /* true=on, false=off */ |
| 2062 | /*UL1D*/ kal_uint8 harq_id; /* 2ms TTI: 0..7, 10ms TTI: 0..3 */ |
| 2063 | /*UL1D*/ kal_bool is_new_tx; |
| 2064 | /*UL1D*/ kal_uint8 etfci; /* Range: 0..127 */ |
| 2065 | /*UL1D*/ kal_uint8 ntx1; /* 10 ms TTI: 8..15, 2ms TTI: don't care */ |
| 2066 | /*UL1D*/ kal_bool happy; |
| 2067 | /*UL1D*/ kal_uint8 rsn; /* Range: 0..3 */ |
| 2068 | /*UL1D*/ kal_uint8 delta_harq; /* Range: 0..6 */ |
| 2069 | /*UL1D*/ kal_uint16 tb_size; |
| 2070 | /*UL1D*/ kal_uint8 *data; /* The buffer contains MAC-es/e PDU data */ |
| 2071 | /*UL1D*/ /* Must be 4 bytes alignment */ |
| 2072 | /*UL1D*/ /* NULL if tx_enable == false */ |
| 2073 | /*UL1D*/ kal_uint8 tebs; /* SI of UMAC */ |
| 2074 | /*UL1D*/ kal_uint8 re_tx_num; /* re-transmission number */ |
| 2075 | /*UL1D*/ kal_uint32 ScheduledGrantPayloadBits; /* Configured SG bits; for RG judgement */ |
| 2076 | /*UL1D*/ kal_uint32 ScheduledGrantUsedBits; /* Used SG bits; for RG judgement */ |
| 2077 | /*UL1D*/ kal_bool scheduled; /* Whether this is scheduled E-DCH transmission or not. */ |
| 2078 | /*UL1D*/ |
| 2079 | } FDD_edch_data_ind_T; |
| 2080 | /*UL1D*/ |
| 2081 | /*UL1D*//* No output parameters of FDD_umac_e_dch_tick_3() */ |
| 2082 | /*UL1D*/ |
| 2083 | /*UL1D*//* Input parameters of FDD_umac_e_dch_tick_3() */ |
| 2084 | /*UL1D*/typedef struct _FDD_umac_edch_data_req_tick_3_T |
| 2085 | /*UL1D*/ |
| 2086 | { |
| 2087 | /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */ |
| 2088 | /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */ |
| 2089 | /*UL1D*/ |
| 2090 | } FDD_umac_edch_data_req_tick_3_T; |
| 2091 | /*UL1D*/ |
| 2092 | /*UL1D*//* Output parameters of FDD_umac_e_dch_tick_3() */ |
| 2093 | /*UL1D*/typedef struct _FDD_umac_edch_data_ind_tick_3_T |
| 2094 | /*UL1D*/ |
| 2095 | { |
| 2096 | /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */ |
| 2097 | /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */ |
| 2098 | /*UL1D*/ |
| 2099 | } FDD_umac_edch_data_ind_tick_3_T; |
| 2100 | /*UL1D*/ |
| 2101 | /*UL1D*/extern kal_bool FDD_UL1D_Check_ASU( kal_int32 added_cell_tm/* echips */, kal_uint16 added_cell_dpch_offset /* chips */ ); |
| 2102 | /*UL1D*/extern kal_bool FDD_UL1D_RxDualCarrier_Check( kal_uint16 pri_uarfcn, kal_uint16 sec_uarfcn, kal_int16 *pri_sec_diff ); |
| 2103 | /*UL1D*/extern kal_bool FDD_UL1D_RxMultiCarrier_Check( kal_uint16 *uarfcn_list, kal_uint8 num_uarfcn ); |
| 2104 | /*UL1D*/extern kal_bool FDD_UL1D_TxMultiCarrier_Check( kal_uint16 *uarfcn_list, kal_uint8 num_uarfcn ); |
| 2105 | /*UL1D*/kal_uint16/*100kHz*/ FDD_UL1D_RRC_UlUarfcnToFrequency( kal_uint16 uarfcn ); |
| 2106 | /**********************************************************************************************************************/ |
| 2107 | /*********************************** UL1 Interface maintained by UL1D (End) ***************************************/ |
| 2108 | /**********************************************************************************************************************/ |
| 2109 | /* Input parameters of FDD_umac_e_dch_tick_5() */ |
| 2110 | typedef struct |
| 2111 | { |
| 2112 | kal_bool match_mac_dtx_cycle; |
| 2113 | kal_uint8 long_preamble_target_cfn; // 0..255. |
| 2114 | kal_uint8 long_preamble_target_subframe; // 10ms=0, 2ms=0..4. |
| 2115 | FDD_edch_scell_E edch_cell; |
| 2116 | } FDD_etfc_eval_lpr_info_req_T; |
| 2117 | |
| 2118 | #ifdef __UMTS_R7__ |
| 2119 | /* [R7] Enumeration of rrc state. To distinguish the usage of HS-DSCH */ |
| 2120 | typedef enum _FDD_rrc_state_E |
| 2121 | { |
| 2122 | FDD_CELL_DCH, |
| 2123 | FDD_URA_PCH, |
| 2124 | FDD_CELL_PCH, |
| 2125 | FDD_IDLE_FACH, |
| 2126 | FDD_CELL_FACH |
| 2127 | } FDD_rrc_state_E; |
| 2128 | |
| 2129 | /* [R7] Enumeration of octet aligned table 9.2.3.2 is used, else bit aligned table 9.2.3.1 is used in [25.321]. */ |
| 2130 | typedef enum _FDD_hs_tbsize_table_E |
| 2131 | { |
| 2132 | FDD_BIT_ALIGNED = 0, |
| 2133 | FDD_OCTET_ALIGNED |
| 2134 | } FDD_hs_tbsize_table_E; |
| 2135 | |
| 2136 | /* [R7] Enumeration of dtx_drx_status. */ |
| 2137 | typedef enum _FDD_dtx_drx_status_E |
| 2138 | { |
| 2139 | FDD_DTX_DRX_OFF = 0, /* Disable CPC operation */ |
| 2140 | FDD_DTX_DRX_NEW_TIMING, /* Use new CPC configuration */ |
| 2141 | FDD_DTX_DRX_ON_REVERT, /* Uses the old CPC configuration when HHO revert. Consider oly the HS-SCCH orders which were acknowledged prior to the activation timer of the received message. */ |
| 2142 | FDD_DTX_DRX_ON_HS_SERV_CELL_CHANGE, /* Uses the old CPC configuration when serving cell was changed. Consider the HS-SCCH order were never received. */ |
| 2143 | FDD_DTX_DRX_ALL_RL_TIMING_MODIFY, /* If the CPC choice timing is ¡§continue¡¨ when receiving ALL RL TIMING MODIFY, Uses the old CPC configuration. */ |
| 2144 | FDD_DTX_DRX_INVALID /* Invalid DTX_DRX status */ |
| 2145 | } FDD_dtx_drx_status_E; |
| 2146 | |
| 2147 | /* [R7] Enumeration of enabling delay. Uint is radio frame. */ |
| 2148 | typedef enum _FDD_enabling_delay_E |
| 2149 | { |
| 2150 | FDD_ED_0 = 0, |
| 2151 | FDD_ED_1, |
| 2152 | FDD_ED_2, |
| 2153 | FDD_ED_4, |
| 2154 | FDD_ED_8, |
| 2155 | FDD_ED_16, |
| 2156 | FDD_ED_32, |
| 2157 | FDD_ED_64, |
| 2158 | FDD_ED_128 |
| 2159 | } FDD_enabling_delay_E; |
| 2160 | |
| 2161 | /* [R7] Enumeration of ue_dtx_cycle2_inactivity_threshold. Uint is E-DCH TTIs. */ |
| 2162 | typedef enum _FDD_ue_dtx_cycle2_inactivity_threshold_E |
| 2163 | { |
| 2164 | FDD_dtx_cycle2_inaTrHd_1 = 0, |
| 2165 | FDD_dtx_cycle2_inaTrHd_4, |
| 2166 | FDD_dtx_cycle2_inaTrHd_8, |
| 2167 | FDD_dtx_cycle2_inaTrHd_16, |
| 2168 | FDD_dtx_cycle2_inaTrHd_32, |
| 2169 | FDD_dtx_cycle2_inaTrHd_64, |
| 2170 | FDD_dtx_cycle2_inaTrHd_128, |
| 2171 | FDD_dtx_cycle2_inaTrHd_256 |
| 2172 | } FDD_ue_dtx_cycle2_inactivity_threshold_E; |
| 2173 | |
| 2174 | /* [R7] Enumeration of ue_dtx_long_preamble_length. Uint is slot. */ |
| 2175 | typedef enum _FDD_ue_dtx_long_preamble_length_E |
| 2176 | { |
| 2177 | FDD_slot_2 = 0, |
| 2178 | FDD_slot_4, |
| 2179 | FDD_slot_15, |
| 2180 | FDD_slot_invalid |
| 2181 | } FDD_ue_dtx_long_preamble_length_E, FDD_dtx_pream_len_E; |
| 2182 | |
| 2183 | /* [R7] Enumeration of cqi_dtx_timer period. Uint is subframe. */ |
| 2184 | typedef enum _FDD_cqi_dtx_timer_E |
| 2185 | { |
| 2186 | FDD_subframe_0 = 0, |
| 2187 | FDD_subframe_1, |
| 2188 | FDD_subframe_2, |
| 2189 | FDD_subframe_4, |
| 2190 | FDD_subframe_8, |
| 2191 | FDD_subframe_16, |
| 2192 | FDD_subframe_32, |
| 2193 | FDD_subframe_64, |
| 2194 | FDD_subframe_128, |
| 2195 | FDD_subframe_256, |
| 2196 | FDD_subframe_512, |
| 2197 | FDD_subframe_infinity |
| 2198 | } FDD_cqi_dtx_timer_E; |
| 2199 | |
| 2200 | /* [R7] Enumeration of ue_dpcch_burst. Uint is subframe. */ |
| 2201 | typedef enum _FDD_ue_dpcch_burst_E |
| 2202 | { |
| 2203 | FDD_burst_1 = 0, |
| 2204 | FDD_burst_2, |
| 2205 | FDD_burst_5 |
| 2206 | } FDD_ue_dpcch_burst_E; |
| 2207 | |
| 2208 | /* [R7] Enumeration of mac_inactivity_threshold. Uint is E-DCH TTI. */ |
| 2209 | typedef enum _FDD_mac_inactivity_threshold_E |
| 2210 | { |
| 2211 | FDD_mac_inaTrHd_1 = 0, |
| 2212 | FDD_mac_inaTrHd_2, |
| 2213 | FDD_mac_inaTrHd_4, |
| 2214 | FDD_mac_inaTrHd_8, |
| 2215 | FDD_mac_inaTrHd_16, |
| 2216 | FDD_mac_inaTrHd_32, |
| 2217 | FDD_mac_inaTrHd_64, |
| 2218 | FDD_mac_inaTrHd_128, |
| 2219 | FDD_mac_inaTrHd_256, |
| 2220 | FDD_mac_inaTrHd_512, |
| 2221 | FDD_mac_inaTrHd_infinity |
| 2222 | } FDD_mac_inactivity_threshold_E; |
| 2223 | |
| 2224 | /* [R7] Enumeration of ue_rx_cycle. Uint is subframe. */ |
| 2225 | typedef enum _FDD_ue_drx_cycle_E |
| 2226 | { |
| 2227 | FDD_drx_cycle_4 = 0, |
| 2228 | FDD_drx_cycle_5, |
| 2229 | FDD_drx_cycle_8, |
| 2230 | FDD_drx_cycle_10, |
| 2231 | FDD_drx_cycle_16, |
| 2232 | FDD_drx_cycle_20 |
| 2233 | } FDD_ue_drx_cycle_E; |
| 2234 | |
| 2235 | /* [R7] Enumeration of ue_drx_cycle_inactivity_threshold. Uint is subframe. */ |
| 2236 | typedef enum _FDD_ue_drx_cycle_inactivity_threshold_E |
| 2237 | { |
| 2238 | FDD_drx_cycle_inaTrHd_0 = 0, |
| 2239 | FDD_drx_cycle_inaTrHd_1, |
| 2240 | FDD_drx_cycle_inaTrHd_2, |
| 2241 | FDD_drx_cycle_inaTrHd_4, |
| 2242 | FDD_drx_cycle_inaTrHd_8, |
| 2243 | FDD_drx_cycle_inaTrHd_16, |
| 2244 | FDD_drx_cycle_inaTrHd_32, |
| 2245 | FDD_drx_cycle_inaTrHd_64, |
| 2246 | FDD_drx_cycle_inaTrHd_128, |
| 2247 | FDD_drx_cycle_inaTrHd_256, |
| 2248 | FDD_drx_cycle_inaTrHd_512 |
| 2249 | } FDD_ue_drx_cycle_inactivity_threshold_E; |
| 2250 | |
| 2251 | /* [R7] Enumeration of ue_grantMonitoring_inactivity_threshold. Uint is subframe. */ |
| 2252 | typedef enum _FDD_ue_grantMonitoring_inactivity_threshold_E |
| 2253 | { |
| 2254 | FDD_graMon_inaTrhd_0 = 0, |
| 2255 | FDD_graMon_inaTrhd_1, |
| 2256 | FDD_graMon_inaTrhd_2, |
| 2257 | FDD_graMon_inaTrhd_4, |
| 2258 | FDD_graMon_inaTrhd_8, |
| 2259 | FDD_graMon_inaTrhd_16, |
| 2260 | FDD_graMon_inaTrhd_32, |
| 2261 | FDD_graMon_inaTrhd_64, |
| 2262 | FDD_graMon_inaTrhd_128, |
| 2263 | FDD_graMon_inaTrhd_256 |
| 2264 | } FDD_ue_grantMonitoring_inactivity_threshold_E; |
| 2265 | |
| 2266 | /* [R7] HS-SCCH less mode status in CELL_DCH state */ |
| 2267 | typedef enum _FDD_hs_scch_less_status_E |
| 2268 | { |
| 2269 | FDD_HS_SCCH_LESS_OFF = 0, /* disable HS-SCCH less operation and all HS-SCCH less parameters are invalid. */ |
| 2270 | FDD_HS_SCCH_LESS_ON, /* use new HS-SCCH less configuration and reset order. */ |
| 2271 | FDD_HS_SCCH_LESS_ON_REVERT, /* Uses the old HS-SCCH less configuration when HHO revert or 3G to 2G inter-RAT procedure revert. */ |
| 2272 | FDD_HS_SCCH_LESS_ALL_RL_TIMING_MODIFY, /* If the HS-SCCH less operation choice timing is "continue" when receiving ALL RL TIMING MODIFY, |
| 2273 | * uses the old HS-SCCH less configuration without reset order. */ |
| 2274 | FDD_HS_SCCH_LESS_INVALID /* SLCE internal use, won't config this enum to UL1. */ |
| 2275 | } FDD_hs_scch_less_status_E; |
| 2276 | #endif /* __UMTS_R7__ */ |
| 2277 | |
| 2278 | #ifdef __UMTS_R8__ |
| 2279 | /* [R8] Enumeration of enhanced CELL_FACH DRX status */ |
| 2280 | typedef enum _FDD_hs_cell_fach_drx_status_E |
| 2281 | { |
| 2282 | FDD_DRX_OFF = 0, /* No DRX in CELL_FACH state or ETWS reception is on-going */ |
| 2283 | FDD_DRX_ON_NORMAL, /* UL1 should start CELL_FACH DRX when the normal criterion is fulfilled */ |
| 2284 | FDD_DRX_ON_ETWS_END, /* SLCE should set this enum when the ETWS procedure ends */ |
| 2285 | FDD_DRX_INVALID /* SLCE internal use. Invalid for UL1. */ |
| 2286 | } FDD_hs_cell_fach_drx_status_E; |
| 2287 | |
| 2288 | /* [R8] inactivity timer to start HS CELL_FACH DRX */ |
| 2289 | typedef enum _FDD_hs_t321_E |
| 2290 | { |
| 2291 | FDD_t321_100 = 0, /* 100ms */ |
| 2292 | FDD_t321_200 = 1, /* 200ms */ |
| 2293 | FDD_t321_400 = 2, /* 400ms */ |
| 2294 | FDD_t321_800 = 3 /* 800ms */ |
| 2295 | } FDD_hs_t321_E; |
| 2296 | |
| 2297 | /* Length of inactivity timer T321/T328/T329 */ |
| 2298 | typedef enum |
| 2299 | { |
| 2300 | FDD_EFACH_DRX_1_LEVEL, |
| 2301 | FDD_EFACH_DRX_2_LEVEL |
| 2302 | } FDD_hs_cell_fach_drx_level_E; |
| 2303 | |
| 2304 | /* Length of inactivity timer T321/T328/T329 */ |
| 2305 | typedef enum |
| 2306 | { |
| 2307 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_INVALID, |
| 2308 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_20MS, |
| 2309 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_40MS, |
| 2310 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_60MS, |
| 2311 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_80MS, |
| 2312 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_100MS, |
| 2313 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_200MS, |
| 2314 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_400MS, |
| 2315 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_500MS, |
| 2316 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_800MS, |
| 2317 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_1000MS, |
| 2318 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_2000MS, |
| 2319 | FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_4000MS |
| 2320 | } FDD_hs_cell_fach_drx_status_timer_length_E; |
| 2321 | |
| 2322 | /* Length of EFACH DRX cycle */ |
| 2323 | typedef enum |
| 2324 | { |
| 2325 | FDD_EFACH_DRX_CYCLE_LEN_INVALID, |
| 2326 | FDD_EFACH_DRX_CYCLE_LEN_2_FRAMES, |
| 2327 | FDD_EFACH_DRX_CYCLE_LEN_4_FRAMES, |
| 2328 | FDD_EFACH_DRX_CYCLE_LEN_8_FRAMES, |
| 2329 | FDD_EFACH_DRX_CYCLE_LEN_16_FRAMES, |
| 2330 | FDD_EFACH_DRX_CYCLE_LEN_32_FRAMES, |
| 2331 | FDD_EFACH_DRX_CYCLE_LEN_64_FRAMES, |
| 2332 | FDD_EFACH_DRX_CYCLE_LEN_128_FRAMES, |
| 2333 | FDD_EFACH_DRX_CYCLE_LEN_256_FRAMES, |
| 2334 | FDD_EFACH_DRX_CYCLE_LEN_512_FRAMES |
| 2335 | } FDD_hs_cell_fach_drx_cycle_E; |
| 2336 | |
| 2337 | /* Length of EFACH DRX burst */ |
| 2338 | typedef enum |
| 2339 | { |
| 2340 | FDD_EFACH_DRX_BURST_LEN_INVALID, |
| 2341 | FDD_EFACH_DRX_BURST_LEN_1_FRAMES, |
| 2342 | FDD_EFACH_DRX_BURST_LEN_2_FRAMES, |
| 2343 | FDD_EFACH_DRX_BURST_LEN_4_FRAMES, |
| 2344 | FDD_EFACH_DRX_BURST_LEN_8_FRAMES, |
| 2345 | FDD_EFACH_DRX_BURST_LEN_16_FRAMES, |
| 2346 | FDD_EFACH_DRX_BURST_LEN_2_SUBFRAMES, |
| 2347 | FDD_EFACH_DRX_BURST_LEN_4_SUBFRAMES |
| 2348 | } FDD_hs_cell_fach_drx_rx_burst_E; |
| 2349 | |
| 2350 | #if 0 |
| 2351 | /* under construction !*/ |
| 2352 | /* under construction !*/ |
| 2353 | /* under construction !*/ |
| 2354 | /* under construction !*/ |
| 2355 | /* under construction !*/ |
| 2356 | /* under construction !*/ |
| 2357 | /* under construction !*/ |
| 2358 | /* under construction !*/ |
| 2359 | /* under construction !*/ |
| 2360 | /* under construction !*/ |
| 2361 | /* under construction !*/ |
| 2362 | /* under construction !*/ |
| 2363 | /* under construction !*/ |
| 2364 | /* under construction !*/ |
| 2365 | /* under construction !*/ |
| 2366 | /* under construction !*/ |
| 2367 | /* under construction !*/ |
| 2368 | /* under construction !*/ |
| 2369 | #endif |
| 2370 | |
| 2371 | /* [R8] variable to control UL1 DC HS-DSCH receiving */ |
| 2372 | typedef enum _FDD_dc_hsdpa_status_E |
| 2373 | { |
| 2374 | FDD_DC_HSDPA_OFF = 0, /* Disable DC-HSDPA operation and all DC-HSDPA parameters are invalid. */ |
| 2375 | FDD_DC_HSDPA_ON, /* Use new DC-HSDPA configuration and reset order */ |
| 2376 | FDD_DC_HSDPA_ON_REVERT, /* Uses the old DC-HSDPA configuration when HHO revert or 3G to 2G inter-RAT procedure revert. */ |
| 2377 | FDD_DC_HSDPA_ALL_RL_TIMING_MODIFY, /* If the DC-HSDPA choice timing is "continue" when receiving ALL_RL_TIMING_MODIFY, |
| 2378 | * uses the old DC-HSDPA configuration without reset order. */ |
| 2379 | FDD_DC_HSDPA_ON_WITHOUT_RESET_ORDER, /* Use new DC-HSDPA configuration and do not reset order */ |
| 2380 | FDD_DC_HSDPA_INVALID /* SLCE internal use, won't config this enum to UL1 */ |
| 2381 | } FDD_dc_hsdpa_status_E; |
| 2382 | |
| 2383 | /* [R8] Specify that E-DCH transmission is in dedicated state or common state */ |
| 2384 | typedef enum _FDD_edch_transmission_type_E |
| 2385 | { |
| 2386 | FDD_EDCH_IN_DCH_STATE = 0, /* E-DCH allocated in dedicated state */ |
| 2387 | FDD_EDCH_IN_COMMON_STATE /* E-DCH allocated in common state */ |
| 2388 | } FDD_edch_transmission_type_E; |
| 2389 | |
| 2390 | /* [R8] common E-DCH suspend cause. UL1 Internal use */ |
| 2391 | typedef enum _FDD_cedch_suspend_cause_type_E |
| 2392 | { |
| 2393 | FDD_CEDCH_NONE = 0, /* no common EDCH */ |
| 2394 | FDD_CEDCH_SUSPEND_RLF, /* common EDCH terminate due to RLF */ |
| 2395 | FDD_CEDCH_SUSPEND_SYNCAA_FAIL, /* common EDCH terminate due to Sync AA failure */ |
| 2396 | FDD_CEDCH_SUSPEND_PROCESS_TERMINATION, /* common EDCH terminate from UMAC */ |
| 2397 | FDD_CEDCH_SUSPEND_PREAMBLE, /* common EDCH terminate when AI result has not been received by UL1C */ |
| 2398 | FDD_CEDCH_SUSPEND_CHANNEL_RELEASE /* common EDCH terminate due to channel release */ |
| 2399 | } FDD_cedch_suspend_cause_type_E; |
| 2400 | |
| 2401 | /* [R8] Transport channel type in random access procedure */ |
| 2402 | typedef enum _FDD_cell_fach_ul_trch_type_E |
| 2403 | { |
| 2404 | FDD_CELL_FACH_UL_TRCH_TYPE_RACH = 0, /* random access attemp for RACH transmission */ |
| 2405 | FDD_CELL_FACH_UL_TRCH_TYPE_EDCH /* random access attemp for E-DCH transmission */ |
| 2406 | } FDD_cell_fach_ul_trch_type_E; |
| 2407 | #endif /* __UMTS_R8__ */ |
| 2408 | |
| 2409 | |
| 2410 | #ifdef __UMTS_R7__ |
| 2411 | typedef struct _FDD_hs_scch_less_info_T |
| 2412 | { |
| 2413 | FDD_hs_scch_less_status_E hs_scch_less_status; /* HS-SCCH less mode control flag */ |
| 2414 | kal_uint8 hs_scch_less_hspdsch_code_index; /* [Range] Integer(1..15) Index of the first HS-PDSCH code */ |
| 2415 | FDD_hs_tb_size_list_T hs_scch_less_tb_size_list[FDD_MAX_SCCH_LESS_BLK_NUM]; /* 1..<maxHSSCCHLessTrBlk > maxHSSCCHLessTrBlk = 4 */ |
| 2416 | } FDD_hs_scch_less_info_T; |
| 2417 | |
| 2418 | typedef struct _FDD_hs_fach_pch_rl_info_T |
| 2419 | { |
| 2420 | kal_uint16 dl_freq; /* DL UARFCN */ |
| 2421 | kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */ |
| 2422 | kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */ |
| 2423 | kal_uint16 psc; /* Primary scrambling code */ |
| 2424 | kal_bool sttd; /* Indicate if STTD is used for P-CPICH for this RL */ |
| 2425 | /* If the value of tm is not equal to -1, UL1 will use this value */ |
| 2426 | /* If the value of tm is equal to -1, UL1 will not use this value */ |
| 2427 | kal_int16 rscp; /* Serving cell RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/ |
| 2428 | } FDD_hs_fach_pch_rl_info_T; |
| 2429 | |
| 2430 | typedef struct _FDD_hs_dtx_drx_timing_info_T |
| 2431 | { |
| 2432 | FDD_enabling_delay_E ED; /* Time threshold the UE waits until enabling a new timing pattern for DTX/ DRX operation. Uint is radio frame. */ |
| 2433 | kal_uint8 ue_dtx_drx_offset; /* [Range]: 0~159 Units of subframes. Offset of the DTX and DRX cycles at the given TTI. */ |
| 2434 | } FDD_hs_dtx_drx_timing_info_T; |
| 2435 | |
| 2436 | typedef struct _FDD_hs_dtx_param_T |
| 2437 | { |
| 2438 | kal_bool ue_dtx_on; /* DTX operation enable/ disable */ |
| 2439 | kal_bool tti_change; /* E-DCH TTI is change to 2ms->10ms or 10ms->2ms */ |
| 2440 | kal_uint8 ue_dtx_cycle1; /* DPCCH activity pattern.(1, 5, 10, 20 subframes for 10 ms TTI; 1, 4, 5, 8, 10, 16, 20 subframes for 2 ms TTI) */ |
| 2441 | kal_uint8 ue_dtx_cycle2; /* DPCCH activity pattern.(5, 10, 20, 40, 80, 160 subframes for 10 ms TTI;4, 5, 8, 10, 16, 20, 32, 40, 64, 80, 128, 160 subframes for 2 ms TTI) */ |
| 2442 | FDD_ue_dtx_cycle2_inactivity_threshold_E cycle2_inactivity_threshold; /* When to activate the UE DTX cycle 2 after the last uplink data transmission */ |
| 2443 | FDD_ue_dtx_long_preamble_length_E preamble_length; /* Uplink preamble length. Units of slots.Default value is 2 slots */ |
| 2444 | FDD_cqi_dtx_timer_E timer_length; /* Number of subframes after an HS-DSCH reception during which the CQI reports have higher priority than the DTX pattern and are transmitted according to the regular CQI pattern */ |
| 2445 | FDD_ue_dpcch_burst_E dpcch_burst1; /* Length of DPCCH transmission when UE DTX cycle 1 is active Units of sub-frames */ |
| 2446 | FDD_ue_dpcch_burst_E dpcch_burst2; /* Length of DPCCH transmission when UE DTX cycle 2 is active Units of sub-frames */ |
| 2447 | |
| 2448 | kal_uint8 mac_dtx_cycle; /* Pattern of time instances where the start of uplink E-DCH transmission after inactivity is allowed.(5, 10, 20 subframes for 10 ms TTI; 1, 4, 5, 8, 10, 16, 20 subframes for 2 ms TTI */ |
| 2449 | FDD_mac_inactivity_threshold_E mac_inactivity_threshold; /* E-DCH inactivity time after which the UE can start E-DCH transmission only at given time. */ |
| 2450 | } FDD_hs_dtx_param_T; |
| 2451 | |
| 2452 | typedef struct _FDD_hs_drx_param_T |
| 2453 | { |
| 2454 | kal_bool ue_drx_on; /* DRX operation enable/ disable */ |
| 2455 | FDD_ue_drx_cycle_E drx_cycle_length; /* HS-SCCH reception pattern, i.e. how often UE has to monitor HSSCCH. */ |
| 2456 | FDD_ue_drx_cycle_inactivity_threshold_E drx_cycle_inactivity_threshold; /* Number of subframes after downlink activity where UE has to continuously monitor HS-SCCH. Units of subframes */ |
| 2457 | FDD_ue_grantMonitoring_inactivity_threshold_E grantMonitoring_inactivity_threshold; /* Number of subframes after uplink activity when UE has to continue to monitor E-AGCH/E-RGCH. Units of E-DCH TTIs. */ |
| 2458 | kal_bool ue_drx_grantMonitoring; /* whether the UE is required to monitor E-AGCH/E-RGCH when they overlap with the start of an HS-SCCH reception as defined in the HS-SCCH reception pattern */ |
| 2459 | } FDD_hs_drx_param_T; |
| 2460 | |
| 2461 | typedef struct _FDD_hs_dtx_drx_info_T |
| 2462 | { |
| 2463 | FDD_dtx_drx_status_E status; |
| 2464 | FDD_hs_dtx_drx_timing_info_T timing; |
| 2465 | FDD_hs_dtx_param_T hs_dtx_param; |
| 2466 | FDD_hs_drx_param_T hs_drx_param; |
| 2467 | } FDD_hs_dtx_drx_info_T; |
| 2468 | |
| 2469 | typedef struct _FDD_hs_cell_pch_state_info_T |
| 2470 | { |
| 2471 | #ifdef UL1_PHASE3_TEST |
| 2472 | kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */ |
| 2473 | kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */ |
| 2474 | #else |
| 2475 | // kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */ |
| 2476 | // kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */ |
| 2477 | #endif |
| 2478 | FDD_pich_info_T pich_info; |
| 2479 | kal_uint8 pcch_hspdsch_ovsf; /* [Range] Integer (0..15) HS-PDSCH channel associated with the PICH for HSSCCH less PAGING TYPE 1 message transmission. */ |
| 2480 | kal_uint8 num_of_pcch_trans; /* [Range] Integer (1..5) number of subframes used to transmit the PAGING TYPE 1. */ |
| 2481 | kal_int8 pcch_tb_size_index[2]; /* [Range] Integer (1..32). -1 if this is invalid. Index of value range 1 to 32 of the MAC-ehs transport block size as described in appendix A of 25.321. */ |
| 2482 | FDD_hs_fach_pch_rl_info_T fach_pch_rl_info; |
| 2483 | } FDD_hs_cell_pch_state_info_T; |
| 2484 | |
| 2485 | typedef struct _FDD_hs_cell_fach_state_info_T |
| 2486 | { |
| 2487 | #ifdef UL1_PHASE3_TEST |
| 2488 | kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */ |
| 2489 | kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */ |
| 2490 | #else |
| 2491 | // kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */ |
| 2492 | // kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */ |
| 2493 | #endif |
| 2494 | FDD_hs_fach_pch_rl_info_T fach_pch_rl_info; |
| 2495 | } FDD_hs_cell_fach_state_info_T; |
| 2496 | |
| 2497 | typedef struct _FDD_hs_cell_dch_state_info_T |
| 2498 | { |
| 2499 | kal_bool dl_64QAM_on; /* 64QAM enable/disable */ |
| 2500 | FDD_hs_tbsize_table_E hsdsch_tbsize_table; /* If this IE is present, octet aligned table [25.321] is used, else bit aligned table [25.321] is used. |
| 2501 | In DCH state, this field is assigned by SLCE. Otherthan DCH state, UL1 should use octet-aligned table by itself.*/ |
| 2502 | } FDD_hs_cell_dch_state_info_T; |
| 2503 | |
| 2504 | typedef union _FDD_hspdsch_state_info_T |
| 2505 | { |
| 2506 | FDD_hs_cell_pch_state_info_T cell_pch; /* The parameters in CELL_PCH or URA state. */ |
| 2507 | FDD_hs_cell_fach_state_info_T cell_fach; /* The parameters in CELL_FACH or IDLE_FAC state. */ |
| 2508 | FDD_hs_cell_dch_state_info_T cell_dch; /* The parameters in CELL_DCH state. */ |
| 2509 | } FDD_hspdsch_state_info_T; |
| 2510 | |
| 2511 | #ifdef __UMTS_R8__ |
| 2512 | typedef struct _FDD_hs_cell_fach_drx_T |
| 2513 | { |
| 2514 | kal_bool interrupt_by_hsdsch; /* TRUE : the DRX operation can be interrupted by HS-DSCH data. */ |
| 2515 | /* FALSE: the DRX operation cannot be interrupted by HS-DSCH data. */ |
| 2516 | FDD_hs_cell_fach_drx_status_E hs_cell_fach_drx_status; /* enhanced CELL_FACH DRX status */ |
| 2517 | FDD_hs_cell_fach_drx_level_E drx_level; /* 1-level DRX or 2-level DRX cycle is used */ |
| 2518 | /* When NW configures R8 DRX pattern, SLCE will configure 2nd-level DRX parameters only |
| 2519 | and set 1st-level DRX parameters as invalid */ |
| 2520 | FDD_hs_cell_fach_drx_status_timer_length_E second_timer_length; /* Inactivity timer to start 1-level HS CELL_FACH DRX. Set from T321(SIB5) or T329 (SIB22) */ |
| 2521 | FDD_hs_cell_fach_drx_cycle_E second_drx_cycle_length; /* HS CELL_FACH DRX cycle length during the 2nd DRX operation */ |
| 2522 | FDD_hs_cell_fach_drx_rx_burst_E second_drx_burst_length; /* the period within the 2nd HS DRX cycle that the UE continuously receive */ |
| 2523 | FDD_hs_cell_fach_drx_status_timer_length_E first_timer_length; /* Inactivity timer to start 2-level HS CELL_FACH DRX. Set from T321(SIB5) or T328 (SIB22) */ |
| 2524 | FDD_hs_cell_fach_drx_cycle_E first_drx_cycle_length; /* HS CELL_FACH DRX cycle length during the 1st DRX operation */ |
| 2525 | FDD_hs_cell_fach_drx_rx_burst_E first_drx_burst_length; /* The period within the 1st HS DRX cycle that the UE continuously receive */ |
| 2526 | } FDD_hs_cell_fach_drx_T; |
| 2527 | |
| 2528 | typedef struct _FDD_secondary_hspdsch_info_T |
| 2529 | { |
| 2530 | kal_bool dl_64QAM_on; /* If 64QAM supported in secondary HS-DSCH */ |
| 2531 | kal_uint16 h_rnti; /* h_rnti to decode secondary HS-DSCH receiving */ |
| 2532 | FDD_hs_tbsize_table_E hsdsch_tbsize_table; /* If dl_64QAM_on = KAL_TRUE, hsdsch_tbsize_table should be FDD_OCTET_ALIGNED. */ |
| 2533 | } FDD_secondary_hspdsch_info_T; |
| 2534 | |
| 2535 | #define FDD_DC_HSDPA_ALL_CONFIG_BIT 0x7F |
| 2536 | typedef struct _FDD_dc_hsdpa_info_T |
| 2537 | { |
| 2538 | kal_uint8 modify_field; /* Bit 0: FDD_hs_scch_info_T |
| 2539 | * Bit 1: FDD_secondary_hspdsch_info_T |
| 2540 | * Bit 2: psc |
| 2541 | * Bit 3: meas_po |
| 2542 | * Bit 4: dl_freq |
| 2543 | * Bit 5: sttd |
| 2544 | * Bit 6: dpch_offset */ |
| 2545 | FDD_dc_hsdpa_status_E dc_hsdpa_status; /* variable to control UL1 DC HS-DSCH receiving */ |
| 2546 | FDD_hs_scch_info_T hs_scch_info; /* Secondary HS-SCCH info. */ |
| 2547 | FDD_secondary_hspdsch_info_T sec_h_info; /* Secondary HS-PDSCH info. */ |
| 2548 | kal_uint16 psc; /* Primary scrambling code used in secondary H cell*/ |
| 2549 | kal_int8 meas_po; /* Measurement power offset, step = half dB. Range = -12~26 (-6dB~13dB)*/ |
| 2550 | kal_uint16 dl_freq; /* DL UARFCN, 0~16383*/ |
| 2551 | kal_bool sttd; /* TRUE: STTD is used for P-CPICH of the secondary cell |
| 2552 | * FALSE: STTD is not used for P-CPICH of the secondary cell.*/ |
| 2553 | #ifdef __UMTS_R9__ |
| 2554 | kal_uint8 dpch_offset; /* [R9] f-dpch offset of 2nd freq when DC-HSUPA is configured, |
| 2555 | otherwise invalid value 0xFFFF is configured. (0~38144 chips by step of 256 ) |
| 2556 | [R10] For additional dc-hsdpa (dc_hsdpa_info[1]/dc_hsdpa_info[2]), this is always invalid value 0xFFFF. */ |
| 2557 | #endif /*__UMTS_R9__*/ |
| 2558 | } FDD_dc_hsdpa_info_T; |
| 2559 | |
| 2560 | typedef struct _FDD_dl_pc_info_T /* DL power control information used for common E-DCH */ |
| 2561 | { |
| 2562 | kal_uint8 tpc_target; /* range: 1~10, the actual TPC command error rate target is tpc_target/100 */ |
| 2563 | kal_uint8 dpc_mode; /*DL Power control mode. 0 or 1 or 2. In current spec, SLCE will always fix this field by 0 for common E-DCH. */ |
| 2564 | kal_uint8 fdpch_slot_format; /* range: 0~9. In current spec, SLCE will always fix this field by 0 for common E-DCH. */ |
| 2565 | } FDD_dl_pc_info_T; |
| 2566 | |
| 2567 | typedef struct _FDD_ul_dpch_code_info_T /* UL DPCH information used for common E-DCH transmission */ |
| 2568 | { |
| 2569 | FDD_sc_type_E sc_type; /* short type or long type scrambling code */ |
| 2570 | kal_uint32 sc_code; /* 0 ~ 16777215 */ |
| 2571 | } FDD_ul_dpch_code_info_T; |
| 2572 | |
| 2573 | typedef struct _FDD_edch_resource_list_T |
| 2574 | { |
| 2575 | kal_uint8 s_offset; /* symbol offset. range: 0~9 */ |
| 2576 | kal_uint8 fdpch_ovsf; /* 0 ~ 255 */ |
| 2577 | kal_uint8 ehirgch_ovsf; /* ovsf code for receiving E-HICH and E-RGCH in common E-DCH transmission */ |
| 2578 | kal_uint8 hich_signature_seq; /* E-HICH signature sequence in common E-DCH transmission [Range: 0~39] */ |
| 2579 | kal_uint8 rgch_signature_seq; /* E-RGCH signature sequence in common E-DCH transmission [Range: 0~39, 0xff means invalid. No need to decode E-RGCH] */ |
| 2580 | FDD_ul_dpch_code_info_T ul_dpch_code_info; /* UL DPCH information used for common E-DCH transmission */ |
| 2581 | } FDD_edch_resource_list_T; |
| 2582 | |
| 2583 | typedef struct _FDD_common_edch_info_T |
| 2584 | { |
| 2585 | kal_uint8 add_tran_back_off; /* 0 ~ 15, unit is TTI */ |
| 2586 | kal_uint8 edch_resource_num; /* 1~32 */ |
| 2587 | FDD_edch_resource_list_T edch_resource_list[32]; /* common RLs for E-DCH transmission */ |
| 2588 | FDD_ul_pc_info_T ul_pc; /* ul power control info. */ |
| 2589 | } FDD_common_edch_info_T; |
| 2590 | |
| 2591 | typedef struct _FDD_edch_specific_info_T |
| 2592 | { |
| 2593 | kal_bool e_ai_ind; /* TRUE: E-AI should be used. FALSE: E-AI should not be used. */ |
| 2594 | kal_int8 po_p_e; /* -5 ~ 10 dB, power offset between last TX preamble and initial DPCCH */ |
| 2595 | } FDD_edch_specific_info_T; |
| 2596 | |
| 2597 | |
| 2598 | typedef struct |
| 2599 | { |
| 2600 | kal_bool d_hrnti_valid; |
| 2601 | kal_uint16 d_hrnti;/*dH-RNTI*/ |
| 2602 | |
| 2603 | kal_bool c_hrnti_valid; |
| 2604 | kal_uint16 c_hrnti;/*cH-RNTI*/ |
| 2605 | |
| 2606 | kal_bool b_hrnti_valid; |
| 2607 | kal_uint16 b_hrnti;/*cH-RNTI*/ |
| 2608 | |
| 2609 | } FDD_hs_hrnti_info_T; |
| 2610 | |
| 2611 | |
| 2612 | #ifdef __UMTS_R9__ |
| 2613 | |
| 2614 | typedef enum |
| 2615 | { |
| 2616 | FDD_DC_HSUPA_OFF, /* disable DC-HSUPA operation and all DC-HSUPA parameters are invalid */ |
| 2617 | FDD_DC_HSUPA_ON, /* use new DC-HSUPA configuration and reset order. |
| 2618 | The default status is deactivated until receiving HS-SCCH order to activate, |
| 2619 | and don't need sync A procedure on 2nd freq. */ |
| 2620 | FDD_DC_HSUPA_ALL_RL_TIMING_MODIFY, /* If the DC-HSUPA choice timing is "continue" when receiving ALL_RL_TIMING_MODIFY, |
| 2621 | SLCE uses the old DC-HSUPA configuration to UL1, and UL1 applies the configuration without reset order. |
| 2622 | Do not apply sync A procedue no matter the DC-HSUPA status after E-DCH setup. */ |
| 2623 | FDD_DC_HSUPA_ON_WITHOUT_RESET_ORDER, /* Use new DC-HSUPA configuration and do not reset order. |
| 2624 | Sync A will need if DC-HSUPA is activate after E-DCH setup, but not for E-DCH modify. */ |
| 2625 | FDD_DC_HSUPA_INVALID /* SLCE internal use, won't config this enum to UL1 */ |
| 2626 | |
| 2627 | } FDD_dc_hsupa_status_E; |
| 2628 | |
| 2629 | typedef enum |
| 2630 | { |
| 2631 | FDD_DC_HSUPA_MODIFY_NORMAL_CONFIG, /* Normal configuration */ |
| 2632 | FDD_DC_HSUPA_MODIFY_ASU, /* ASU configuration. */ |
| 2633 | FDD_DC_HSUPA_MODIFY_ALL_ACTIVE_SET, /* All active set cell change (RBR) */ |
| 2634 | FDD_DC_HSUPA_MODIFY_NUM |
| 2635 | } FDD_dc_hsupa_modify_type_E; |
| 2636 | |
| 2637 | |
| 2638 | typedef struct |
| 2639 | { |
| 2640 | kal_bool pri_e_rnti_valid; /* Indicate if pri_e_rnti field is valid */ |
| 2641 | kal_uint16 pri_e_rnti; /* Primary E-RNTI assigned to UE */ |
| 2642 | kal_bool sec_e_rnti_valid; /* Indicate if sec_e_rnti field is valid */ |
| 2643 | kal_uint16 sec_e_rnti; /* Secondary E-RNTI assigned to UE */ |
| 2644 | } FDD_sec_e_rnti_info_T; |
| 2645 | |
| 2646 | typedef struct |
| 2647 | { |
| 2648 | kal_uint16 ul_freq; /* UL UARFCN */ |
| 2649 | kal_uint16 dl_freq; /* DL UARFCN */ |
| 2650 | FDD_sc_type_E sc_type; /* Type of scrambling code */ |
| 2651 | kal_uint32 sc_code; /* Scrambling code #. 0 ~ 16777215 */ |
| 2652 | FDD_beta_ed_reduced_min_E beta_ed_reduced_min; /* Minimum reduced E-DPDCH gain factor. |
| 2653 | If not configured in RRC message, SLCE should set the default value "FDD_beta_ed_8_15". */ |
| 2654 | kal_uint8 dpcch_po_SecondaryULFrequency; /* power offset. Integer (0..7 by step of 1) */ |
| 2655 | kal_uint8 pc_pream; /* Power control Preamble. 0 ~ 7 frames */ |
| 2656 | } FDD_sec_edch_info_common_T; |
| 2657 | |
| 2658 | #define FDD_DC_HSUPA_ALL_CONFIG_BIT 0x7F |
| 2659 | |
| 2660 | typedef struct |
| 2661 | { |
| 2662 | /*** mandatory configuration ***/ |
| 2663 | FDD_dc_hsupa_status_E dc_hsupa_status; /* variable to control UL1 DC-HSUPA receiving */ |
| 2664 | FDD_dc_hsupa_modify_type_E modify_type; /* DC-HSUPA modify type */ |
| 2665 | kal_int16 edch_serv_rscp; /* RSCP of secondary edch serving cell. Range: -464 ~ -100 dBm. |
| 2666 | SLCE always sets RSCP value from DB_cell without comparison.*/ |
| 2667 | /*** optional configuration ***/ |
| 2668 | kal_uint8 config_field; /* Indicates the configured field: |
| 2669 | Bit 0: sec_e_rnti_info |
| 2670 | Bit 1: sec_edch_info_common |
| 2671 | Bit 2: dl_dpch_rl_delete/dl_dpch_rl_add |
| 2672 | Bit 3: edch_serv_psc |
| 2673 | Bit 4: eagch_info |
| 2674 | Bit 5: ehich_info |
| 2675 | Bit 6: ergch_info |
| 2676 | All field must be configured when switching DC-HSUPA OFF to ON. */ |
| 2677 | /* Bit 0: sec_e_rnti_info */ |
| 2678 | FDD_sec_e_rnti_info_T sec_e_rnti_info; /* [TS25.331]10.3.6.116 Secondary serving E-DCH cell info */ |
| 2679 | /* Bit 1: sec_edch_info_common */ |
| 2680 | FDD_sec_edch_info_common_T sec_edch_info_common; /* [TS25.331]10.3.6.117 Secondary E-DCH info common */ |
| 2681 | /* Bit 2: dl_dpch_rl_delete/dl_dpch_rl_add */ |
| 2682 | kal_uint8 dl_dpch_rl_delete_num; /* Number of RL to be removed: 0~FDD_MAX_EDCH_RL */ |
| 2683 | kal_uint16 dl_dpch_rl_delete[FDD_MAX_EDCH_RL]; /* RL to be removed (PSC) */ |
| 2684 | kal_uint8 dl_dpch_rl_add_num; /* Number of DL DPCH RL to be added: 0~FDD_MAX_EDCH_RL */ |
| 2685 | FDD_dl_dpch_rl_T dl_dpch_rl_add[FDD_MAX_EDCH_RL]; /* DL DPCH info. for each RL. |
| 2686 | If modify_type != ASU, dl_dpch_rl_add is the full set of DL DPCH RL info. */ |
| 2687 | /* Bit 3: edch_serv_psc */ |
| 2688 | kal_uint16 edch_serv_psc; /* serving E-DCH cell */ |
| 2689 | /* Bit 4: eagch_info */ |
| 2690 | FDD_eagch_info_T eagch_info; /* E-AGCH info */ |
| 2691 | /* Bit 5: ehich_info */ |
| 2692 | kal_uint8 ehich_info_num; /* Number of E-HICH info: 1~FDD_MAX_EDCH_RL */ |
| 2693 | FDD_ehich_info_T ehich_info[FDD_MAX_EDCH_RL]; /* E-HICH info */ |
| 2694 | /* Bit 6: ergch_info */ |
| 2695 | kal_uint8 ergch_info_num; /* Number of E-RGCH info: 0~FDD_MAX_EDCH_RL */ |
| 2696 | FDD_ergch_info_T ergch_info[FDD_MAX_EDCH_RL]; /* E-RGCH info */ |
| 2697 | |
| 2698 | } FDD_dc_hsupa_info_T; |
| 2699 | |
| 2700 | #endif /* __UMTS_R9__ */ |
| 2701 | #endif /* __UMTS_R8__ */ |
| 2702 | #endif /* __UMTS_R7__ */ |
| 2703 | |
| 2704 | #if defined (__L1_STANDALONE__ ) |
| 2705 | /*HsDsch check Interface*/ |
| 2706 | typedef struct |
| 2707 | { |
| 2708 | kal_bool is_hsscch_result_valid ; // need each tti hsscch result |
| 2709 | kal_bool is_valid_data ; // need each tti hspdsch result |
| 2710 | kal_uint8 cfn_drx;//need each cfn number |
| 2711 | kal_uint8 s_drx;// need each subframe number |
| 2712 | kal_bool is_scheduled;//need each tti scheduling information |
| 2713 | kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled. |
| 2714 | kal_bool is_in_gap; // is current tti is gap |
| 2715 | kal_bool is_postpone;// is postpone condition |
| 2716 | kal_uint8 ndi;// is new data or retransmission (1: new data, 0: retransmssion) |
| 2717 | |
| 2718 | } FDD_IF_HSDSCH_PARAM_T; |
| 2719 | typedef struct |
| 2720 | { |
| 2721 | kal_bool is_valid_data;// need each tti result |
| 2722 | kal_uint8 ag_value;// need each tti result |
| 2723 | kal_uint8 ag_scope;// need each tti result |
| 2724 | kal_uint8 cfn_drx;//need each cfn number |
| 2725 | kal_uint8 s_drx;// need each subframe number |
| 2726 | kal_bool is_tti_2ms;// need each tti result |
| 2727 | kal_bool is_scheduled;//need each tti scheduling information |
| 2728 | kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled. |
| 2729 | kal_bool is_in_gap;// is current tti is gap ,current test is without gap |
| 2730 | FDD_edch_scell_E ecell_type; |
| 2731 | } FDD_IF_EAGCH_PARAM_T; |
| 2732 | typedef struct |
| 2733 | { |
| 2734 | kal_uint8 e_rgch_result_serving; // need each tti result |
| 2735 | kal_uint8 cfn_drx;//need each cfn number |
| 2736 | kal_uint8 s_drx;// need each subframe number |
| 2737 | kal_bool is_tti_2ms;// need each tti result |
| 2738 | kal_bool is_scheduled;// need each tti result |
| 2739 | kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled. |
| 2740 | kal_bool is_in_gap;// is current tti is gap, current test is without gap |
| 2741 | FDD_edch_scell_E ecell_type; |
| 2742 | } FDD_IF_ERGCH_PARAM_T; |
| 2743 | typedef struct |
| 2744 | { |
| 2745 | |
| 2746 | kal_uint8 cfn_drx;//need each cfn number |
| 2747 | kal_uint16 scheduled_bimap;//need each slot result |
| 2748 | kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled. |
| 2749 | FDD_edch_scell_E ecell_type; |
| 2750 | |
| 2751 | } FDD_IF_ULDPCCH_PARAM_T; |
| 2752 | #endif /*__L1_STANDALONE__*/ |
| 2753 | |
| 2754 | typedef enum |
| 2755 | { |
| 2756 | RAS_INVALID, |
| 2757 | RAS_PATH_MAIN, |
| 2758 | RAS_PATH_BOTH |
| 2759 | } RAS_PATH_T; |
| 2760 | |
| 2761 | typedef enum |
| 2762 | { |
| 2763 | CS_PS_INVALID, |
| 2764 | CS_ONLY, |
| 2765 | CS_PS_BOTH, |
| 2766 | PS_ONLY |
| 2767 | } FDD_IS_CS_PS; |
| 2768 | |
| 2769 | typedef struct |
| 2770 | { |
| 2771 | kal_uint8 numElements; |
| 2772 | kal_uint8 elements[NUM_MCC_MNC]; |
| 2773 | } FDD_MCC_MNC_T; |
| 2774 | |
| 2775 | typedef struct |
| 2776 | { |
| 2777 | FDD_MCC_MNC_T mcc; |
| 2778 | FDD_MCC_MNC_T mnc; |
| 2779 | } FDD_PLMN_IDENTITY_T; |
| 2780 | |
| 2781 | typedef struct |
| 2782 | { |
| 2783 | kal_uint8 cell_plmn_num; |
| 2784 | FDD_PLMN_IDENTITY_T cell_plmn_info[NUM_PLMN_INFO]; |
| 2785 | kal_uint16 lac; |
| 2786 | kal_uint16 rac; |
| 2787 | kal_int16 cellidx; |
| 2788 | } FDD_PLMN_LAC_PARAM_T; |
| 2789 | typedef struct |
| 2790 | { |
| 2791 | kal_uint8 radio_bearer_ID; |
| 2792 | kal_uint32 rx_window_size; |
| 2793 | } FDD_RLC_WINDOW_SIZE_INFO_T; |
| 2794 | |
| 2795 | #endif |