blob: 440893a47085e7234ee2d9a6da654c0d3ce38204 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +08001/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * ul1_struct.h
41 *
42 * Project:
43 * --------
44 * WCDMA_Software
45 *
46 * Description:
47 * ------------
48 * Layer 1 and Protocol Stack message and callback function definition
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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1044 *------------------------------------------------------------------------------
1045 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
1046 *============================================================================
1047 ****************************************************************************/
1048
1049#ifndef _UL1_STRUCT_H
1050#define _UL1_STRUCT_H
1051
1052/* auto add by kw_check begin */
1053#include "ul1_def.h"
1054#include "kal_general_types.h"
1055#include "ul1_cnst.h"
1056/*#include "ul1tst_msg.h"*/
1057#include "kal_public_defs.h" //MSBB change #include "stack_msgs.h"
1058#include "kal_public_api.h" //MSBB change #include "app_ltlcom.h"
1059/* auto add by kw_check end */
1060#include "em_public_struct.h"
1061
1062#include "global_type.h" /* [UBin] For inclusion of erac_rat_enum */
1063#include "mll1_umts_fdd.h" /* umts_fdd_dch_gap_struct */
1064#if !defined(__XL1SIM__)
1065#include "rsvak_public_enum.h" /* for freq_scan_type_enum */
1066#endif
1067
1068#if defined(__ATERFTX_ERROR_HANDLE_ENHANCE__)
1069#include "ps_public_enum.h" /*for error cause in AT+ERFTX EM changes*/
1070#endif //__ATERFTX_ERROR_HANDLE_ENHANCE__
1071
1072/*****************************************************************************
1073Request from 3G PS
1074*****************************************************************************/
1075typedef struct _fdd_cphy_bch_setup_req_struct
1076{
1077 LOCAL_PARA_HDR
1078
1079 kal_int16 act_time; /* activation time. should -1 (Immediate) */
1080 kal_int16 rx_sfn; /* SFN for start BCH. -1 ~ 4095. -1 means immedaite */
1081 kal_int32 tm; /* LST of the cell boundary. 0 ~ 38400*8-1 */
1082 kal_int16 off; /* Frame # offset to LST. -1 ~ 4095. -1 means unknown */
1083 kal_bool sfn_only; /* Only read SFN */
1084 kal_uint16 dl_freq; /* DL UARFCN */
1085 kal_uint16 psc; /* Primary scrambling code */
1086 kal_bool sttd; /* STTD setting */
1087 kal_int8 sib7_index; /* Indicate which SIB Info in sib_list is SIB7 */
1088 /* -1 means there is not SIB7 in the list */
1089 kal_uint16 sib7_rep_cycle; /* 2 ~ 256. The meaning of sib7_rep_cycle becomes "SIB7 expiration timer / SIP_REP" */
1090 /* The true value is 2^sib7_rep_cycle. */
1091 kal_bool servingcell; /* MTK not used */
1092 FDD_bch_priority_E bch_priority; /* Priority of this BCH */
1093 kal_uint8 priority_level;
1094 kal_uint8 sib_num; /* # of SIB to be read, 0 means all SIBs reception.*/
1095 FDD_sib_info_T sib_list[FDD_MAX_SIB_PATTERN]; /* SIB information */
1096
1097#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
1098 kal_uint16 priority_index; /*Priority_index for same priority channel in 3G Gemini project*/
1099#endif
1100
1101 kal_bool is_auto_gap_support; /* this bch req is for rptCGI */
1102
1103} fdd_cphy_bch_setup_req_struct;
1104
1105typedef struct _fdd_cphy_bch_modify_req_struct
1106{
1107 LOCAL_PARA_HDR
1108
1109 kal_int16 act_time; /* activation time. -1 ~ 4095. -1 means immediate */
1110 kal_int16 rx_sfn; /* SFN for start BCH. -1 ~ 4095. -1 means immedaite */
1111 kal_uint8 modify_flag; /* 0x01 : bch_priority is changed */
1112 /* 0x02 : SIB information is changed */
1113 /* 0x03 : Both bch_priority and SIB information are changed */
1114 /*0x04: priority idx*/
1115 kal_int8 sib7_index; /* Indicate which SIB Info in sib_list is SIB7 */
1116 /* -1 means there is not SIB7 in the list */
1117 kal_uint16 sib7_rep_cycle; /* 2 ~ 256. The meaning of sib7_rep_cycle becomes "SIB7 expiration timer / SIP_REP" */
1118 /* The true value is 2^sib7_rep_cycle. */
1119
1120 FDD_bch_priority_E bch_priority; /* Priority of this BCH */
1121 kal_uint8 priority_level;
1122 kal_uint8 sib_num; /* # of SIB to be read */
1123 FDD_sib_info_T sib_list[FDD_MAX_SIB_PATTERN]; /* SIB Information */
1124
1125#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
1126 kal_uint16 priority_index; /*Priority_index for same priority channel in 3G Gemini project*/
1127#endif
1128
1129} fdd_cphy_bch_modify_req_struct;
1130
1131typedef struct _fdd_cphy_bch_release_req_struct
1132{
1133 LOCAL_PARA_HDR
1134} fdd_cphy_bch_release_req_struct;
1135
1136typedef struct _fdd_cphy_pch_setup_req_struct
1137{
1138 LOCAL_PARA_HDR
1139
1140 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1141 kal_uint16 dl_freq; /* DL UARFCN */
1142 kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
1143 kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
1144 kal_bool is_CSFB; /* to specify this PCH setup is for CSFB redirection */
1145 FDD_FACH_PCH_Info_T fach_pch_info; /* Channel information */
1146} fdd_cphy_pch_setup_req_struct;
1147
1148typedef struct _fdd_cphy_pch_modify_req_struct
1149{
1150 LOCAL_PARA_HDR
1151
1152 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1153 FDD_pich_reconfig_type_E reconfig_type;
1154 FDD_pich_drx_T pich_drx; /* Modified DRX information */
1155#ifdef __SMART_PAGING_3G_FDD__
1156 FDD_pich_smartpaging_T smartpaging_info;
1157#endif
1158#ifdef __UMTS_R7__
1159 FDD_pich_drx_T pich_drx_cycle2; /* DRX parameters 2 for PICH. */
1160 kal_uint16 drx_cycle2_time; /* if it's not 0. UL1 shall use pich_drx_2 for PICH receptin, else shall directly use pich_drx for PICH reception. 0~5120 ms */
1161#endif /* __UMTS_R7__ */
1162} fdd_cphy_pch_modify_req_struct;
1163
1164typedef struct _fdd_cphy_pch_release_req_struct
1165{
1166 LOCAL_PARA_HDR
1167
1168 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1169} fdd_cphy_pch_release_req_struct;
1170
1171typedef struct _fdd_cphy_fach_setup_req_struct
1172{
1173 LOCAL_PARA_HDR
1174
1175 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1176 kal_uint16 dl_freq; /* DL UARFCN */
1177 kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
1178 kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
1179 FDD_FACH_PCH_Info_T fach_pch_info; /* Channel information */
1180} fdd_cphy_fach_setup_req_struct;
1181
1182typedef struct _fdd_cphy_fach_modify_req_struct
1183{
1184 LOCAL_PARA_HDR
1185
1186 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1187 FDD_ctch_drx_T ctch_drx; /* Modified CTCH DRX information */
1188} fdd_cphy_fach_modify_req_struct;
1189
1190typedef struct _fdd_cphy_fach_release_req_struct
1191{
1192 LOCAL_PARA_HDR
1193
1194 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1195} fdd_cphy_fach_release_req_struct;
1196
1197typedef struct _fdd_cphy_rach_setup_req_struct
1198{
1199 LOCAL_PARA_HDR
1200
1201 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1202 kal_uint16 ul_freq; /* UL UARFCN */
1203 FDD_aich_info_T aich_info; /* AICH info and ASC setting for PRACH partition */
1204 FDD_prach_info_T prach_info; /* PRACH information */
1205 FDD_prach_power_T prach_power; /* PRACH power information */
1206 kal_uint8 tfc_num; /* # of TFC. 1 ~ 32 (Only 1 TrCH for 1 PRACH) */
1207 FDD_ul_rach_tfc_T tfcs[FDD_MAXTF]; /* TFCS (TFS) */
1208 FDD_ul_rach_trch_T trch_list[1]; /* Only 1 TrCH */
1209#ifdef __UMTS_R8__
1210 FDD_cell_fach_ul_trch_type_E trch_type; /* the transport channel type of random access attemp */
1211 FDD_edch_specific_info_T edch_specific_info; /* PRACH and AICH specific information used for common E-DCH transmission */
1212#endif /* __UMTS_R8__ */
1213} fdd_cphy_rach_setup_req_struct;
1214
1215typedef struct _fdd_cphy_rach_release_req_struct
1216{
1217 LOCAL_PARA_HDR
1218
1219 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1220} fdd_cphy_rach_release_req_struct;
1221
1222typedef struct _fdd_cphy_dch_setup_req_struct
1223{
1224 LOCAL_PARA_HDR
1225
1226 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1227 FDD_dch_setup_msg_type_E setup_type; /* SETUP, TRHHO or TRHHO revert */
1228 kal_int8 tm_rl_index; /* indicate the index of specific RL in array dl_dpch_rl[] which has the valid Tm value. */
1229 kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
1230 kal_int16 rscp; /* Serving cell RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/
1231 kal_uint8 tid; /* Transaction id */
1232
1233 kal_uint8 dl_crc_ind; /* For those TrCHs whose CRC data should be sent to MAC,
1234 their corresponding bit will be set to 1.
1235 The MSB represents the lowest numbered TrCH ID.
1236 */
1237
1238 kal_uint16 ul_freq; /* UL UARFCN */
1239 kal_uint16 ul_tfc_num; /* # of TFC for UL DPCH */
1240 FDD_ul_dpch_tfc_T ul_tfcs[FDD_MAX_UL_TFC]; /* UL TFCS */
1241 kal_uint8 ul_trch_num; /* # of UL TrCH */
1242 FDD_ul_dch_trch_T ul_trch_list[FDD_MAX_UL_TRCH]; /* UL DPCH TrCH Info */
1243 FDD_ul_dpch_info_T ul_dpch_info;
1244
1245 kal_uint16 dl_freq; /* DL UARFCN */
1246 kal_uint16 dl_tfc_num; /* # of TFC for DL DPCH */
1247 FDD_dl_tfc_T dl_tfcs[FDD_MAX_DL_TFC]; /* DL TFCS */
1248 kal_uint8 dl_trch_num; /* # of DL TrCH */
1249 FDD_dl_dch_trch_T dl_trch_list[FDD_MAX_DL_TRCH]; /* DL DPCH TrCH Info */
1250 kal_int8 max_tx_power; /* Max allowed TX power. -50 ~ 33 dBm */
1251 kal_int8 umts_power_class; /* UE capability*/
1252
1253 kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
1254 FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
1255
1256 FDD_dl_dpch_rla_T dl_dpch_rla; /* DL Info & DL DPCH Info common for all RLs */
1257 kal_uint8 rl_num; /* # of RL. 1 ~ 8 */
1258 FDD_dl_dpch_rl_T dl_dpch_rl[FDD_MAX_RL]; /* DL Info & DL DPCH Info. for each RL */
1259
1260 FDD_dl_establish_T dl_sync_info; /* DL DPCH establishment criterion */
1261
1262 kal_bool non_sync_ind; /* [R6] FALSE: sync procedure shall be performed. TRUE: Sync procedure shall not be performed
1263 for R5 and previous version, this value should be FALSE.
1264 This field can be set to true only when setup_type is FDD_DCH_TMHHO */
1265 kal_bool post_verification; /* [R6] TRUE: Post verification period shall be used . FALSE: Post verification period shall not be used.
1266 for R5 and previous version, this value should be FALSE */
1267 FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
1268 /* This value should be consistent with the dpch_type field in dl_dpch_rl */
1269
1270 kal_uint8 ul_mac_event; /* Indicate if UMAC need setup/modify/release event */
1271#ifdef __UMTS_R8__
1272 kal_bool edch_info_included; /* True means that IE "E-DCH info" is include in the reconfiguration message in the transition
1273 * from FACH state to DCH state. UL1 uses this and following flags and other condition to determine
1274 * if it is needed to perform Sync A procedure. Please see UL1 SAP in details. */
1275 kal_bool fach_to_dch_cell_change; /* the PSC of RLs included in active set does not include the PSC of the current cell in CELL_FACH. */
1276#endif /* __UMTS_R8__ */
1277 FDD_IS_CS_PS is_cs_ps_call; /* for TAS feature. To check if DCH channel is for CS call */
1278 kal_bool is_cs_call_only; /* for lo_rx. To check if DCH channel is only CS call */
1279 kal_bool is_CSFB; /* to specify this DCH setup is for CSFB redirection */
1280 kal_bool is_ecall_or_callback; /* To use eCall Information so that UL1 can disable features like LoRX, ARX */
1281 kal_bool is_vc_resume; /* To decide DCH setup type after Virtual connected resume */
1282} fdd_cphy_dch_setup_req_struct;
1283
1284typedef struct _fdd_cphy_dch_modify_req_struct
1285{
1286 LOCAL_PARA_HDR
1287
1288 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1289 FDD_dch_modify_msg_type_E modify_type; /* MODIFY, ASU, or Loop back mode 2 */
1290
1291 kal_uint8 tid; /* Transaction id */
1292
1293 kal_bool ul_mod_ind; /* Indicate whether UL modify indication should be sent to MAC */
1294 kal_bool dl_mod_ind; /* Indicate whether DL modify indication should be sent to MAC */
1295
1296 kal_uint8 dl_crc_ind; /* For those TrCHs whose CRC data should be sent to MAC,
1297 their corresponding bit will be set to 1.
1298 The MSB represents the lowest numbered TrCH ID.
1299 */
1300
1301 kal_uint16 modify_field; /* Bit field to represent for the parameters that should be modified
1302 Bit 0 : DL TrCH parameter
1303 Bit 1 : DL TFCS parameter
1304 Bit 2 : UL TrCH parameter
1305 Bit 3 : UL TFCS parameter
1306 Bit 4 : DL common RL parameter
1307 Bit 5 : DL each RL parameter
1308 Bit 6 : UL RL parameter
1309 Bit 7 : Physical parameters such as UL/DL freq and max TX power
1310 Bit 8 : DL sync info which means timer and constant updating
1311 */
1312 /* Bit 3 */
1313 kal_uint16 ul_tfc_num; /* # of TFC for UL DPCH */
1314 FDD_ul_dpch_tfc_T ul_tfcs[FDD_MAX_UL_TFC]; /* UL TFCS */
1315 /* Bit 2 */
1316 kal_uint8 ul_trch_num; /* # of UL TrCH */
1317 FDD_ul_dch_trch_T ul_trch_list[FDD_MAX_UL_TRCH]; /* UL DPCH TrCH Info */
1318 /* Bit 1 */
1319 kal_uint16 dl_tfc_num; /* # of TFC for DL DPCH */
1320 FDD_dl_tfc_T dl_tfcs[FDD_MAX_DL_TFC]; /* DL TFCS */
1321 /* Bit 0 */
1322 kal_uint8 dl_trch_num; /* # of DL TrCH */
1323 FDD_dl_dch_trch_T dl_trch_list[FDD_MAX_DL_TRCH]; /* DL DPCH TrCH Info */
1324 /* Bit 4 */
1325 FDD_dl_dpch_rla_T dl_dpch_rla; /* DL Info & DL DPCH Info common for all RLs */
1326
1327 kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
1328 FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
1329
1330 /* Bit 6 */
1331 FDD_ul_dpch_info_T ul_dpch_info;
1332 /* Bit 7 */
1333 /*remove these fields according to frequency info handler discussion*/
1334// kal_uint16 ul_freq; /* UL UARFCN */
1335// kal_uint16 dl_freq; /* DL UARFCN */
1336 kal_int8 max_tx_power; /* Max allowed TX power. -50 ~ 33 dBm */
1337 kal_int8 umts_power_class; /* UE capability*/
1338 /* Bit 5 or ASU */ /* For Bit 5 modification, only rl_num_add and dl_dpch_rl_add are used */
1339 kal_uint8 rl_num_delete; /* # of RL to be removed. 1 ~ 8*/
1340 kal_uint16 dl_dpch_rl_delete[FDD_MAX_RL]; /* RL to be removed (PSC) */
1341 kal_uint8 rl_num_add; /* # of RL to be added. 1 ~ 8 */
1342 FDD_dl_dpch_rl_T dl_dpch_rl_add[FDD_MAX_RL]; /* DL Info & DL DPCH Info. for each RL */
1343 FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
1344 /* This value should be consistent with the dpch_type field in dl_dpch_rl */
1345
1346 kal_uint8 ul_mac_event; /* Indicate if UMAC need setup/modify/release event */
1347
1348 /* Bit 8 for dl sync info updating */
1349 FDD_dl_establish_T dl_sync_info; /* DL DPCH establishment criterion */
1350 FDD_IS_CS_PS is_cs_ps_call; /* for TAS feature. To check if DCH channel is for CS call */
1351 kal_bool is_cs_call_only; /* for lo_rx. To check if DCH channel is only CS call */
1352 kal_bool is_ecall_or_callback; /* To use eCall Information so that UL1 can disable features like LoRX, ARX */
1353} fdd_cphy_dch_modify_req_struct;
1354
1355typedef struct _fdd_cphy_dch_release_req_struct
1356{
1357 LOCAL_PARA_HDR
1358
1359 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1360
1361 kal_bool isStopLoopTestM2First; /* LCL needs to stop Loop Test explicitly before releasing DCH in abnormal case. */
1362
1363 kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
1364 FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
1365
1366 FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
1367 /* This value should be consistent with the dpch_type field in dl_dpch_rl */
1368
1369 kal_uint8 ul_mac_event; /* Indicate if UMAC need setup/modify/release event */
1370#ifdef __UMTS_R7__
1371 FDD_dpch_release_type_E release_type; /* [R7] for whether UL1 need to record the HSS-SCCH oreder */
1372#endif /* __UMTS_R7__ */
1373
1374} fdd_cphy_dch_release_req_struct;
1375
1376typedef struct _fdd_cphy_tgps_delete_req_struct
1377{
1378 LOCAL_PARA_HDR
1379
1380 kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
1381 FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
1382
1383} fdd_cphy_tgps_delete_req_struct;
1384
1385/* RRCE notifies UL1 if UL1 should resume sending cphy_tgps_overlap_ind*/
1386typedef struct _fdd_cphy_tgps_overlap_resume_reporting_req_struct
1387{
1388 LOCAL_PARA_HDR
1389
1390 kal_uint8 tgpsi; /* TGPSI of TGPS beging removed. 1 ~ 6 */
1391} fdd_cphy_tgps_overlap_resume_reporting_req_struct;
1392
1393
1394typedef struct _fdd_cphy_frequency_scan_req_struct
1395{
1396 LOCAL_PARA_HDR
1397 kal_uint8 max_num_cell; /* maximum # of cells reported in 1 freq scan
1398 If L1 found and report max_num_cell in 1 freq,
1399 it should halt the freq scan
1400 */
1401 kal_int16 timeout; /* The max time spent to do cell search on 1 freq. (ms)
1402 If L1 has spent so much time to do cell search on 1 freq,
1403 it will send an ind to RRC and halt the freq scan procedure.
1404 */
1405
1406 kal_uint8 num_freq_range; /* # of range list */
1407 kal_uint16 uarfcn_begin[FDD_MAX_FREQ_RANGE]; /* Begin of DL uARFCN for range cell search */
1408 kal_uint16 uarfcn_end[FDD_MAX_FREQ_RANGE]; /* End of DL uARFCN for range cell search */
1409
1410 kal_uint8 num_freq_list; /* # of freq for preferred freq list */
1411 kal_uint16 uarfcn_list[FDD_MAX_FREQ_LIST]; /* List of UARFCN */
1412
1413 kal_uint8 num_psc; /* # of preferred cells */
1414 FDD_preferred_cell_list_T preferred_cell_list[FDD_MAX_PREFERRED_PSC]; /* Preferred cell list */
1415
1416 kal_bool full_band_search; /* Perform full band scan; igonoring other parameters. */
1417 kal_bool freq_correct; /* If 3G L1 need to do frequency correction */
1418 kal_bool resume; /* TRUE: UL1 should resume previous freq scan, UL1 didn't care the other fields in this msg
1419 FALSE: UL1 should start a new freq scan according to this msg */
1420 /*Flag to indicate Quick Search Scan enabled or not*/
1421 kal_bool quick_search;
1422 /*Add for improving full band FS efficiency -- by excluding some UARFCN or some frequency range*/
1423 FDD_full_band_option_E full_band_option; /*To indicate if "[filtered frequency list]/[frequency range]" shall be refered for full band search"*/
1424 kal_uint8 working_UMTS_FDD_band[4]; /* Bitmask for frequency bands necessary to be scanned for this request */
1425 kal_uint8 prefer_freq_list_cnt; /* # of preferred freq list */
1426 kal_uint16 prefer_uarfcn_list[FDD_MAX_FREQ_LIST]; /* List of prefered freq */
1427 kal_bool is_plmn_list; /* the prefered freq list is PLMN list or PLMN search */
1428#ifdef __UMTS_R8__
1429 kal_bool is_csg_search; /* [Rel8][CSG search]: to notify that current fs is for csg */
1430#endif
1431
1432#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
1433#if !defined(__XL1SIM__)
1434 freq_scan_type_enum freq_scan_type;
1435#else
1436 kal_uint16 priority_index;
1437#endif
1438
1439 kal_uint8 priority_level; /* This field is only used for Gemini 2.0. to indicate the gap pattern used for this freq scan in Virtual mode.
1440 The higher the priority, the smaller the priority level number. The highest priority is 2, which means this field can't be smaller than 2. */
1441#endif /* __GEMINI__ && __UMTS_RAT__ */
1442
1443 kal_bool is_auto_gap_support; /* [MM] this freq scan req is for rptCGI */
1444 kal_bool is_CSFB_search; /* [MM] to notify L1 the frequency scan is specified for CSFB */
1445
1446} fdd_cphy_frequency_scan_req_struct;
1447
1448typedef struct _fdd_cphy_frequency_scan_continue_req_struct
1449{
1450 LOCAL_PARA_HDR
1451
1452 kal_bool continue_cell; /* True if MEME want L1 to do continue cell search on current frequency
1453 instead of jumping to next specified frequency. */
1454 kal_uint16 ecs_freq; /* exhaustive cell search frequency */
1455 kal_bool apply_l1_filter;
1456 kal_uint8 num_exclude_frequency_list;
1457 kal_uint16 exclude_frequency_list[FDD_MAX_FREQ_EXCLUDE];
1458} fdd_cphy_frequency_scan_continue_req_struct;
1459
1460typedef struct _fdd_cphy_frequency_scan_suspend_req_struct
1461{
1462 LOCAL_PARA_HDR
1463
1464 kal_bool is_compensate_meas_cell_required; /* True if the suspend_req is triggered by RSVAU itself, UL1 may help to send a measurement_cell_ind */
1465} fdd_cphy_frequency_scan_suspend_req_struct;
1466
1467/* This interface should not be used in MT6268 */
1468typedef struct _fdd_cphy_frequency_scan_stop_req_struct
1469{
1470 LOCAL_PARA_HDR
1471} fdd_cphy_frequency_scan_stop_req_struct;
1472
1473/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_START_REQ (Add by Janet) */
1474typedef struct _fdd_cphy_rssi_sniffer_start_req_struct
1475{
1476 LOCAL_PARA_HDR
1477
1478 kal_uint8 num_freq_list; /* # of freq for scan list of RSSI sniffer */
1479 kal_uint16 uarfcn_list[FDD_MAX_RSSI_SNIFFER_SCAN_LIST]; /* List of UARFCN */
1480
1481} fdd_cphy_rssi_sniffer_start_req_struct;
1482
1483/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_STOP_REQ (Add by Janet) */
1484typedef struct _fdd_cphy_rssi_sniffer_stop_req_struct
1485{
1486 LOCAL_PARA_HDR
1487} fdd_cphy_rssi_sniffer_stop_req_struct;
1488
1489/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_PERIOD_CHANGE_REQ*/
1490typedef struct _fdd_cphy_rssi_sniffer_period_change_req_struct
1491{
1492 LOCAL_PARA_HDR
1493
1494 kal_uint8 periodicity_time; /*Range: [10,60], default: 30 // If the setting value is greater than the max value that xL1 can support, use the max supported value as setting*/
1495
1496} fdd_cphy_rssi_sniffer_period_change_req_struct;
1497
1498typedef struct _fdd_cphy_measurement_config_tgps_req_struct
1499{
1500 LOCAL_PARA_HDR
1501
1502 kal_int16 rx_cfn; /* message rx_cfn */
1503 FDD_tgps_status_info_T tgps_status_info; /* Used to enable/disable particular TGPSs */
1504
1505 kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
1506 FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
1507} fdd_cphy_measurement_config_tgps_req_struct;
1508
1509typedef struct _fdd_cphy_measurement_config_fmo_req_struct
1510{
1511 LOCAL_PARA_HDR
1512
1513 FDD_fach_mo_info_T fach_mo_info; /* FACH MO param */
1514} fdd_cphy_measurement_config_fmo_req_struct;
1515
1516typedef struct _fdd_cphy_auto_gap_on_req_struct
1517{
1518 LOCAL_PARA_HDR
1519} fdd_cphy_auto_gap_on_req_struct;
1520
1521typedef struct _fdd_cphy_auto_gap_on_cnf_struct
1522{
1523 LOCAL_PARA_HDR
1524} fdd_cphy_auto_gap_on_cnf_struct;
1525
1526typedef struct _fdd_cphy_auto_gap_off_req_struct
1527{
1528 LOCAL_PARA_HDR
1529} fdd_cphy_auto_gap_off_req_struct;
1530
1531typedef struct _fdd_cphy_auto_gap_off_cnf_struct
1532{
1533 LOCAL_PARA_HDR
1534} fdd_cphy_auto_gap_off_cnf_struct;
1535
1536typedef struct _fdd_cphy_measurement_config_cell_req_struct
1537{
1538 LOCAL_PARA_HDR
1539
1540 kal_uint8 tid; /* Transaction ID to sync between request and indication */
1541 kal_bool stop_flag; /* TRUE : just stop meas. UL1 will NOT clear all cell info list and meas param */
1542 FDD_CPHY_MEASUREMENT_STOP_CAUSE_E stop_cause; /* check this value only when stop_flag=TRUE */
1543
1544 kal_bool meas_spec_valid; /* Indicate if meas_spec is valid */
1545 FDD_meas_spec_T meas_spec; /* meas spec for CPICH cell meas */
1546
1547 kal_bool cell_info_list_valid; /* Indicate if cell_info_list[], uarfcn[] and action[] are valid */
1548 kal_uint16 uarfcn[FDD_MAX_UMTS_FREQ]; /* List of reference DL UARFCN */
1549 kal_uint8 num_cell; /* # of cells in cell_info_list[] */
1550 FDD_cell_info_list_T cell_info_list[FDD_MAX_NUM_MEASURED_CELL]; /* List of cells to be measured. */
1551 FDD_meas_act_E action[FDD_MAX_UMTS_FREQ]; /* Action that should be applied to cell lsits.
1552 FDD_MEAS_UPDATE : Add/Repleace cell list of a new specified freq (Both freq and cell list with tm/off are changed)
1553 FDD_MEAS_MODIFY : (20080130: Removed)
1554 FDD_MEAS_DELETE : Delete the cell list of a freq.
1555 */
1556
1557 FDD_supplementary_meas_parameter_T supplementary_meas_parameter; /* These parameters are supplementary for UL1 measurement. These parameters may be set by CSCE or MEME */
1558
1559 kal_int8 idx_intra_freq; /* [Range]: 0 ~ 2. Indicate which frequency in the array uarfcn[FDD_MAX_UMTS_FREQ] is intra-frequency, -1 means invalid */
1560
1561 kal_bool intra_meas_period_valid; /* Only for MTK L1: configure Intra-freq. meas. period in DCH/FACH */
1562 kal_uint8 intra_period_N; /* Num. of 40/50 ms */
1563
1564 kal_bool inter_meas_period_valid; /* Only for MTK L1: configure Inter-freq. meas. period in DCH/FACH */
1565 kal_uint8 inter_period_N; /* Num. of GAPs or FMOs */
1566
1567 kal_bool meas_period_valid; /* Only for MA */
1568 kal_uint16 period_unit; /* Only for MA */
1569 kal_uint8 period_N; /* Only for MA */
1570
1571#ifdef __UMTS_R8__
1572 kal_int16 T_higher_prio_search; /* [Rel8][Absolute Priority Search] -1: no need to watch priority_search_control in FDD_cell_info_list_T */
1573 /* [Rel8][Absolute Priority Search] others: real value for the timer */
1574
1575 kal_bool detected_cell_info_list_valid; /* [Rel8][CSG search]: to judge if detected cell list is valid, the list is configured under IDLE state */
1576 kal_uint8 num_detected_cell; /* [Rel8][CSG search]: number of detected cell, number <= 6 */
1577 FDD_cell_info_list_T detected_cell_info_list[6]; /* [Rel8][CSG search]: information of the detected cell list */
1578
1579 kal_bool non_compressed_mode_inter_freq[FDD_MAX_UMTS_FREQ]; /* Indicates which inter-frequency in the array uarfcn[] should be measured without compressed mode */
1580#endif /*__UMTS_R8__*/
1581
1582 kal_bool is_detected_cell_meas[FDD_MAX_UMTS_FREQ]; /* [MM] other-RATs can use this flag to trigger detected search */
1583 kal_bool is_standby_meas_period_reset; /* [Rel8][MM] MEME notifies UL1 if short period meas cell list changes. */
1584 /* If changes, measurement needs to be reconfigured (reset short period timer) */
1585 kal_bool is_standby_prio_meas_period_reset; /* [Rel8][MM] MEME notifies UL1 if long period meas cell list changes. */
1586 /* If changes, measurement needs to be reconfigured (reset long period timer) */
1587
1588 kal_bool prohibit_apply_n_layer; /* [Rel8][MM] Due to OOS, MEME notifies UL1 not to apply n_layer factor to accelerate meas frequency */
1589
1590 kal_int8 idx_first_meas_uarfcn_for_3g_standby; /* [Rel8][ABPCR] under standby mode, indicated uarfcn controlled by RR is first to be scheduling measured */
1591#ifdef __UMTS_R9__
1592 kal_int8 idx_sec_intra_freq; /* [R9]Indicates which frequency in the array uarfcn[] is secondary intra-freq. -1 measn invalid. [Range]0~3.*/
1593#endif /*__UMTS_R9__*/
1594} fdd_cphy_measurement_config_cell_req_struct;
1595
1596typedef struct _fdd_cphy_measurement_config_tx_power_req_struct
1597{
1598 LOCAL_PARA_HDR
1599
1600 kal_bool periodic_ind; /* Indicate periodically or event triggered. TRUE means period */
1601
1602 kal_uint8 periodic_measurement_id;
1603 kal_uint8 report_num; /* # of period report to be sent. 0 ~ 64 */
1604 kal_uint16 period; /* Report period. 25 ~ 6400 frames */
1605
1606 kal_uint8 event_num; /* # of events in event[] */
1607 FDD_meas_event_T event[FDD_MAX_MEAS_EVENT]; /* List of TX power meas event */
1608
1609 kal_uint8 filter; /* L3 filtering coefficient. 0 ~ 19 */
1610
1611} fdd_cphy_measurement_config_tx_power_req_struct;
1612
1613typedef struct _fdd_cphy_measurement_config_tx_power_stop_req_struct
1614{
1615 LOCAL_PARA_HDR
1616
1617} fdd_cphy_measurement_config_tx_power_stop_req_struct;
1618
1619
1620
1621typedef struct _fdd_cphy_treselection_start_req_struct
1622{
1623 LOCAL_PARA_HDR
1624
1625 kal_uint32 treselection_value; /* One shot cell measurement will be triggered after T_reselection.
1626 treselection_value can not be 0. uint = ms */
1627 kal_uint8 freq_num; /* Indicate the number of freq that need to perform CM after T_reselection.
1628 range: 1~FDD_MAX_UMTS_FREQ */
1629 kal_uint16 freq[FDD_MAX_UMTS_FREQ]; /* Indicate the frequency that need to perfrom CM. */
1630} fdd_cphy_treselection_start_req_struct;
1631
1632typedef struct _fdd_cphy_tx_power_result_req_struct
1633{
1634 LOCAL_PARA_HDR
1635} fdd_cphy_tx_power_result_req_struct;
1636
1637typedef struct _fdd_cphy_specific_cell_search_req_struct
1638{
1639 LOCAL_PARA_HDR
1640
1641 kal_uint16 freq; /* UARFCN of the specific cell */
1642 kal_uint16 psc; /* Primary scrambling code of the specific cell */
1643 kal_bool sttd; /* True if STTD is used in the designated cell. */
1644 kal_bool sttd_valid; /* True if sttd is useful to UL1 */
1645 kal_bool freq_correction; /* True if frequency correction is required */
1646
1647} fdd_cphy_specific_cell_search_req_struct;
1648
1649typedef struct _fdd_cphy_specific_cell_search_stop_req_struct
1650{
1651 LOCAL_PARA_HDR
1652} fdd_cphy_specific_cell_search_stop_req_struct;
1653
1654typedef struct _fdd_cphy_reset_req_struct
1655{
1656 LOCAL_PARA_HDR
1657} fdd_cphy_reset_req_struct;
1658
1659typedef struct _fdd_cphy_rf_on_req_struct
1660{
1661 LOCAL_PARA_HDR
1662
1663 kal_uint8 working_UMTS_FDD_band[4];
1664} fdd_cphy_rf_on_req_struct;
1665
1666typedef struct _fdd_cphy_rf_off_req_struct
1667{
1668 LOCAL_PARA_HDR
1669} fdd_cphy_rf_off_req_struct;
1670
1671typedef struct _fdd_cphy_set_active_rat_req_struct
1672{
1673 LOCAL_PARA_HDR
1674
1675 FDD_mode_type_E mode; /* Curernt mode setting (Single, Dual) */
1676 FDD_rat_type_E rat; /* Current active RAT setting (Flight, UMTS, GSM) */
1677 erac_rat_enum full_rat_info; /* Full RAT info */
1678} fdd_cphy_set_active_rat_req_struct;
1679
1680/* 20080131: By MEME's request, define new I/F for event 6E. */
1681typedef struct _fdd_cphy_measurement_config_rssi_event_req_struct
1682{
1683 LOCAL_PARA_HDR
1684
1685 kal_bool enable; /* Indicate if we need to monitor the 6E RSSI event. TRUE means to be activated */
1686 kal_uint16 delay; /* Time to Trigger. 0 ~ 500 frames */
1687} fdd_cphy_measurement_config_rssi_event_req_struct;
1688
1689/*-------- Message(Primitive) related definition ----------------------*/
1690
1691typedef struct _FDD_msg_buf_T /* Buffer of message container */
1692{
1693 kal_uint8 channel_id; /* Channel ID */
1694 msg_type msg_id; /* Message ID */
1695 kal_uint16 buff_size; /* Buffer size */
1696 local_para_struct *buffer; /* Channel configuration message buffer */
1697} FDD_msg_buf_T;
1698
1699
1700typedef struct _fdd_cphy_msg_container_req_struct
1701{
1702 LOCAL_PARA_HDR
1703
1704 kal_uint8 at_ref; /* Reference channge of activation time.
1705 0 : Ref channel is the released channel.
1706 There should be ch to be released
1707 1 : Ref channel is the setup channel.
1708 There should be ch to be setup.
1709 */
1710 kal_int16 rx_cfn; /* Indicate peer message receive cfn. Ex: tti = 4, receive frame number : 0,1,2,3. rx_cfn = 3 (set by ul1)
1711 [Range]: -1 ~ 255.
1712 -1 : Means upper layer internal control
1713 */
1714#ifdef __UMTS_R6__
1715 kal_bool delay_restriction; /* From R6 : TS25.331 8.6.3.1 */
1716#endif
1717 FDD_meas_control_E meas_control; /* Indicate whether UL1 need to not to resume meas. after apply corresponding buffer's config. */
1718
1719 kal_uint8 msg_num; /* # of included msg. 1 ~ 4 */
1720 FDD_msg_buf_T msg_buffer[4]; /* List of msg buffer for included channel msg */
1721
1722 /* [R5R6] For HS-DSCH and E-DCH */
1723 kal_uint8 h_msg_num; /* # of included H-msg. 0~2 */
1724 FDD_msg_buf_T h_msg_buffer[2]; /* List of msg buffer for included channel msg */
1725 kal_uint8 e_msg_num; /* # of included E-msg. 0~2 */
1726 FDD_msg_buf_T e_msg_buffer[2]; /* List of msg buffer for included channel msg */
1727#ifdef __UMTS_R7__
1728 kal_uint8 cpc_msg_num; /* # of included CPC-msg. 0~1 */
1729 FDD_msg_buf_T cpc_msg_buffer[1]; /* List of msg buffer for included CPC msg */
1730#endif /* __UMTS_R7__ */
1731// PLMN releated info
1732 FDD_PLMN_LAC_PARAM_T plmn_info; /*PLMN, RAC and LAC info*/
1733// RLC window size info
1734 kal_uint8 rlc_info_msg_num; /* # of included rlc_info */
1735 FDD_RLC_WINDOW_SIZE_INFO_T rlc_info_msg_buffer[4]; /* List of msg buffer for included rlc_info msg */
1736} fdd_cphy_msg_container_req_struct;
1737
1738typedef struct _fdd_cphy_abort_req_struct
1739{
1740 LOCAL_PARA_HDR
1741} fdd_cphy_abort_req_struct;
1742
1743typedef struct _fdd_cphy_TAS_notify_ind_struct
1744{
1745 LOCAL_PARA_HDR
1746} fdd_cphy_TAS_notify_ind_struct;
1747/****************************************************************/
1748/* __HSDPA_SUPPORT__ */
1749typedef struct _fdd_cphy_hsdsch_setup_req_struct
1750{
1751 LOCAL_PARA_HDR
1752
1753 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1754
1755 FDD_dl_dpch_rla_T hsdsch_rla; /* Downlink information common for all RLs and downlink DPCH info. common for all RLs */
1756 /* tgps_num in hsdsch_rla should be 0.*/
1757 FDD_dl_dpch_rl_T hsdsch_rl; /* Downlink information for each RL (and downlink DPCH info. for each RL (for HS-DSCH serving cell*/
1758 FDD_hs_scch_info_T hs_scch_info; /* HS-SCCH Info (25.331 10.3.6.36a) */
1759 FDD_hs_meas_fb_info_T hs_meas_fb_info; /* Measurement Feedback Info (25.331 10.3.6.40a) */
1760 FDD_hs_harq_info_T hs_harq_info; /* HARQ Info (25.331 10.3.5.7a) */
1761 FDD_hs_ulpc_info_T hs_ulpc_info; /* Uplink power control info related to HSDPA */
1762
1763 kal_bool mac_hs_reset; /* TRUE indicates the MAC-hs entity needs to be reset */
1764 kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
1765 kal_uint16 h_rnti; /* H-RNTI assigned to UE */
1766#ifdef __UMTS_R7__
1767 FDD_rrc_state_E rrc_status; /* Indicate the RRC current status */
1768 FDD_hspdsch_state_info_T hspdsch_state_info; /* HSPDSCH related parameter */
1769 FDD_hs_scch_less_info_T hs_scch_less_info; /* HS-SCCH less Info (25.331 10.3.6.36ab) */
1770 kal_bool h_rnti_valid; /* Indicate if h_rnti field is valid for UL1. H-RNTI shall be always valid for CELL_DCH, CELL_FACH, IDLE_FACH, and shall be always invalid for URA_PCH. */
1771 kal_bool c_h_rnti_valid; /* [R7] Indicate if common H-RNTI is valid for UL1. This field shall be set to FALSE when rrc_status is equal to CELL_DCH. */
1772 kal_uint16 c_h_rnti; /* [R7] Common H-RNTI assigned to UE. UL1 should not refer to this field if c_h_rnti_valid = KAL_FALSE. */
1773 kal_bool b_h_rnti_valid; /* [R7] Indicate if bcch-specific H-RNTI is valid for UL1 */
1774 kal_uint16 b_h_rnti; /* [R7] bcch-specific H-RNTI assigned to UE. UL1 should not refer to this field if b_h_rnti_valid = KAL_FALSE. */
1775#ifdef __UMTS_R8__
1776 kal_bool cqi_report_on; /* This field should always be TRUE when rrc_status = CELL_DCH, and should always be FALSE when rrc_status = CELL_PCH and URA_PCH. */
1777 kal_bool ack_nack_report_on; /* This field should always be TRUE when rrc_status = CELL_DCH, and should always be FALSE when rrc_status = CELL_PCH and URA_PCH. */
1778 FDD_hs_cell_fach_drx_T hs_cell_fach_drx; /* HS CELL_FACH DRX information. This field is only valid when rrc_status = CELL_FACH. */
1779 FDD_dc_hsdpa_info_T dc_hsdpa_info; /* DC-HSDPA information. This field is only valid when rrc_status = CELL_DCH. */
1780 FDD_dl_pc_info_T dl_pc_common_edch; /* dl power control info. This field in only valid in EFACH state with common E-DCH transmission */
1781#ifdef __UMTS_R10__
1782 FDD_dc_hsdpa_info_T addi_dc_hsdpa_info[FDD_MAX_ADDI_DC_HSDPA]; /* Additional DC-HSDPA information. This field is only valid when rrc_status = CELL_DCH.
1783 FDD_MAX_ADDI_DC_HSDPA = 2. */
1784#endif /* __UMTS_R10__ */
1785#endif /* __UMTS_R8__ */
1786#endif /* __UMTS_R7__ */
1787} fdd_cphy_hsdsch_setup_req_struct;
1788
1789typedef struct _fdd_cphy_hsdsch_modify_req_struct
1790{
1791 LOCAL_PARA_HDR
1792
1793 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1794
1795#ifdef __UMTS_R7__
1796 kal_uint16 modify_field; /* Bit field to represent for the parameters that should be modified
1797 Bit 0 : dedicated H-RNTI or common H-RNTI
1798 Bit 1 : hsdsch_rla
1799 Bit 2 : hsdsch_rl
1800 Bit 3 : HS-SCCH Info
1801 Bit 4 : Measurement Feedback Info
1802 Bit 5 : HARQ Info
1803 Bit 6 : Uplink power control info related to HSDPA
1804 Bit 7 : h_rnti_valid or hspdsch_state_info
1805 Bit 8 : HS-SCCH less Info
1806 Bit 9 : [R8] FDD_dc_hsdpa_info_T
1807 Bit10 : [R8] FDD_hs_cell_fach_drx_T
1808 Bit11 : [R10] addi_dc_hsdpa_info[0]
1809 */
1810#else /* __UMTS_R7__ */
1811 kal_uint8 modify_field; /* Bit field to represent for the parameters that should be modified
1812 Bit 0 : H-RNTI
1813 Bit 1 : hsdsch_rla
1814 Bit 2 : hsdsch_rl
1815 Bit 3 : HS-SCCH Info
1816 Bit 4 : Measurement Feedback Info
1817 Bit 5 : HARQ Info
1818 Bit 6 : Uplink power control info related to HSDPA
1819 */
1820#endif /* !__UMTS_R7__ */
1821 FDD_dl_dpch_rla_T hsdsch_rla; /* Downlink information common for all RLs and downlink DPCH info. common for all RLs */
1822 /* tgps_num in hsdsch_rla should be 0.*/
1823 FDD_dl_dpch_rl_T hsdsch_rl; /* Downlink information for each RL (and downlink DPCH info. for each RL (for HS-DSCH serving cell*/
1824 FDD_hs_scch_info_T hs_scch_info; /* HS-SCCH Info (25.331 10.3.6.36a) */
1825 FDD_hs_meas_fb_info_T hs_meas_fb_info; /* Measurement Feedback Info (25.331 10.3.6.40a) */
1826 FDD_hs_harq_info_T hs_harq_info; /* HARQ Info (25.331 10.3.5.7a) */
1827 FDD_hs_ulpc_info_T hs_ulpc_info; /* Uplink power control info related to HSDPA */
1828 kal_bool mac_hs_reset; /* TRUE indicates the MAC-hs entity needs to be reset */
1829 kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
1830 kal_uint16 h_rnti; /* H-RNTI assigned to UE */
1831#ifdef __UMTS_R7__
1832 FDD_rrc_state_E rrc_status; /* Indicate the RRC current status */
1833 FDD_hspdsch_state_info_T hspdsch_state_info; /* HSPDSCH related parameter */
1834 FDD_hs_scch_less_info_T hs_scch_less_info; /* HS-SCCH less Info (25.331 10.3.6.36ab) */
1835 kal_bool h_rnti_valid; /* Indicate if h_rnti field is valid for UL1. H-RNTI shall be always valid for CELL_DCH, CELL_FACH, IDLE_FACH, and shall be always invalid for URA_PCH. */
1836 kal_bool c_h_rnti_valid; /* [R7] Indicate if common H-RNTI is valid for UL1. This field shall be set to FALSE when rrc_status is equal to CELL_DCH. */
1837 kal_uint16 c_h_rnti; /* [R7] Common H-RNTI assigned to UE. UL1 should not refer to this field if c_h_rnti_valid = KAL_FALSE. */
1838 kal_bool b_h_rnti_valid; /* [R7] Indicate if bcch-specific H-RNTI is valid for UL1 */
1839 kal_uint16 b_h_rnti; /* [R7] bcch-specific H-RNTI assigned to UE. UL1 should not refer to this field if b_h_rnti_valid = KAL_FALSE. */
1840#ifdef __UMTS_R8__
1841 kal_bool cqi_report_on; /* This field should always be TRUE when rrc_status = CELL_DCH, and should always be FALSE when rrc_status = CELL_PCH and URA_PCH. */
1842 kal_bool ack_nack_report_on; /* This field should always be TRUE when rrc_status = CELL_DCH, and should always be FALSE when rrc_status = CELL_PCH and URA_PCH. */
1843 FDD_hs_cell_fach_drx_T hs_cell_fach_drx; /* HS CELL_FACH DRX information. This field is only valid when rrc_status = CELL_FACH. */
1844 FDD_dc_hsdpa_info_T dc_hsdpa_info; /* DC-HSDPA information. This field is only valid when rrc_status = CELL_DCH. */
1845#ifdef __UMTS_R10__
1846 FDD_dc_hsdpa_info_T addi_dc_hsdpa_info[FDD_MAX_ADDI_DC_HSDPA]; /* Additional DC-HSDPA information. This field is only valid when rrc_status = CELL_DCH.
1847 FDD_MAX_ADDI_DC_HSDPA = 2. */
1848#endif /* __UMTS_R10__ */
1849#endif /* __UMTS_R8__ */
1850#endif /* __UMTS_R7__ */
1851} fdd_cphy_hsdsch_modify_req_struct;
1852
1853typedef struct _fdd_cphy_hsdsch_release_req_struct
1854{
1855 LOCAL_PARA_HDR
1856
1857 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1858
1859 kal_bool mac_hs_reset; /* TRUE indicates the MAC-hs entity needs to be reset */
1860 kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
1861} fdd_cphy_hsdsch_release_req_struct;
1862
1863#ifdef __UMTS_R7__
1864typedef struct _FDD_phy_mac_ehs_reset_req_struct
1865{
1866 LOCAL_PARA_HDR
1867
1868 FDD_mac_ehs_reset_cause_E cause; /* Indicate the cause about the reason of UMAC reset */
1869} fdd_phy_mac_ehs_reset_req_struct;
1870#endif /* __UMTS_R7__ */
1871
1872#ifdef __UMTS_R7__
1873typedef struct _fdd_cphy_cpc_config_req_struct
1874{
1875 LOCAL_PARA_HDR
1876
1877 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1878 FDD_hs_dtx_drx_info_T hs_dtx_drx_info; /* DTX/DRX information */
1879} fdd_cphy_cpc_config_req_struct;
1880
1881typedef struct _fdd_cphy_d_hrnti_detected_ind_struct
1882{
1883 LOCAL_PARA_HDR
1884} fdd_cphy_d_hrnti_detected_ind_struct;
1885
1886#ifdef __UMTS_R8__
1887typedef struct _fdd_cphy_start_monitor_order_req_struct
1888{
1889 LOCAL_PARA_HDR
1890
1891 kal_uint16 h_rnti; /* h_rnti to decode target cell HS-SCCH */
1892 kal_uint16 psc; /* psc to receive target cell HS-SCCH */
1893 FDD_hs_scch_info_T hs_scch_info; /* ovsf_code_num field should always be 1 */
1894 kal_int16 rpt_act_time; /* [Range]: (-1~255). (0-255) for CFN type, */
1895} fdd_cphy_start_monitor_order_req_struct;
1896
1897typedef struct _fdd_cphy_start_monitor_order_cnf_struct
1898{
1899 LOCAL_PARA_HDR
1900} fdd_cphy_start_monitor_order_cnf_struct;
1901
1902typedef struct _fdd_cphy_stop_monitor_order_req_struct
1903{
1904 LOCAL_PARA_HDR
1905} fdd_cphy_stop_monitor_order_req_struct;
1906
1907typedef struct _fdd_cphy_stop_monitor_order_cnf_struct
1908{
1909 LOCAL_PARA_HDR
1910} fdd_cphy_stop_monitor_order_cnf_struct;
1911
1912typedef struct _fdd_cphy_monitor_order_received_ind_struct
1913{
1914 LOCAL_PARA_HDR
1915
1916 kal_uint16 psc; /* Range: {0..511} */
1917 kal_int16 act_time; /* Range {-1..255}: -1 is T324, 0..255 is AT */
1918 kal_uint16 rx_cfn;
1919} fdd_cphy_monitor_order_received_ind_struct;
1920#endif /* __UMTS_R8__ */
1921
1922#endif /* __UMTS_R7__ */
1923
1924typedef struct _fdd_cphy_rlc_info_req_struct
1925{
1926 LOCAL_PARA_HDR
1927
1928 kal_uint16 distance[FDD_MAX_HS_RB_NUM]; /* The distance between VR_H and VR_R (VR_H - VR_R) */
1929 kal_uint32 rx_window_size[FDD_MAX_HS_RB_NUM];
1930 kal_uint32 RTT[FDD_MAX_HS_RB_NUM]; /* Round trip time */
1931} fdd_cphy_rlc_info_req_struct;
1932
1933/****************************************************************/
1934
1935/****************************************************************/
1936/* __HSUPA_SUPPORT__ */
1937typedef struct _fdd_cphy_edch_setup_req_struct
1938{
1939 LOCAL_PARA_HDR
1940
1941 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1942
1943 kal_bool pri_e_rnti_valid; /* Indicate if pri_e_rnti field is valid */
1944 kal_uint16 pri_e_rnti; /* Primary E-RNTI assigned to UE */
1945 kal_bool sec_e_rnti_valid; /* Indicate if sec_e_rnti field is valid */
1946 kal_uint16 sec_e_rnti; /* Secondary E-RNTI assigned to UE */
1947
1948 FDD_edch_tti_E edch_tti; /* E-DCH TTI 2ms or 10ms */
1949
1950 kal_uint16 edch_serv_psc; /* serving E-DCH cell */
1951
1952 FDD_eagch_info_T eagch_info; /* E-AGCH info*/
1953
1954 kal_uint8 ehich_info_num; /* Number of E-HICH info: 1~FDD_MAX_EDCH_RL */
1955 FDD_ehich_info_T ehich_info[FDD_MAX_EDCH_RL]; /* E-HICH info */
1956 kal_uint8 ergch_info_num; /* Number of E-RGCH info: 0~FDD_MAX_EDCH_RL */
1957 FDD_ergch_info_T ergch_info[FDD_MAX_EDCH_RL]; /* E-RGCH info */
1958
1959 FDD_edpdch_info_T edpdch_info; /* E-DPDCH info */
1960 FDD_edpcch_info_T edpcch_info; /* E-DPCCH info */
1961
1962 FDD_edch_harq_info_T edch_harq_info; /* HARQ info for E-DCH */
1963
1964 kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
1965#ifdef __UMTS_R7__
1966 kal_bool ul_16QAM_on; /* Uplink 16QAM enable/disable */
1967#endif /* __UMTS_R7__ */
1968#ifdef __UMTS_R8__
1969 FDD_edch_transmission_type_E transmission_type; /* Specify that E-DCH is allocated in dedicated state or common state */
1970 FDD_common_edch_info_T common_edch_info; /* [R8] This field is only valid when transmission_type is equal to FDD_EDCH_IN_COMMON_STATE */
1971#ifdef __UMTS_R9__
1972 FDD_dc_hsupa_info_T dc_hsupa_info; /* [R9] DC-HSUPA information. This field is only valid when rrc_status = CELL_DCH. */
1973#endif /* __UMTS_R9__ */
1974#endif /* __UMTS_R8__ */
1975} fdd_cphy_edch_setup_req_struct;
1976
1977typedef struct _fdd_cphy_edch_modify_req_struct
1978{
1979 LOCAL_PARA_HDR
1980
1981 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
1982
1983 kal_uint16 modify_field; /* Bit field to represent for the parameters that should be modified
1984 Bit 0 : E-RNTI
1985 Bit 1 : E-DCH TTI
1986 Bit 2 : E-AGCH info
1987 Bit 3 : E-HICH info
1988 Bit 4 : E-RGCH info
1989 Bit 5 : E-DPDCH info
1990 Bit 6 : E-DPCCH info
1991 Bit 7 : E-DCH serving cell
1992 Bit 8 : E-DCH harq info
1993 Bit 9 : ul_16QAM_on
1994 Bit 10: [R8] FDD_common_edch_info_T
1995 Bit 11: [R9] FDD_dc_hsupa_info_T
1996 */
1997
1998 kal_bool pri_e_rnti_valid; /* Indicate if pri_e_rnti field is valid */
1999 kal_uint16 pri_e_rnti; /* Primary E-RNTI assigned to UE */
2000 kal_bool sec_e_rnti_valid; /* Indicate if sec_e_rnti field is valid */
2001 kal_uint16 sec_e_rnti; /* Secondary E-RNTI assigned to UE */
2002 FDD_edch_tti_E edch_tti; /* E-DCH TTI 2ms or 10ms */
2003
2004 kal_uint16 edch_serv_psc; /* serving E-DCH cell */
2005
2006 FDD_eagch_info_T eagch_info; /* E-AGCH info*/
2007
2008 kal_uint8 ehich_info_num; /* Number of E-HICH info: 1~FDD_MAX_EDCH_RL */
2009 FDD_ehich_info_T ehich_info[FDD_MAX_EDCH_RL]; /* E-HICH info */
2010 kal_uint8 ergch_info_num; /* Number of E-RGCH info: 0~FDD_MAX_EDCH_RL */
2011 FDD_ergch_info_T ergch_info[FDD_MAX_EDCH_RL]; /* E-RGCH info */
2012
2013 FDD_edpdch_info_T edpdch_info; /* E-DPDCH info */
2014 FDD_edpcch_info_T edpcch_info; /* E-DPCCH info */
2015
2016 FDD_edch_harq_info_T edch_harq_info; /* HARQ info for E-DCH */
2017
2018 kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
2019#ifdef __UMTS_R7__
2020 kal_bool ul_16QAM_on; /* Uplink 16QAM enable/disable */
2021#endif /* __UMTS_R7__ */
2022#ifdef __UMTS_R8__
2023 FDD_edch_transmission_type_E transmission_type; /* Specify that E-DCH is allocated in dedicated state or common state */
2024 FDD_common_edch_info_T common_edch_info; /* [R8] This field is only valid when transmission_type is equal to FDD_EDCH_IN_COMMON_STATE */
2025#ifdef __UMTS_R9__
2026 FDD_dc_hsupa_info_T dc_hsupa_info; /* [R9] DC-HSUPA information. This field is only valid when rrc_status = CELL_DCH. */
2027#endif /* __UMTS_R9__ */
2028#endif /* __UMTS_R8__ */
2029} fdd_cphy_edch_modify_req_struct;
2030
2031typedef struct _fdd_cphy_edch_release_req_struct
2032{
2033 LOCAL_PARA_HDR
2034
2035 kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
2036 kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
2037} fdd_cphy_edch_release_req_struct;
2038/****************************************************************/
2039
2040/****************************************************************/
2041/* GEMINI 2.0 */
2042#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
2043typedef struct _fdd_cphy_channel_priority_adjustment_req_struct
2044{
2045 LOCAL_PARA_HDR
2046#ifdef __MODIFY_CTCH_RECEPTION_PRIO__
2047 FDD_rrce_gemini_priority_adjust_E channel_priority;
2048#else
2049 kal_bool channel_priority_high; /* TRUE: UL1 channel priority is set to high. The priority of the timer related DCH/FACH will has the highest priority.
2050 FALSE: UL1 channel priority is set to normal. The priority of the timer related DCH/FACH will has the lowest priority. */
2051 FDD_rrce_gemini_priority_adjust_E adjust_channel;
2052#endif
2053} fdd_cphy_channel_priority_adjustment_req_struct;
2054
2055typedef struct _FDD_urr_ul1_switch_gemini_mode_req_struct
2056{
2057 LOCAL_PARA_HDR
2058
2059 kal_bool is_virtual_mode; /* TRUE: UL1 will switch from Normal mode to Virtual mode.
2060 FALSE: UL1 will switch from Virtual mode to Normal mode. */
2061} fdd_urr_ul1_switch_gemini_mode_req_struct;
2062
2063
2064typedef struct _fdd_cphy_peer_gemini_mode_notify_req_struct
2065{
2066 LOCAL_PARA_HDR
2067
2068 kal_bool is_peer_virtual_mode; /* TRUE: UL1 is informed that peer SIM enters virtual mode.
2069 FALSE: UL1 is informed that peer SIM leaves virtual mode. */
2070} fdd_cphy_peer_gemini_mode_notify_req_struct;
2071
2072
2073
2074typedef struct _FDD_rsvas_ul1_virtual_resume_req_struct
2075{
2076 LOCAL_PARA_HDR
2077} fdd_rsvas_ul1_virtual_resume_req_struct;
2078
2079#endif /* __GEMINI__ && __UMTS_RAT__ */
2080
2081typedef struct _fdd_cphy_rb_lpbk_req_struct
2082{
2083 LOCAL_PARA_HDR
2084} fdd_cphy_rb_lpbk_req_struct;
2085
2086/****************************************************************/
2087
2088
2089/*****************************************************************************
2090 confirm & indication for cphy
2091*****************************************************************************/
2092typedef struct _fdd_cphy_rb_lpbk_cnf_struct
2093{
2094 LOCAL_PARA_HDR
2095} fdd_cphy_rb_lpbk_cnf_struct;
2096
2097typedef struct _fdd_cphy_bch_setup_cnf_struct
2098{
2099 LOCAL_PARA_HDR
2100} fdd_cphy_bch_setup_cnf_struct;
2101
2102typedef struct _fdd_cphy_bch_setup_ind_struct
2103{
2104 LOCAL_PARA_HDR
2105
2106 kal_bool success; /* Indicate if BCH setup success.
2107 For current L1, it always return true.
2108 */
2109} fdd_cphy_bch_setup_ind_struct;
2110
2111typedef struct _fdd_cphy_bch_modify_cnf_struct
2112{
2113 LOCAL_PARA_HDR
2114} fdd_cphy_bch_modify_cnf_struct;
2115
2116typedef struct _fdd_cphy_bch_modify_ind_struct
2117{
2118 LOCAL_PARA_HDR
2119} fdd_cphy_bch_modify_ind_struct;
2120
2121typedef struct _fdd_cphy_bch_release_cnf_struct
2122{
2123 LOCAL_PARA_HDR
2124} fdd_cphy_bch_release_cnf_struct;
2125
2126typedef struct _fdd_cphy_bch_release_ind_struct
2127{
2128 LOCAL_PARA_HDR
2129} fdd_cphy_bch_release_ind_struct;
2130
2131typedef struct _fdd_cphy_sfn_ind_struct
2132{
2133 LOCAL_PARA_HDR
2134
2135 kal_bool success; /* Indicate if SFN ready success */
2136 kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
2137 kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
2138
2139 kal_uint16 dl_freq; /* UARFCN of the specific cell */
2140 kal_uint16 psc; /* Primary scrambling code of the specific cell */
2141
2142 kal_bool dch_meas_valid; /* TRUE: DCH related parameters are valid */
2143 kal_uint8 CFN; /* CFN of serving cell*/
2144 kal_uint16 SFN; /* SFN of neighbor cell*/
2145 kal_uint8 meas_off; /* SFN_CFN difference in frames*/
2146 kal_uint16 meas_tm; /* SFN_CFN difference in chips*/
2147
2148 kal_bool common_meas_valid; /* TRUE: common channel related parameter is valid */
2149 kal_uint32 meas_sfn_diff; /* SFN_SFN difference in chips*/
2150
2151#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
2152 FDD_uas_gemini_conflict_cause_enum conflict_cause;
2153 kal_uint16 peer_priority_index;
2154#endif
2155
2156} fdd_cphy_sfn_ind_struct;
2157
2158
2159/* MEME use this primitive as a trigger point to query UL1 tgps status */
2160typedef struct _fdd_cphy_tgps_delete_ind_struct
2161{
2162 LOCAL_PARA_HDR
2163
2164 kal_uint8 tgpsi_nbr; /* Number of TGPSI deleted */
2165 kal_uint8 tgpsi[FDD_MAX_TGPS]; /* TGPSI deleted*/
2166} fdd_cphy_tgps_delete_ind_struct;
2167
2168typedef struct _fdd_cphy_tgps_info_ind_struct
2169{
2170 LOCAL_PARA_HDR
2171
2172 umts_fdd_dch_gap_struct dch_gap_pattern; /* The latest TGPS pattern indicator */
2173} fdd_cphy_tgps_info_ind_struct;
2174
2175typedef struct _fdd_cphy_tgps_overlap_ind_struct
2176{
2177 LOCAL_PARA_HDR
2178
2179 kal_uint8 tgpsi; /* TGPSI of TGPS beging removed. 1 ~ 6 */
2180} fdd_cphy_tgps_overlap_ind_struct;
2181
2182typedef struct _fdd_cphy_gap_complete_ind_struct
2183{
2184 LOCAL_PARA_HDR
2185
2186 kal_uint8 tgpsi; /* TGPSI of TGPS beging completed. 1 ~ 6 */
2187} fdd_cphy_gap_complete_ind_struct;
2188
2189typedef struct _fdd_cphy_t312_expiry_ind_struct
2190{
2191 LOCAL_PARA_HDR
2192
2193 kal_uint8 tid; /* Transaction id */
2194
2195} fdd_cphy_t312_expiry_ind_struct;
2196
2197typedef struct _fdd_cphy_dl_init_sync_ind_struct
2198{
2199 LOCAL_PARA_HDR
2200
2201 kal_uint8 tid; /* Transaction id */
2202 kal_int32 dpch_tm; /* For CFN-SFN TD */
2203 kal_int16 dpch_off; /* For CFN-SFN TD */
2204} fdd_cphy_dl_init_sync_ind_struct;
2205
2206typedef struct _phy_ul_not_activated_ind_struct
2207{
2208 LOCAL_PARA_HDR
2209} phy_ul_not_activated_ind_struct;
2210
2211typedef struct _fdd_cphy_rl_failure_ind_struct
2212{
2213 LOCAL_PARA_HDR
2214} fdd_cphy_rl_failure_ind_struct;
2215
2216/*Raymond 20070717 remove DELETE_TGPS CNF/IND interface*/
2217typedef struct _fdd_cphy_frequency_scan_cnf_struct
2218{
2219 LOCAL_PARA_HDR
2220} fdd_cphy_frequency_scan_cnf_struct;
2221
2222typedef struct _fdd_cphy_frequency_scan_ind_struct
2223{
2224 LOCAL_PARA_HDR
2225} fdd_cphy_frequency_scan_ind_struct;
2226
2227typedef struct _fdd_cphy_frequency_scan_continue_cnf_struct
2228{
2229 LOCAL_PARA_HDR
2230} fdd_cphy_frequency_scan_continue_cnf_struct;
2231
2232typedef struct _fdd_cphy_frequency_scan_suspend_cnf_struct
2233{
2234 LOCAL_PARA_HDR
2235} fdd_cphy_frequency_scan_suspend_cnf_struct;
2236
2237typedef struct _fdd_cphy_frequency_scan_suspend_ind_struct
2238{
2239 LOCAL_PARA_HDR
2240} fdd_cphy_frequency_scan_suspend_ind_struct;
2241
2242/* This interface should not be used in MT6268 */
2243typedef struct _fdd_cphy_frequency_scan_stop_cnf_struct
2244{
2245 LOCAL_PARA_HDR
2246} fdd_cphy_frequency_scan_stop_cnf_struct;
2247
2248/* This interface should not be used in MT6268 */
2249typedef struct _fdd_cphy_frequency_scan_stop_ind_struct
2250{
2251 LOCAL_PARA_HDR
2252} fdd_cphy_frequency_scan_stop_ind_struct;
2253
2254/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_START_CNF (Add by Janet) */
2255typedef struct _fdd_cphy_rssi_sniffer_start_cnf_struct
2256{
2257 LOCAL_PARA_HDR
2258} fdd_cphy_rssi_sniffer_start_cnf_struct;
2259
2260/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_STOP_CNF (Add by Janet) */
2261typedef struct _fdd_cphy_rssi_sniffer_stop_cnf_struct
2262{
2263 LOCAL_PARA_HDR
2264
2265} fdd_cphy_rssi_sniffer_stop_cnf_struct;
2266
2267/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_STOP_IND (Add by Janet) */
2268typedef struct _fdd_cphy_rssi_sniffer_stop_ind_struct
2269{
2270 LOCAL_PARA_HDR
2271} fdd_cphy_rssi_sniffer_stop_ind_struct;
2272
2273/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_SIGNAL_APPEAR_IND (Add by Janet) */
2274typedef struct _fdd_cphy_rssi_sniffer_signal_appear_ind_struct
2275{
2276 LOCAL_PARA_HDR
2277
2278 kal_uint8 num_freq_list; /* # of freq for scan list of RSSI sniffer */
2279 kal_uint16 uarfcn_list[FDD_MAX_RSSI_SNIFFER_SCAN_LIST]; /* List of UARFCN */
2280
2281} fdd_cphy_rssi_sniffer_signal_appear_ind_struct;
2282
2283/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_EXECUTED_IND */
2284typedef struct _fdd_cphy_rssi_sniffer_executed_ind_struct
2285{
2286 LOCAL_PARA_HDR
2287} fdd_cphy_rssi_sniffer_executed_ind_struct;
2288typedef struct _fdd_cphy_measurement_config_tgps_cnf_struct
2289{
2290 LOCAL_PARA_HDR
2291} fdd_cphy_measurement_config_tgps_cnf_struct;
2292
2293typedef struct _fdd_cphy_measurement_config_tgps_ind_struct
2294{
2295 LOCAL_PARA_HDR
2296} fdd_cphy_measurement_config_tgps_ind_struct;
2297
2298typedef struct _fdd_cphy_measurement_config_fmo_cnf_struct
2299{
2300 LOCAL_PARA_HDR
2301} fdd_cphy_measurement_config_fmo_cnf_struct;
2302
2303typedef struct _fdd_cphy_measurement_config_cell_cnf_struct
2304{
2305 LOCAL_PARA_HDR
2306
2307 kal_uint8 tid; /* Transaction ID to sync between req and ind */
2308} fdd_cphy_measurement_config_cell_cnf_struct;
2309
2310typedef struct _fdd_cphy_measurement_cell_ind_struct
2311{
2312 LOCAL_PARA_HDR
2313
2314 kal_uint8 tid; /* Transaction ID to sync between req and ind */
2315 FDD_measured_type_E measured_type; /*IntraFrequency or InterFrequency*/
2316 kal_uint16 uarfcn; /* DL UARFCN */
2317 kal_int16 rssi; /* RSSI. Range: -400 ~ -100 means (-100 ~ -25)dBm 0.25 dB step */
2318 kal_bool fs_halt; /* Indicate if freq scan halt. only for freq scan report */
2319 kal_bool isSuspendByRSVAU; /* Indicate CSE the frequency is suspended. Only TRUE if UL1 receive suspend_req in FS_START and FS_CONTINUE. */
2320 kal_uint8 num_cell; /* # of cell reported in this msg */
2321 FDD_measured_cell_T measured_cell[FDD_MAX_NUM_MEAS_CELL]; /* list of measured cells */
2322 kal_bool rl_status; /* Indicate tx available */
2323#ifdef __UMTS_R8__
2324 kal_bool isLongPeriodIn3GStandby; /* [Rel8][ABPCR] For RR, Indicate if it is prio search peiorid*/
2325#endif
2326 FDD_supplementary_report_info_T supplementary_report_info; /* to notify L3 further information */
2327 kal_bool sttd_valid; /* Indicate sttd result is valid (reliable) or not */
2328} fdd_cphy_measurement_cell_ind_struct;
2329
2330typedef struct _fdd_cphy_measurement_cell_sfn_ind_struct
2331{
2332 LOCAL_PARA_HDR
2333
2334 kal_uint16 dl_freq; /* UARFCN of the specific cell */
2335 kal_uint16 psc; /* Primary scrambling code of the specific cell */
2336 kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
2337 kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
2338 kal_uint16 SFN; /* SFN of neighbor cell*/
2339 kal_bool sttd; /* STTD info of the specified cell */
2340
2341#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
2342 FDD_uas_gemini_conflict_cause_enum conflict_cause;
2343#endif
2344} fdd_cphy_measurement_cell_sfn_ind_struct;
2345
2346typedef struct _fdd_cphy_measurement_rl_ind_struct
2347{
2348 LOCAL_PARA_HDR
2349
2350 kal_uint8 rl_num; /* # of RL */
2351 FDD_rl_meas_result_T rl_meas_result[FDD_MAX_RL]; /* RL measurement result for each RL */
2352 kal_int16 tx_power; /* Averaged TX power meas result */
2353} fdd_cphy_measurement_rl_ind_struct;
2354
2355typedef struct _fdd_cphy_measurement_config_tx_power_cnf_struct
2356{
2357 LOCAL_PARA_HDR
2358} fdd_cphy_measurement_config_tx_power_cnf_struct;
2359
2360typedef struct _fdd_cphy_measurement_tx_power_periodic_ind_struct
2361{
2362 LOCAL_PARA_HDR
2363
2364 kal_uint8 periodic_measurement_id;
2365 kal_int16 tx_power; /* Averaged TX power meas result */
2366 kal_bool last_report; /* Indicate if this is the last report for period rpt */
2367} fdd_cphy_measurement_tx_power_periodic_ind_struct;
2368
2369typedef struct _fdd_cphy_measurement_tx_power_event_ind_struct
2370{
2371 LOCAL_PARA_HDR
2372
2373 kal_int16 tx_power; /* Averaged TX power meas result */
2374 kal_uint8 event_id; /* Event ID being triggered */
2375 kal_uint8 measurement_id; /* Measurement ID being triggered. */
2376} fdd_cphy_measurement_tx_power_event_ind_struct;
2377
2378typedef struct _fdd_cphy_tx_power_result_ind_struct
2379{
2380 LOCAL_PARA_HDR
2381
2382 kal_bool valid; /* Indicate if below tx_power is vaide */
2383 kal_int16 tx_power; /* Averaged TX power meas result */
2384} fdd_cphy_tx_power_result_ind_struct;
2385
2386typedef struct _fdd_cphy_specific_cell_search_ind_struct
2387{
2388 LOCAL_PARA_HDR
2389
2390 kal_bool success; /* Indicate if search success */
2391 FDD_measured_cell_T measured_cell; /* The found(1) cell */
2392} fdd_cphy_specific_cell_search_ind_struct;
2393
2394typedef struct _fdd_cphy_specific_cell_search_stop_ind_struct
2395{
2396 LOCAL_PARA_HDR
2397} fdd_cphy_specific_cell_search_stop_ind_struct;
2398
2399typedef struct _fdd_cphy_reset_cnf_struct
2400{
2401 LOCAL_PARA_HDR
2402
2403 kal_bool success; /* Indicate whether the L1 initialization sucess or fail */
2404} fdd_cphy_reset_cnf_struct;
2405
2406
2407typedef struct _fdd_cphy_rf_on_cnf_struct
2408{
2409 LOCAL_PARA_HDR
2410} fdd_cphy_rf_on_cnf_struct;
2411
2412typedef struct _fdd_cphy_rf_off_cnf_struct
2413{
2414 LOCAL_PARA_HDR
2415} fdd_cphy_rf_off_cnf_struct;
2416
2417typedef struct _fdd_cphy_set_active_rat_cnf_struct
2418{
2419 LOCAL_PARA_HDR
2420} fdd_cphy_set_active_rat_cnf_struct;
2421
2422
2423typedef struct _fdd_cphy_msg_container_cnf_struct
2424{
2425 LOCAL_PARA_HDR
2426} fdd_cphy_msg_container_cnf_struct;
2427
2428typedef struct _fdd_cphy_msg_container_ind_struct
2429{
2430 LOCAL_PARA_HDR
2431
2432 kal_bool success_flag; /* Indicate if configure success
2433 For current L1, it always returns true.
2434 */
2435 kal_bool pending_tgps; /* Indicate if there is any pending TGPS.
2436 Only sent when there is any channel to be released.
2437 */
2438 FDD_msg_container_error_E error_cause; /* Error cause of message container.
2439 */
2440} fdd_cphy_msg_container_ind_struct;
2441
2442typedef struct _fdd_cphy_abort_cnf_struct
2443{
2444 LOCAL_PARA_HDR
2445
2446 kal_bool success; /* Indicate if abort request success
2447 TRUE : L1 will back to the old channel configure.
2448 FALSE : L1 will go forward to the new channel configure.
2449 */
2450} fdd_cphy_abort_cnf_struct;
2451
2452typedef struct _fdd_cphy_tx_status_ind_struct
2453{
2454 LOCAL_PARA_HDR
2455
2456 kal_bool is_tx_allow; /* the current TX status
2457 TRUE : Currentlly, TX is available in UL1.
2458 FALSE : Currentlly, TX is not available in UL1.
2459 */
2460} fdd_cphy_tx_status_ind_struct;
2461
2462/* 20080131: By MEME's request, define new I/F for event 6E. */
2463typedef struct _fdd_cphy_rssi_exceed_range_ind_struct
2464{
2465 LOCAL_PARA_HDR
2466
2467 kal_int16 tx_power; /* Averaged TX power meas result */
2468} fdd_cphy_rssi_exceed_range_ind_struct;
2469
2470typedef struct _fdd_cphy_duplex_mode_change_req_struct
2471{
2472 LOCAL_PARA_HDR
2473
2474 FDD_duplex_mode_info_T duplex_mode_info;
2475} fdd_cphy_duplex_mode_change_req_struct;
2476
2477typedef struct _fdd_cphy_duplex_mode_change_cnf_struct
2478{
2479 LOCAL_PARA_HDR
2480
2481 kal_bool result;
2482} fdd_cphy_duplex_mode_change_cnf_struct;
2483
2484/* Suspend and resume Smart Paging feature */
2485
2486typedef struct _fdd_cphy_smart_paging_reconfig_req_struct
2487{
2488 LOCAL_PARA_HDR
2489 kal_bool smartpaging_enabled;
2490} fdd_cphy_smart_paging_reconfig_req_struct;
2491
2492/*****************************************************************************
2493 request for phy
2494*****************************************************************************/
2495typedef struct _FDD_phy_rach_data_req_struct
2496{
2497 LOCAL_PARA_HDR
2498
2499 kal_uint16 tfci; /* TFCI. 0 ~ 1023 */
2500 FDD_ulTrchData TrchInfo; /* UL TrCH information */
2501 kal_uint16 size_data; /* This parameter represents the number of bytes of the buffer. This number will be equal to the size of allocated buffer plus 4 bytes. */
2502 kal_uint8 *data[FDD_MAX_UL_TB]; /* data for each TB. PS shoul allocate the buffer */
2503} fdd_phy_rach_data_req_struct;
2504
2505typedef struct _FDD_phy_access_req_struct
2506{
2507 LOCAL_PARA_HDR
2508
2509 kal_bool retry; /* Indicate if this is a retry request
2510 TRUE : RACH TX failed in last acces procedure.
2511 L1 will use the same RACH data an ASC in previous access procedure.
2512 */
2513 kal_uint8 asc; /* ASC. 0 ~ 7 */
2514 kal_int16 ul_interference; /* UL interference in SIB7. -110 ~ 70dBm */
2515#ifdef __UMTS_R8__
2516 kal_bool is_CEDCH_CCCH; /* [R8] True: Common E-DCH transmission is for CCCH. FALSE for DTCH/DCCH */
2517#endif /* __UMTS_R8__ */
2518} fdd_phy_access_req_struct;
2519
2520
2521/* confirm & indication for phy */
2522typedef struct _FDD_phy_pch_setup_ind_struct
2523{
2524 LOCAL_PARA_HDR
2525} fdd_phy_pch_setup_ind_struct;
2526
2527typedef struct _FDD_phy_pch_modify_ind_struct
2528{
2529 LOCAL_PARA_HDR
2530} fdd_phy_pch_modify_ind_struct;
2531
2532typedef struct _FDD_phy_pch_release_ind_struct
2533{
2534 LOCAL_PARA_HDR
2535} fdd_phy_pch_release_ind_struct;
2536
2537typedef struct _FDD_phy_fach_setup_ind_struct
2538{
2539 LOCAL_PARA_HDR
2540} fdd_phy_fach_setup_ind_struct;
2541
2542typedef struct _FDD_phy_fach_modify_ind_struct
2543{
2544 LOCAL_PARA_HDR
2545} fdd_phy_fach_modify_ind_struct;
2546
2547typedef struct _FDD_phy_fach_release_ind_struct
2548{
2549 LOCAL_PARA_HDR
2550} fdd_phy_fach_release_ind_struct;
2551
2552typedef struct _FDD_phy_rach_setup_ind_struct
2553{
2554 LOCAL_PARA_HDR
2555} fdd_phy_rach_setup_ind_struct;
2556
2557typedef struct _FDD_phy_rach_release_ind_struct
2558{
2559 LOCAL_PARA_HDR
2560} fdd_phy_rach_release_ind_struct;
2561
2562typedef struct _FDD_phy_dch_setup_ind_struct
2563{
2564 LOCAL_PARA_HDR
2565
2566 kal_uint8 direction; /* Indicate UL or DL is being setup
2567 0 : DL DCH
2568 1 : UL DCH
2569 2 : FDPCH
2570 */
2571 kal_uint16 sfn; /* The LST value of the frame when DL DCH is setup.*/
2572 kal_bool syncA_procedure_needed ; /* TRUE: Indicate syncA procedure is performed.*/
2573} fdd_phy_dch_setup_ind_struct;
2574
2575typedef struct _FDD_phy_dch_modify_ind_struct
2576{
2577 LOCAL_PARA_HDR
2578
2579 kal_uint8 direction; /* Indicate UL or DL is being setup
2580 0 : DL_DCH
2581 1 : UL_DCH
2582 2 : FDPCH
2583 */
2584} fdd_phy_dch_modify_ind_struct;
2585
2586typedef struct _FDD_phy_dch_release_ind_struct
2587{
2588 LOCAL_PARA_HDR
2589
2590 kal_uint8 direction; /* Indicate UL or DL is being setup
2591 0 : DL DCH
2592 1 : UL DCH
2593 2 : FDPCH
2594 */
2595 kal_uint16 sfn; /* The LST value of the frame when DL DCH is setup.*/
2596} fdd_phy_dch_release_ind_struct;
2597
2598typedef struct _FDD_phy_config_abort_ind_struct
2599{
2600 LOCAL_PARA_HDR
2601
2602 kal_bool success; /* Indicate if abort request success
2603 TRUE : L1 will back to old channel configure
2604 FALSE : L1 will go forward to new channel configure
2605 */
2606} fdd_phy_config_abort_ind_struct;
2607
2608typedef struct _FDD_phy_dl_init_sync_ind_struct
2609{
2610 LOCAL_PARA_HDR
2611} fdd_phy_dl_init_sync_ind_struct;
2612
2613typedef struct _FDD_phy_bch_data_ind_struct
2614{
2615 LOCAL_PARA_HDR
2616
2617 kal_uint8 *data; /* PS2 Excel request to add a "data" field in
2618 fdd_phy_bch_data_ind_struct. This field is only for
2619 protocol and not used by UL1 */
2620 kal_bool no_path; /* True: L1 could not find the cell*/
2621 kal_int32 tm; /* LST of the cell boundary. 0 ~ 38400*8-1 */
2622 kal_int16 off; /* Frame # offset to LST. -1 ~ 4095. -1 means unknown */
2623 kal_uint16 dl_freq; /* DL UARFCN */
2624 kal_uint16 psc; /* Primary scrambling code */
2625 kal_uint8 crc_status; /* CRC result.
2626 0 : CRC error
2627 1 : CRC ok
2628 2 : no CRC */
2629 kal_uint16 num_data; /* Length of the valid byte in data. 0 ~ FDD_MAX_DL_DATA */
2630 /* Data is contained in peer buffer */
2631 kal_bool measurement_valid;
2632 kal_int16 rssi;
2633 kal_int16 rscp;
2634 kal_int16 ec_no;
2635 kal_bool standby_no_gap; /* True: L1 has no enough gap time for SIB reception */
2636
2637#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
2638 FDD_uas_gemini_conflict_cause_enum conflict_cause;
2639 kal_uint16 peer_priority_index;
2640#endif
2641} fdd_phy_bch_data_ind_struct;
2642
2643typedef struct _FDD_phy_data_ind_struct
2644{
2645 LOCAL_PARA_HDR
2646
2647 FDD_cctrch_type_E dl_cctrch; /* PCH, FACH or DCH CCTrCH */
2648 kal_uint8 rx_fn; /* FN of the last frame in the TTI that was received */
2649 kal_uint16 rx_sfn;
2650 kal_uint16 dl_freq; /* DL UARFCN */
2651 kal_uint16 psc; /* Primary scrambling code */
2652 kal_uint8 num_trch; /* # of trch */
2653 FDD_dlTrchData TrchInfo[FDD_MAX_TRCH_NUM]; /* DL TrCH Info */
2654 kal_uint32 crc; /* CRC result for each TB
2655 1 : CRC ok.
2656 0 : CRC error.
2657 */
2658 //kal_uint32 crc_bits[FDD_MAX_DL_TB]; /* CRC bits of each TB. (Used for Loop back mode) */
2659 kal_uint16 num_data; /* Length of the valid byte in data. 0 ~ FDD_MAX_DL_DATA */
2660 kal_uint8 *data; /* TB data pointer on share memory. This buffer is allocated by UL1, and freed by UMAC. */
2661
2662 kal_uint8 num_tb; /* num of TB. UMAC will put this value in the first byte of data allocated from ADM,
2663 and the real data part starts at byte 4.*/
2664
2665 kal_uint32 raw_crc; /* Unmodified CRC for speech decoder */
2666 kal_uint32 s_value[FDD_MAX_TRCH_NUM]; /* Viterbi decoder output S value for speech decoder */
2667
2668 /* UL1A provides debugging info. for VM in DCH dldata*/
2669 kal_int16 tpc_SIR_lta; // For recording into speech VM
2670 kal_int16 dpdch_SIR_lta; // For recording into speech VM
2671 kal_int16 TFCI_max_corr; // For recording into speech VM
2672
2673#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
2674 FDD_uas_gemini_conflict_cause_enum conflict_cause; /* This field is only used for Gemini. It indicates the channel conflict cause with peer channel.
2675 It is only meaningful for PCH and CTCH. */
2676 kal_uint8 rx_suspend; /* This field is only used for Gemini 2.0.It is a bitmap to indicate if some TrCH is conflicted with SIM2 gap.
2677 The bit is set to ¡§1¡¨ only when the TrCH TTI ends in this frame and SIM2 gap exists in this TTI.
2678 LSB bit is mapped to trchInfo[0]. */
2679#endif /* __GEMINI__ && __UMTS_RAT__ */
2680
2681#ifdef __SMART_PAGING_3G_FDD__
2682 kal_int8 pi_repeat_cycle;/* -1:invalid, -2:retransmission with CRC pass, 1~20:valid pi_repeat_cyle */
2683#endif
2684
2685 kal_bool is_EBD_CRC_workaround; /*MT6290E1: indicate to MAC if additional CRC append in this data ind due to RXBRP workaround*/
2686
2687 /* serving cell information for speech debug. */
2688 /* These values are valid only when DCH state and RL exists, otherwise, the value will be "0". */
2689 kal_uint8 RSSI;
2690 kal_uint8 RSCP;
2691 kal_uint8 ECIO;
2692 kal_uint8 HHO_SHO;
2693
2694} fdd_phy_data_ind_struct;
2695
2696typedef struct _fdd_phy_data_buffer_free_ind_struct
2697{
2698 LOCAL_PARA_HDR
2699
2700 kal_uint8 *data;
2701} fdd_phy_data_buffer_free_ind_struct;
2702
2703typedef struct _FDD_phy_access_ind_struct
2704{
2705 LOCAL_PARA_HDR
2706
2707 FDD_access_status_E access_status; /* The result of RACH access */
2708} fdd_phy_access_ind_struct;
2709
2710
2711/* __HSDPA_SUPPORT__ */
2712typedef struct _FDD_phy_hsdsch_data_ind_struct
2713{
2714 LOCAL_PARA_HDR
2715
2716 kal_uint8 cfn; /* [Range]: 0-255 */
2717 kal_uint8 subframe; /* indicate subf-number of this data_ind */
2718 kal_uint8 mac_event; /* bit 0: MAC-hs setup, */
2719 /* bit 1: MAC-hs release, */
2720 /* bit 2: MAC-hs modify */
2721 /* bit 3: MAC-(e)hs reset */
2722 kal_uint8 cell_bitmap;
2723 FDD_hsdsch_data_T hsdsch_data[FDD_MAX_SUPPORT_CELL];
2724
2725} fdd_phy_hsdsch_data_ind_struct;
2726
2727
2728
2729#ifdef __UMTS_R8__
2730typedef struct _FDD_phy_cedch_setup_ind_struct
2731{
2732 LOCAL_PARA_HDR
2733} fdd_phy_cedch_setup_ind_struct;
2734
2735typedef struct _FDD_phy_cedch_modify_ind_struct
2736{
2737 LOCAL_PARA_HDR
2738} fdd_phy_cedch_modify_ind_struct;
2739
2740typedef struct _FDD_phy_cedch_release_ind_struct
2741{
2742 LOCAL_PARA_HDR
2743} fdd_phy_cedch_release_ind_struct;
2744
2745typedef struct _FDD_phy_cedch_termination_req_struct
2746{
2747 LOCAL_PARA_HDR
2748} fdd_phy_cedch_termination_req_struct;
2749
2750typedef struct _FDD_phy_cedch_termination_ind_struct
2751{
2752 LOCAL_PARA_HDR
2753
2754 kal_bool stopped_by_ul1; /* CEDCH is terminated due to radio link failure */
2755} fdd_phy_cedch_termination_ind_struct;
2756#endif /* __UMTS_R8__ */
2757
2758/* U3G */
2759typedef struct _FDD_ul1_l1sp_update_dch_info_ind_struct
2760{
2761 LOCAL_PARA_HDR
2762
2763 /* SP3G_UpdateL1InFo */
2764 /* called by L1A to update DCH on/off and TX in/off(DCH UL on/off) */
2765 /* bitmap indicates DCH setup type, and value indicates the status */
2766 /* bitmap = 0: DCH on/off (1: on, 0: off) */
2767 /* bitmap = 1: DCH UL on/off (1: on, 0: off) */
2768 /* bitmap = 2: indicate RLF status (1: indicate RLF, 0: reset RLF) */
2769 kal_uint8 bitmap;
2770 kal_uint8 value;
2771} fdd_ul1_l1sp_update_dch_info_ind_struct;
2772/* U3G */
2773
2774
2775#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
2776
2777typedef struct _FDD_rsvas_ul1_suspend_req_struct
2778{
2779 LOCAL_PARA_HDR
2780} fdd_rsvas_ul1_suspend_req_struct;
2781
2782typedef struct _FDD_rsvas_ul1_suspend_cnf_struct
2783{
2784 LOCAL_PARA_HDR
2785} fdd_rsvas_ul1_suspend_cnf_struct;
2786
2787typedef struct _FDD_rsvas_ul1_resume_req_struct
2788{
2789 LOCAL_PARA_HDR
2790} fdd_rsvas_ul1_resume_req_struct;
2791#endif
2792
2793#if defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__) || defined(__L1_GPS_REF_TIME_SUPPORT__)
2794/* __GPS_FRAME_SYNC_SUPPORT__ */
2795/* CSCE uses this primitive to inform UL1 that OOS occurs when AGPS feature turns on. */
2796typedef struct _fdd_cphy_out_of_service_req_struct
2797{
2798 LOCAL_PARA_HDR
2799} fdd_cphy_out_of_service_req_struct;
2800#endif
2801
2802typedef struct _FDD_user_wakeup_3g_lock_struct
2803{
2804 LOCAL_PARA_HDR
2805
2806 kal_uint8 user_sm_handle;
2807} FDD_user_wakeup_3g_lock_struct;
2808
2809/* SEQUENCE OF MCC */
2810typedef struct ul1_mcc
2811{
2812 kal_uint8 numElements;
2813
2814 kal_uint8 element[3];
2815}
2816ul1_mcc;
2817
2818/* SEQUENCE OF MNC */
2819typedef struct ul1_mnc
2820{
2821 kal_uint8 numElements;
2822
2823 kal_uint8 element[3];
2824}
2825ul1_mnc;
2826
2827
2828/* SEQUENCE PLMN-Identity */
2829typedef struct ul1_plmn_identity
2830{
2831 ul1_mcc mcc; /* MANDATORY */
2832 ul1_mnc mnc; /* MANDATORY */
2833}
2834ul1_plmn_identity;
2835/*****************************************************************************
2836* Functions exported to RRC
2837*****************************************************************************/
2838void UL1_Lcore_Compare_CFN_SFN( UL1_SIM_INDEX_E sim_idx, kal_int16 cfn, kal_int16 sfn, FDD_tgps_time_relationship_E *cfn_sfn_relation );
2839void UL1D_PS_SessionStarted( kal_bool If_PS_SessionStarted );
2840kal_bool UL1D_FDD_HSDPA_Phy_DualCarrier_Status( void *data );
2841
2842
2843
2844/*------------------- Function prototype -----------------------------*/
2845/* L1 provides this function to other entities to get current CFN & SFN */
2846/* CFN : -1 ~ 255. 0 ~ 255 if UE in DCH/FACH mode otherwise -1 */
2847/* SFN : -1 ~ 4095. 0 ~ 4095 for the LST frame number. -1 for an invalid value. */
2848void UL1_GetCurrentTime( UL1_SIM_INDEX_E sim_index, kal_int16 *cfn, kal_int16 *sfn );
2849
2850#if 0
2851/* under construction !*/
2852/* under construction !*/
2853/* under construction !*/
2854/* under construction !*/
2855/* under construction !*/
2856/* under construction !*/
2857/* under construction !*/
2858/* under construction !*/
2859/* under construction !*/
2860/* under construction !*/
2861/* under construction !*/
2862/* under construction !*/
2863/* under construction !*/
2864/* under construction !*/
2865/* under construction !*/
2866/* under construction !*/
2867/* under construction !*/
2868/* under construction !*/
2869/* under construction !*/
2870/* under construction !*/
2871/* under construction !*/
2872/* under construction !*/
2873/* under construction !*/
2874/* under construction !*/
2875/* under construction !*/
2876/* under construction !*/
2877/* under construction !*/
2878/* under construction !*/
2879/* under construction !*/
2880/* under construction !*/
2881/* under construction !*/
2882/* under construction !*/
2883/* under construction !*/
2884/* under construction !*/
2885/* under construction !*/
2886/* under construction !*/
2887/* under construction !*/
2888/* under construction !*/
2889/* under construction !*/
2890/* under construction !*/
2891/* under construction !*/
2892/* under construction !*/
2893/* under construction !*/
2894/* under construction !*/
2895/* under construction !*/
2896/* under construction !*/
2897/* under construction !*/
2898/* under construction !*/
2899#endif
2900/*****************************************************************************
2901* Function: UL1_Compare_CFN_SFN
2902*
2903* Parameters: kal_int16 cfn ; cfn which RRCE wants to compare, range:0~255
2904* kal_int16 sfn ; sfn which RRCE wants to compare, range:0~4095
2905* FDD_tgps_time_relationship_E* cfn_sfn_relation ; FDD_TGPS_AFTER means that expanded CFN is after the specified sfn
2906* ; FDD_TGPS_EQUAL means that expanded CFN is equal to the specified sfn
2907* ; FDD_TGPS_BEFORE means that expanded CFN is equal to the specified sfn
2908* Returns: void
2909*
2910* Description:
2911* The function is to expand the specified CFN to the range 0~4095 and compare the expanded CFN to the specified SFN
2912*****************************************************************************/
2913void UL1_Compare_CFN_SFN( kal_int16 cfn, kal_int16 sfn, FDD_tgps_time_relationship_E *cfn_sfn_relation );
2914
2915
2916/*****************************************************************************
2917* Function: UL1_CEDCH_Check_Started
2918*
2919* Parameters: Non
2920* Returns: If the return value is KAL_TRUE, UL1 has the common EDCH resource, otherwise it's KAL_FALSE.
2921*
2922* Description:
2923* This is a callback function and provide to indicate the common edch status for upper layer.
2924* The resolution is frame base because this function is provided by UL1C.
2925*****************************************************************************/
2926#ifdef __UMTS_R8__
2927#define UL1_Lcore_CEDCH_Check_Started UL1_CEDCH_Check_Started
2928kal_bool UL1_CEDCH_Check_Started( UL1_SIM_INDEX_E sim_index );
2929#endif /* __UMTS_R8__ */
2930
2931/*****************************************************************************
2932* Functions exported to MEME
2933*****************************************************************************/
2934#if 0
2935/* under construction !*/
2936/* under construction !*/
2937/* under construction !*/
2938/* under construction !*/
2939/* under construction !*/
2940/* under construction !*/
2941/* under construction !*/
2942/* under construction !*/
2943/* under construction !*/
2944/* under construction !*/
2945/* under construction !*/
2946/* under construction !*/
2947/* under construction !*/
2948/* under construction !*/
2949#endif
2950/*****************************************************************************
2951* Functions exported to UMAC
2952*****************************************************************************/
2953/*****************************************************************************
2954* Function: UL1_FreePhyDataIndBuffer
2955*
2956* Parameters: kal_uint8* data : DL data buffer to be freed
2957*
2958* Returns: void
2959*
2960* Description:
2961* The function is for UMAC to free the data buffer in PHY_DATA_IND
2962*****************************************************************************/
2963void UL1_FreePhyDataIndBuffer( kal_uint8 *data );
2964
2965
2966/**********************************************************************************************************************/
2967/*********************************** UL1 Interface maintained by UMAC (Begin) *************************************/
2968/**********************************************************************************************************************/
2969/*UMAC*/
2970extern kal_bool FDD_ul_dpch_cctrch(
2971 /*UMAC*/ kal_uint8 cfn,
2972 /*UMAC*/ kal_bool availabe,
2973 /*UMAC*/ kal_bool reconfig_status, /*For notifying DPCH modification*/
2974 /*UMAC*/ kal_uint16 *tfci,
2975 /*UMAC*/ kal_uint8 *num_trch,
2976 /*UMAC*/ FDD_ulTrchData *TrchInfo,
2977 /*UMAC*/ kal_uint16 *size_data,
2978 /*UMAC*/ kal_uint8 **data );
2979/*UMAC*/
2980/*UMAC*/
2981extern void FDD_ul_dpch_cctrch_task(
2982 /*UMAC*/ kal_uint8 cfn,
2983 /*UMAC*/ kal_bool availabe,
2984 /*UMAC*/ kal_bool reconfig_status /*For notifying DPCH modification*/ );
2985/*UMAC*/
2986/*UMAC*/
2987extern kal_bool FDD_ul_dpch_cctrch_HISR(
2988 /*UMAC*/ kal_uint8 cfn,
2989 /*UMAC*/ kal_bool availabe,
2990 /*UMAC*/ kal_bool reconfig_status, /*For notifying DPCH modification*/
2991 /*UMAC*/ kal_uint16 *tfci,
2992 /*UMAC*/ kal_uint8 *num_trch,
2993 /*UMAC*/ FDD_ulTrchData *TrchInfo,
2994 /*UMAC*/ kal_uint16 *size_data,
2995 /*UMAC*/ kal_uint8 **data );
2996/*UMAC*/
2997/*UMAC*/
2998extern void FDD_ul_inform_MAC( kal_uint32 data );
2999/*UMAC*/
3000/*UMAC*/
3001extern void FDD_ul_dpch_power( kal_uint8 cfn, kal_uint8 tfc_status[FDD_MAX_UL_TFC] );
3002/*UMAC*/
3003extern void FDD_mac_hs_get_variable_pdu_buffer( kal_uint8 **buffer_ptr, kal_uint32 num );
3004#ifdef __HSDSCH_HARQ_OFF__
3005/*UMAC*/extern void FDD_mac_hs_free_variable_pdu_buffer( kal_uint8 **buffer_ptr, kal_uint32 num ); // for HARQ off
3006#endif
3007/*UMAC*/extern void FDD_mac_hs_get_pdu_buffer( kal_uint8 **buffer_ptr );
3008/*UMAC*/
3009/*UMAC*/
3010extern FDD_uldch_data_ind_T *FDD_UMAC_UL_DCH_Tick_LISR( UL1_SIM_INDEX_E sim_idx, FDD_uldch_data_req_T *uldch_data_req );
3011/*UMAC*/
3012extern FDD_etfc_eval_info_ind_T *FDD_umac_e_dch_evaluate_tx_process_LISR( UL1_SIM_INDEX_E sim_idx, FDD_etfc_eval_info_req_T *etfc_eval_input );
3013/*UMAC*/
3014extern kal_bool FDD_umac_e_dch_is_tx_permitted_LISR( UL1_SIM_INDEX_E sim_idx, kal_uint8 *supported_etfci_bitmap, FDD_edch_scell_E edch_cell, kal_bool *is_sched_data_included );
3015/*UMAC*/
3016extern FDD_edch_data_ind_T *FDD_umac_e_dch_prepare_data_LISR( UL1_SIM_INDEX_E sim_idx, FDD_edch_data_req_T *edch_data_input );
3017/*UMAC*/
3018extern kal_bool FDD_umac_e_dch_get_happy_bit_LISR( UL1_SIM_INDEX_E sim_idx, kal_bool happy[FDD_E_SCELL_TOTAL] );
3019/*UMAC*/
3020extern void FDD_umac_e_dch_post_tx_process_LISR( UL1_SIM_INDEX_E sim_idx );
3021/*UMAC*/
3022extern void FDD_umac_e_dch_update_ref_etpr_LISR( UL1_SIM_INDEX_E sim_idx, kal_bool tx_enable[FDD_E_SCELL_TOTAL], kal_uint32 ref_etpr_x225[FDD_E_SCELL_TOTAL] );
3023/*UMAC*/
3024extern void FDD_try_to_trigger_CSR_STATUS_IND_LISR( UL1_SIM_INDEX_E sim_idx, kal_uint8 cfn );
3025/*UMAC*/
3026extern kal_bool FDD_umac_e_dch_predict_tx_process_LISR( UL1_SIM_INDEX_E sim_idx, FDD_etfc_eval_lpr_info_req_T *info );
3027/*UMAC*/
3028extern void FDD_ul_inform_Edch_MAC( void *data );
3029/*UMAC*/
3030extern void FDD_send_CSR_STATUS_IND( kal_uint32 data );
3031/*UMAC*/
3032/*UMAC*/
3033#define FDD_UMAC_UL_DCH_Tick(sim_idx,uldch_data_req) FDD_UMAC_UL_DCH_Tick_LISR(sim_idx,uldch_data_req)
3034/*UMAC*/#define FDD_umac_e_dch_tick_1( sim_idx, etfc_eval_input ) FDD_umac_e_dch_evaluate_tx_process_LISR( sim_idx, etfc_eval_input )
3035/*UMAC*/#define FDD_umac_e_dch_is_tx_permitted( sim_idx, supported_etfci_bitmap, edch_cell, is_sched_data_included ) FDD_umac_e_dch_is_tx_permitted_LISR( sim_idx, supported_etfci_bitmap, edch_cell, is_sched_data_included )
3036/*UMAC*/#define FDD_umac_e_dch_tick_2( sim_idx, edch_data_input ) FDD_umac_e_dch_prepare_data_LISR( sim_idx, edch_data_input )
3037/*UMAC*/#define FDD_umac_e_dch_get_happy_bit( sim_idx, happy ) FDD_umac_e_dch_get_happy_bit_LISR( sim_idx, happy )
3038/*UMAC*/#define FDD_umac_e_dch_tick_3( sim_idx, tx_enable, ref_etpr_x225 ) FDD_umac_e_dch_post_tx_process_LISR( sim_idx )
3039/*UMAC*/#define FDD_umac_e_dch_tick_4( sim_idx ) {} //FDD_umac_e_dch_tick_4_LISR(sim_idx)
3040/*UMAC*/#define FDD_umac_e_dch_update_ref_etpr( sim_idx, tx_enable, ref_etpr_x225 ) FDD_umac_e_dch_update_ref_etpr_LISR( sim_idx, tx_enable, ref_etpr_x225 )
3041/*UMAC*/#define FDD_umac_e_dch_tick_5( sim_idx, info ) FDD_umac_e_dch_predict_tx_process_LISR( sim_idx, info )
3042/*UMAC*/
3043/*UMAC*//*========== UMAC END TX STRUCT (BEGIN) ==========*/
3044/*UMAC*/typedef struct _FDD_phy_end_dch_tx_ind_struct
3045/*UMAC*/
3046{
3047 /*UMAC*/ LOCAL_PARA_HDR
3048 /*UMAC*/ kal_uint8 cfn;
3049 /*UMAC*/
3050 /*UMAC*/
3051} fdd_phy_end_dch_tx_ind_struct;
3052/*UMAC*/
3053/*UMAC*//* __HSUPA_SUPPORT__ */
3054/*UMAC*/
3055typedef struct _FDD_phy_end_edch_tx_ind_struct
3056/*UMAC*/
3057{
3058 /*UMAC*/ LOCAL_PARA_HDR
3059 /*UMAC*/ kal_uint8 cfn;
3060 /*UMAC*/
3061 kal_uint8 subframe;
3062 /*UMAC*/
3063 kal_uint8 harq_id;
3064 /*UMAC*/
3065 kal_uint8 mode;
3066 /*UMAC*/
3067} fdd_phy_end_edch_tx_ind_struct;
3068/*UMAC*//*========== UMAC END TX STRUCT (END) ==========*/
3069/*UMAC*//*========== UMAC UT SIMULATE MESSAGE ==========*/
3070/*UMAC*///#ifdef __MNT_UT_UMAC_ALONE_WITHOUT_L1__ /* UMAC UT */
3071/*UMAC*/
3072typedef struct
3073/*UMAC*/
3074{
3075 /*UMAC*/ LOCAL_PARA_HDR
3076 /*UMAC*/ kal_uint8 cfn;
3077 /*UMAC*/
3078 kal_bool availabe;
3079 /*UMAC*/
3080 kal_bool reconfig_status;
3081 /*UMAC*/
3082} fdd_phy_simulate_dch_ul_cctrch_task_struct;
3083/*UMAC*/
3084/*UMAC*/
3085typedef struct
3086/*UMAC*/
3087{
3088 /*UMAC*/ LOCAL_PARA_HDR
3089 /*UMAC*/ kal_uint8 cfn;
3090 /*UMAC*/
3091 kal_uint8 ul_mac_event; /* bit 0: UL DCH setup, */
3092 /*UMAC*/ /* bit 1: UL DCH release, */
3093 /*UMAC*/ /* bit 2: UL DCH modify */
3094 /*UMAC*/
3095 kal_uint8 dpdch_num;
3096 /*UMAC*/
3097 kal_bool restartSRB; /* set true when PCP_Finish (not align max TTI) */
3098 /*UMAC*/
3099 kal_bool tx_enable; /* set true if TX data could be sent (min TTI) */
3100 /*UMAC*/
3101 kal_bool tx_suspend;
3102 /*UMAC*/
3103 kal_uint8 tfc_status[FDD_MAX_UL_TFC];
3104 /*UMAC*/
3105} fdd_phy_simulate_dch_ul_cctrch_lisr_struct;
3106/*UMAC*/
3107/*UMAC*/
3108typedef struct
3109/*UMAC*/
3110{
3111 /*UMAC*/ LOCAL_PARA_HDR
3112 /*UMAC*/ kal_uint8 cfn;
3113 /*UMAC*/
3114 kal_bool availabe;
3115 /*UMAC*/
3116 kal_bool reconfig_status;
3117 /*UMAC*/ /* Use structure instead of pointer to simulate this */
3118 /*UMAC*/
3119 kal_uint16 tfci;
3120 /*UMAC*/
3121 kal_uint8 num_trch;
3122 /*UMAC*/
3123 FDD_ulTrchData TrchInfo[FDD_MAX_TRCH_NUM];
3124 /*UMAC*/
3125 kal_uint16 size_data[FDD_MAX_TRCH_NUM];
3126 /*UMAC*/
3127 kal_uint8 *data[FDD_MAX_UL_TB];
3128 /*UMAC*/
3129} fdd_phy_simulate_dch_ul_cctrch_hisr_struct;
3130/*UMAC*/
3131/*UMAC*/
3132typedef struct
3133/*UMAC*/
3134{
3135 /*UMAC*/ LOCAL_PARA_HDR
3136 /*UMAC*/ kal_uint8 cfn;
3137 /*UMAC*/
3138 kal_uint8 num_trch;
3139 /*UMAC*/
3140 FDD_ulTrchData trchInfo[FDD_MAX_TRCH_NUM];
3141 /*UMAC*/
3142 kal_uint16 tfci;
3143 /*UMAC*/
3144 kal_uint16 num_data[FDD_MAX_TRCH_NUM];
3145 /*UMAC*/
3146 kal_uint8 *data[FDD_MAX_TRCH_NUM];
3147 /*UMAC*/
3148 /*UMAC*/
3149#ifdef UNIT_TEST
3150 /*UMAC*/ void *addr;
3151 /*UMAC*/
3152#endif /* UNIT_TEST */
3153 /*UMAC*/
3154} fdd_phy_simulate_dch_ul_cctrch_lisr_rsp_struct;
3155/*UMAC*/
3156/*UMAC*/
3157typedef struct
3158/*UMAC*/
3159{
3160 /*UMAC*/ LOCAL_PARA_HDR
3161 /*UMAC*/ kal_uint8 cfn;
3162 /*UMAC*/
3163 kal_bool availabe;
3164 /*UMAC*/
3165 kal_bool reconfig_status;
3166 /*UMAC*/ /* Use structure instead of pointer to simulate this */
3167 /*UMAC*/
3168 kal_uint16 tfci;
3169 /*UMAC*/
3170 kal_uint8 num_trch;
3171 /*UMAC*/
3172 FDD_ulTrchData TrchInfo[FDD_MAX_TRCH_NUM];
3173 /*UMAC*/
3174 kal_uint16 size_data[FDD_MAX_TRCH_NUM];
3175 /*UMAC*/
3176 kal_uint8 *data[FDD_MAX_UL_TB];
3177 /*UMAC*/
3178} fdd_phy_simulate_dch_ul_cctrch_hisr_rsp_struct;
3179/*UMAC*/
3180/*UMAC*/
3181typedef struct
3182/*UMAC*/
3183{
3184 /*UMAC*/ LOCAL_PARA_HDR
3185 /*UMAC*/ kal_uint8 cfn;
3186 /*UMAC*/
3187 kal_bool availabe;
3188 /*UMAC*/
3189 kal_bool reconfig_status;
3190 /*UMAC*/ /* Use structure instead of pointer to simulate this */
3191 /*UMAC*/
3192 kal_uint16 tfci;
3193 /*UMAC*/
3194 kal_uint8 num_trch;
3195 /*UMAC*/
3196 FDD_ulTrchData TrchInfo[FDD_MAX_TRCH_NUM];
3197 /*UMAC*/
3198 kal_uint16 size_data[FDD_MAX_TRCH_NUM];
3199 /*UMAC*/
3200 kal_uint8 *data[FDD_MAX_UL_TB];
3201 /*UMAC*/
3202} fdd_phy_simulate_dch_ul_callback_cctrch_rsp_struct;
3203/*UMAC*/
3204/*UMAC*/
3205/*UMAC*/
3206/*UMAC*/
3207typedef struct
3208/*UMAC*/
3209{
3210 /*UMAC*/ LOCAL_PARA_HDR
3211 /*UMAC*/ kal_uint8 cfn;
3212 /*UMAC*/
3213 kal_uint8 tfc_status[FDD_MAX_UL_TFC];
3214 /*UMAC*/
3215} fdd_phy_simulate_dch_ul_callback_power_struct;
3216/*UMAC*/
3217/*UMAC*/
3218typedef struct /* Old DCH Callback */
3219/*UMAC*/
3220{
3221 /*UMAC*/ LOCAL_PARA_HDR
3222 /*UMAC*/ kal_uint8 cfn;
3223 /*UMAC*/
3224 kal_bool availabe;
3225 /*UMAC*/
3226 kal_bool reconfig_status; /*MA only, for notifying DPCH modification*/
3227 /*UMAC*/ /* Use structure instead of pointer to simulate this */
3228 /*UMAC*/
3229 kal_uint16 tfci;
3230 /*UMAC*/
3231 kal_uint8 num_trch;
3232 /*UMAC*/
3233 FDD_ulTrchData TrchInfo[FDD_MAX_TRCH_NUM];
3234 /*UMAC*/
3235 kal_uint16 size_data[FDD_MAX_TRCH_NUM];
3236 /*UMAC*/
3237 kal_uint8 *data[FDD_MAX_UL_TB];
3238 /*UMAC*/
3239} fdd_phy_simulate_dch_ul_callback_cctrch_struct;
3240/*UMAC*/
3241/*UMAC*/
3242/*UMAC*/
3243typedef struct
3244/*UMAC*/
3245{
3246 /*UMAC*/ LOCAL_PARA_HDR
3247 /*UMAC*/ kal_uint8 cfn;
3248 /*UMAC*/
3249 /*UMAC*/
3250} fdd_phy_simulate_end_dch_tx_ind_struct;
3251/*UMAC*/
3252/*UMAC*/
3253/*UMAC*/ /* For MT6291 U3G */
3254/*UMAC*/
3255typedef struct
3256/*UMAC*/
3257{
3258 /*UMAC*/ LOCAL_PARA_HDR
3259 /*UMAC*/ FDD_etfc_eval_info_req_T etfc_eval_info_req;
3260 /*UMAC*/
3261 /*UMAC*/
3262 kal_uint8 sf_of_etfci[8][128 / 2];
3263 /*UMAC*/
3264} fdd_phy_simulate_umac_e_dch_eval_tx_proc_struct;
3265/*UMAC*/
3266/*UMAC*/
3267/*UMAC*/
3268typedef struct
3269/*UMAC*/
3270{
3271 /*UMAC*/ LOCAL_PARA_HDR
3272 /*UMAC*/ FDD_etfc_eval_info_ind_T etfc_eval_info_ind;
3273 /*UMAC*/
3274 kal_uint8 active_process[FDD_E_SCELL_TOTAL]; /* easy to check the result after processing AG command */
3275 /*UMAC*/
3276} fdd_phy_simulate_umac_e_dch_eval_tx_proc_rsp_struct;
3277/*UMAC*/
3278/*UMAC*/
3279/*UMAC*/
3280typedef struct
3281/*UMAC*/
3282{
3283 /*UMAC*/ LOCAL_PARA_HDR
3284 /*UMAC*/ /* MAX_NUM_OF_ETFC = 128 */
3285 /*UMAC*/ kal_uint8 supported_etfci_bitmap[128 / 4];
3286 /*UMAC*/
3287 /*UMAC*/ /* FDD_MAX_NTX1_10MS = (15-8+1), FDD_MAX_ETFC_NUM = 128 */
3288 /*UMAC*/
3289 FDD_edch_scell_E edch_cell;
3290 /*UMAC*/
3291} fdd_phy_simulate_umac_e_dch_is_tx_permit_struct;
3292/*UMAC*/
3293/*UMAC*/
3294/*UMAC*/
3295typedef struct
3296/*UMAC*/
3297{
3298 /*UMAC*/ LOCAL_PARA_HDR
3299 /*UMAC*/ kal_bool is_sched_data_included;
3300 /*UMAC*/
3301 kal_bool tx_enable;
3302 /*UMAC*/
3303} fdd_phy_simulate_umac_e_dch_is_tx_permit_rsp_struct;
3304/*UMAC*/
3305/*UMAC*/
3306/*UMAC*/
3307typedef struct
3308/*UMAC*/
3309{
3310 /*UMAC*/ LOCAL_PARA_HDR
3311 /*UMAC*/ FDD_edch_data_req_T edch_data_req;
3312 /*UMAC*/ /* FDD_MAX_ETFC_NUM = 128 */
3313 /*UMAC*/
3314 kal_uint8 supported_etfci_bitmap[128 / 4];
3315 /*UMAC*/
3316 kal_uint32 FRC_Curr_Time;
3317 /*UMAC*/
3318} fdd_phy_simulate_umac_e_dch_prepare_data_struct;
3319/*UMAC*/
3320/*UMAC*/
3321/*UMAC*/
3322typedef struct
3323/*UMAC*/
3324{
3325 /*UMAC*/ LOCAL_PARA_HDR
3326 /*UMAC*/ FDD_edch_data_ind_T edch_data_ind;
3327 /*UMAC*/
3328 kal_uint8 SI_HLID; /* easy to check result of Highest Priority Logical Channel Identity */
3329 /*UMAC*/
3330 kal_uint32 SI_HLBS; /* easy to check result of Highest priority Logical channel Buffer Status (Bytes) */
3331 /*UMAC*/
3332 kal_uint8 NoOfCoproTBTriggered;
3333 /*UMAC*/
3334} fdd_phy_simulate_umac_e_dch_prepare_data_rsp_struct;
3335/*UMAC*/
3336/*UMAC*/
3337/*UMAC*/
3338typedef struct
3339/*UMAC*/
3340{
3341 /*UMAC*/ LOCAL_PARA_HDR
3342 /*UMAC*/
3343} fdd_phy_simulate_umac_e_dch_get_happy_bit_struct;
3344/*UMAC*/
3345/*UMAC*/
3346/*UMAC*/
3347typedef struct
3348/*UMAC*/
3349{
3350 /*UMAC*/ LOCAL_PARA_HDR
3351 /*UMAC*/ kal_bool happy[FDD_E_SCELL_TOTAL]; /* easy to check result of Highest priority Logical channel Buffer Status (Bytes) */
3352 /*UMAC*/
3353 kal_bool is_tebs_larger_than_0;
3354 /*UMAC*/
3355} fdd_phy_simulate_umac_e_dch_get_happy_bit_rsp_struct;
3356/*UMAC*/
3357/*UMAC*/
3358/*UMAC*/
3359typedef struct
3360/*UMAC*/
3361{
3362 /*UMAC*/ LOCAL_PARA_HDR
3363 /*UMAC*/ kal_uint32 FRC_Curr_Time;
3364 /*UMAC*/
3365} fdd_phy_simulate_umac_e_dch_post_tx_proc_struct;
3366/*UMAC*/
3367/*UMAC*/
3368typedef struct
3369/*UMAC*/
3370{
3371 /*UMAC*/ LOCAL_PARA_HDR
3372 /*UMAC*/ kal_uint8 NoOfCoproTBTriggered;
3373 /*UMAC*/
3374 kal_uint8 NotifyRLCHarqBitmap[FDD_E_SCELL_TOTAL];
3375 /*UMAC*/
3376} fdd_phy_simulate_umac_e_dch_post_tx_proc_rsp_struct;
3377/*UMAC*/
3378/*UMAC*/
3379#ifdef __UMTS_R7__
3380/*UMAC*/typedef struct
3381/*UMAC*/
3382{
3383 /*UMAC*/ LOCAL_PARA_HDR
3384 /*UMAC*/ FDD_etfc_eval_lpr_info_req_T etfc_eval_lpr_info_req;
3385 /*UMAC*/
3386} fdd_phy_simulate_umac_e_dch_predict_tx_struct;
3387/*UMAC*/
3388/*UMAC*/
3389typedef struct
3390/*UMAC*/
3391{
3392 /*UMAC*/ LOCAL_PARA_HDR
3393 /*UMAC*/ kal_bool result;
3394 /*UMAC*/
3395} fdd_phy_simulate_umac_e_dch_predict_tx_rsp_struct;
3396#endif /* __UMTS_R7__*/
3397/*UMAC*/
3398/*UMAC*/
3399/*UMAC*/typedef struct
3400/*UMAC*/
3401{
3402 /*UMAC*/ LOCAL_PARA_HDR
3403 /*UMAC*/ kal_bool tx_enable[FDD_E_SCELL_TOTAL];
3404 /*UMAC*/
3405 kal_uint32 ReferenceEtpr[FDD_E_SCELL_TOTAL];
3406 /*UMAC*/
3407} fdd_phy_simulate_umac_e_dch_update_ref_etpr_struct;
3408/*UMAC*/
3409/*UMAC*/
3410typedef struct
3411/*UMAC*/
3412{
3413 /*UMAC*/ LOCAL_PARA_HDR
3414 /*UMAC*/
3415} fdd_phy_simulate_umac_e_dch_update_ref_etpr_rsp_struct;
3416/*UMAC*/
3417/*UMAC*/
3418/*UMAC*/
3419typedef struct
3420/*UMAC*/
3421{
3422 /*UMAC*/ LOCAL_PARA_HDR
3423 /*UMAC*/ /* MAX_NUM_OF_ETFC = 128 */
3424 /*UMAC*/ kal_uint8 supported_etfci_bitmap[128 / 4];
3425 /*UMAC*/
3426 /*UMAC*/ /* NUM_OF_NTX1_10MS = (15-8+1), MAX_NUM_OF_ETFC = 128 */
3427 /*UMAC*/
3428 kal_uint8 sf_of_etfci[8][128 / 2];
3429 /*UMAC*/
3430} fdd_phy_simulate_umac_e_dch_tx_param_setup_struct;
3431/*UMAC*/
3432/*UMAC*/
3433/*UMAC*/
3434typedef struct
3435/*UMAC*/
3436{
3437 /*UMAC*/ LOCAL_PARA_HDR
3438 /*UMAC*/ kal_uint8 cfn;
3439 /*UMAC*/
3440} fdd_phy_simulate_try_to_trigger_csr_status_ind_struct;
3441/*UMAC*/
3442typedef struct
3443/*UMAC*/
3444{
3445 /*UMAC*/ kal_uint8 ref_count;
3446 /*UMAC*/
3447 kal_uint16 msg_len;
3448 /*UMAC*/
3449 /*UMAC*/
3450 kal_uint8 get_num;
3451 /*UMAC*/
3452} fdd_phy_simulate_umac_get_hs_buffer_struct;
3453/*UMAC*/
3454/*UMAC*/
3455typedef struct
3456/*UMAC*/
3457{
3458 /*UMAC*/ kal_uint8 ref_count;
3459 /*UMAC*/
3460 kal_uint16 msg_len;
3461 /*UMAC*/
3462 /*UMAC*/
3463 kal_uint8 free_num;
3464 /*UMAC*/
3465} fdd_phy_simulate_umac_free_hs_buffer_struct;
3466/*UMAC*/
3467/*UMAC*/
3468typedef struct
3469/*UMAC*/
3470{
3471 /*UMAC*/ LOCAL_PARA_HDR
3472 /*UMAC*/ kal_uint32 NoOfEdchCell;
3473 /*UMAC*/
3474} fdd_phy_simulate_umac_forced_to_send_edch_em_info_struct;
3475/*UMAC*/
3476/*UMAC*/
3477typedef struct
3478/*UMAC*/
3479{
3480 /*UMAC*/ LOCAL_PARA_HDR
3481 /*UMAC*/
3482} fdd_phy_simulate_umac_forced_to_send_hsdsch_em_info_struct;
3483/*UMAC*/
3484/*UMAC*/
3485typedef struct
3486/*UMAC*/
3487{
3488 /*UMAC*/ LOCAL_PARA_HDR
3489 /*UMAC*/ kal_bool b_pch_Crc;
3490 /*UMAC*/
3491 kal_bool b_em_from_logger;
3492 /*UMAC*/
3493} fdd_phy_simulate_umac_setup_pch_em_info_struct;
3494/*UMAC*///#endif /* __MNT_UT_UMAC_ALONE_WITHOUT_L1__ */
3495typedef struct
3496/*UMAC*/
3497{
3498 /*UMAC*/ LOCAL_PARA_HDR
3499 /*UMAC*/ kal_uint32 kpi;
3500 /*UMAC*/
3501} fdd_phy_simulate_umac_forced_to_send_mdmi_mac_em_info_struct;
3502/*UMAC*/
3503/*UMAC*/
3504typedef struct
3505/*UMAC*/
3506{
3507 /*UMAC*/ LOCAL_PARA_HDR
3508 /*UMAC*/ kal_uint32 kpi;
3509 /*UMAC*/ kal_uint8 cfn;
3510 /*UMAC*/ kal_uint8 subframe;
3511 /*UMAC*/ kal_uint8 harq_id;
3512 /*UMAC*/ kal_uint8 dummy;
3513 /*UMAC*/
3514} fdd_phy_simulate_umac_forced_to_send_mdmi_upa_em_info_struct;
3515/*UMAC*/
3516/*UMAC*/
3517typedef struct
3518/*UMAC*/
3519{
3520 /*UMAC*/ LOCAL_PARA_HDR
3521 /*UMAC*/
3522} fdd_phy_simulate_umac_forced_to_send_mdmi_mea_em_info_struct;
3523/*UMAC*/
3524/*UMAC*/
3525/*UMAC*//*========== END UMAC UT SIMULATE MESSAGE ==========*/
3526/*UMAC*/
3527/*UMAC*//*========== UMAC DEBUG MESSAGE ==========*/
3528/*UMAC*/
3529typedef struct
3530/*UMAC*/
3531{
3532 /*UMAC*/ LOCAL_PARA_HDR
3533 /*UMAC*/
3534 /*UMAC*/ FDD_etfc_eval_info_req_T etfc_eval_info_req;
3535 /*UMAC*/
3536 FDD_etfc_eval_info_ind_T etfc_eval_info_ind;
3537 /*UMAC*/
3538 kal_uint8 ServingGrant;
3539 /*UMAC*/
3540 kal_bool old_isNewTransmission;
3541 /*UMAC*/
3542 kal_bool update_isNewTransmission;
3543 /*UMAC*/
3544 /*UMAC*/
3545} FDD_umac_umac_edch_eval_tx_proc_ind_struct;
3546/*UMAC*/
3547/*UMAC*/
3548/*UMAC*/
3549typedef struct
3550/*UMAC*/
3551{
3552 /*UMAC*/ LOCAL_PARA_HDR
3553 /*UMAC*/
3554 /*UMAC*/ FDD_edch_data_ind_T edch_data_ind;
3555 /*UMAC*/
3556 kal_uint8 supported_etfci_bitmap[32];
3557 /*UMAC*/
3558} FDD_umac_umac_edch_prepare_data_ind_struct;
3559/*UMAC*/
3560/*UMAC*/
3561/*UMAC*/
3562typedef struct
3563/*UMAC*/
3564{
3565 /*UMAC*/ LOCAL_PARA_HDR
3566 /*UMAC*/
3567 /*UMAC*/ kal_bool tx_enable[FDD_E_SCELL_TOTAL];
3568 /*UMAC*/
3569 kal_uint8 old_ReferenceEtpr[FDD_E_SCELL_TOTAL];
3570 /*UMAC*/
3571 kal_uint8 update_ReferenceEtpr[FDD_E_SCELL_TOTAL];
3572 /*UMAC*/
3573 kal_uint32 ref_etpr_x225[FDD_E_SCELL_TOTAL];
3574 /*UMAC*/
3575 kal_uint32 update_ref_etpr_x225[FDD_E_SCELL_TOTAL];
3576 /*UMAC*/
3577} FDD_umac_umac_edch_post_tx_proc_ind_struct;
3578/*UMAC*//*========== END UMAC DEBUG MESSAGE ==========*/
3579/**********************************************************************************************************************/
3580/*********************************** UL1 Interface maintained by UMAC (END) *************************************/
3581/**********************************************************************************************************************/
3582
3583/*------------------- MSC Composer -----------------------------*/
3584/* The following definition is used only for MSC composer. */
3585typedef union _FDD_local_para_unpack_T
3586{
3587 fdd_cphy_pch_setup_req_struct cphy_pch_setup_req;
3588 fdd_cphy_pch_modify_req_struct cphy_pch_modify_req;
3589 fdd_cphy_pch_release_req_struct cphy_pch_release_req;
3590 fdd_cphy_fach_setup_req_struct cphy_fach_setup_req;
3591 fdd_cphy_fach_modify_req_struct cphy_fach_modify_req;
3592 fdd_cphy_fach_release_req_struct cphy_fach_release_req;
3593 fdd_cphy_dch_setup_req_struct cphy_dch_setup_req;
3594 fdd_cphy_dch_modify_req_struct cphy_dch_modify_req;
3595 fdd_cphy_dch_release_req_struct cphy_dch_release_req;
3596 fdd_cphy_rach_setup_req_struct cphy_rach_setup_req;
3597 fdd_cphy_rach_release_req_struct cphy_rach_release_req;
3598 fdd_cphy_hsdsch_setup_req_struct cphy_hsdsch_setup_req;
3599 fdd_cphy_hsdsch_modify_req_struct cphy_hsdsch_modify_req;
3600 fdd_cphy_hsdsch_release_req_struct cphy_hsdsch_release_req;
3601 fdd_cphy_edch_setup_req_struct cphy_edch_setup_req;
3602 fdd_cphy_edch_modify_req_struct cphy_edch_modify_req;
3603 fdd_cphy_edch_release_req_struct cphy_edch_release_req;
3604#ifdef __UMTS_R7__
3605 fdd_cphy_cpc_config_req_struct cphy_cpc_setup_req;
3606#endif /* __UMTS_R7__ */
3607} FDD_local_para_unpack_T;
3608
3609typedef struct _FDD_msg_buf_unpack_T /* Buffer of message container */
3610{
3611 kal_uint8 channel_id; /* Channel ID */
3612 msg_type msg_id; /* Message ID */
3613 kal_uint16 buff_size; /* Buffer size */
3614 FDD_local_para_unpack_T buffer; /* Channel configuration message buffer */
3615} FDD_msg_buf_unpack_T;
3616
3617typedef struct _fdd_cphy_msg_container_req_unpack_struct
3618{
3619 LOCAL_PARA_HDR
3620
3621 kal_uint8 at_ref; /* Reference channge of activation time.
3622 0 : Ref channel is the released channel.
3623 There should be ch to be released
3624 1 : Ref channel is the setup channel.
3625 There should be ch to be setup.
3626 */
3627 kal_int16 rx_cfn; /* Indicate peer message receive cfn. Ex: tti = 4, receive frame number : 0,1,2,3. rx_cfn = 3 (set by ul1)
3628 [Range]: -1 ~ 255.
3629 -1 : Means upper layer internal control
3630 */
3631#ifdef __UMTS_R6__
3632 kal_bool delay_restriction; /* From R6 : TS25.331 8.6.3.1 */
3633#endif
3634 FDD_meas_control_E meas_control; /* Indicate whether UL1 need to not to resume meas. after apply corresponding buffer's config. */
3635
3636 kal_uint8 msg_num; /* # of included msg. 1 ~ 4 */
3637 FDD_msg_buf_unpack_T msg_buffer[4]; /* List of msg buffer for included channel msg */
3638
3639 /* [R5R6] For HS-DSCH and E-DCH */
3640 kal_uint8 h_msg_num; /* # of included H-msg. 0~2 */
3641 FDD_msg_buf_unpack_T h_msg_buffer[2]; /* List of msg buffer for included channel msg */
3642 kal_uint8 e_msg_num; /* # of included E-msg. 0~2 */
3643 FDD_msg_buf_unpack_T e_msg_buffer[2]; /* List of msg buffer for included channel msg */
3644#ifdef __UMTS_R7__
3645 kal_uint8 cpc_msg_num; /* # of included CPC-msg. 0~1 */
3646 FDD_msg_buf_unpack_T cpc_msg_buffer[1]; /* List of msg buffer for included CPC msg */
3647#endif /* __UMTS_R7__ */
3648} fdd_cphy_msg_container_req_unpack_struct;
3649
3650typedef struct _ul1_umts_max_tx_pwr_red_req_struct
3651{
3652 LOCAL_PARA_HDR
3653
3654 kal_bool valid;
3655 //UMTS_CUSTOM_TAS_STATE_E tas_state; /*0: Main, 1: Div, 2: Main'*/
3656 kal_uint8 umts_power_reduction_in_edb[20][2/*Service*/];
3657
3658 /* Add power reduction value for ANT1 (op=9/10).
3659 * When user only specify one set of values by using op=1/3,
3660 * L4C help copy parameters from umts_power_reduction_in_edb[] to umts_power_reduction_in_edb_tas[]*/
3661 kal_uint8 umts_power_reduction_in_edb_tas[20][2/*Service*/];
3662} ul1_umts_max_tx_pwr_red_req_struct;
3663
3664typedef enum
3665{
3666 FDD_UL1_EM_TST_CMD_TX_DPCH = 0,
3667 FDD_UL1_EM_TST_CMD_RX_RSSI_MEASURE = 1,
3668 FDD_UL1_EM_TST_CMD_GET_PD_MEASUREMENT = 2, // retrieved TX power
3669 FDD_UL1_EM_TST_CMD_END
3670} FDD_UL1_EM_TSTCmdType;
3671
3672typedef struct
3673{
3674 kal_int8 power;
3675 kal_uint8 rf_band;
3676 kal_uint16 ul_freq;
3677} FDD_UL1_EM_TSTCmdTxDPCh_T;
3678
3679typedef struct
3680{
3681 kal_uint16 dl_freq;
3682} FDD_UL1_EM_TSTCmdRxRSSI_T;
3683
3684typedef union
3685{
3686 FDD_UL1_EM_TSTCmdTxDPCh_T txdpch;
3687 FDD_UL1_EM_TSTCmdRxRSSI_T rxrssi;
3688} FDD_UL1_EM_TSTCmdParam;
3689
3690typedef struct _l4ul1_em_tst_req_struct
3691{
3692 LOCAL_PARA_HDR
3693
3694 kal_uint8 src_id;
3695 FDD_UL1_EM_TSTCmdType type;
3696 FDD_UL1_EM_TSTCmdParam param;
3697} l4ul1_em_tst_req_struct;
3698
3699
3700typedef struct _l4ul1_em_tst_cnf_struct
3701{
3702 LOCAL_PARA_HDR
3703
3704 kal_uint8 src_id;
3705 kal_bool success;
3706#if defined(__ATERFTX_ERROR_HANDLE_ENHANCE__)
3707 ps_cause_enum err_cause;
3708#endif //__ATERFTX_ERROR_HANDLE_ENHANCE__
3709} l4ul1_em_tst_cnf_struct;
3710
3711typedef struct _l4ul1_em_tx_report_ind
3712{
3713 LOCAL_PARA_HDR
3714
3715 kal_int32 tx_power; // retrieved TX power
3716} l4ul1_em_tx_report_ind_struct;
3717
3718typedef l4ul1_em_tst_req_struct l4cul1_em_tst_control_req_struct;
3719typedef l4ul1_em_tst_cnf_struct l4cul1_em_tst_control_cnf_struct;
3720typedef l4ul1_em_tx_report_ind_struct l4cul1_em_tx_report_ind_struct;
3721
3722typedef struct _l4cul1_get_rf_temperature_req_struct
3723{
3724 LOCAL_PARA_HDR
3725
3726} l4cul1_get_rf_temperature_req_struct;
3727
3728typedef struct _l4cul1_get_rf_temperature_cnf_struct
3729{
3730 LOCAL_PARA_HDR
3731
3732 kal_int16 modem_temperature;
3733} l4cul1_get_rf_temperature_cnf_struct;
3734
3735typedef struct _l4cul1_rssi_measurement_ind_struct
3736{
3737 LOCAL_PARA_HDR
3738 kal_int16 rssi[2]; /* RSSI. Range: -400 ~ -100 means (-100 ~ -25)dBm 0.25 dB step */
3739 kal_int32 rssi_edBm[2]; /* RSSI value in 1/8 dBm */
3740 kal_uint16 uarfcn; /* UARFCN */
3741
3742} l4cul1_rssi_measurement_ind_struct;
3743
3744/* Inform SLT task that UL1 has finished task init */
3745typedef struct _FDD_ul1_slt_task_init_ind_struct
3746{
3747 LOCAL_PARA_HDR
3748
3749} fdd_ul1_slt_task_init_ind_struct;
3750
3751#if defined (__MML1_ADT_ENABLE__)
3752/*****************************************************************************
3753 UL1 req for ADT Task
3754*****************************************************************************/
3755typedef struct _fdd_ul1_l1adt_enter_connected_req_struct
3756{
3757 LOCAL_PARA_HDR
3758 FDD_ADT_Mode_E adt_mode;
3759} fdd_ul1_l1adt_enter_connected_req_struct;
3760
3761typedef struct _fdd_ul1_l1adt_leave_connected_req_struct
3762{
3763 LOCAL_PARA_HDR
3764 FDD_ADT_Mode_E adt_mode;
3765} fdd_ul1_l1adt_leave_connected_req_struct;
3766
3767typedef struct _fdd_ul1_l1adt_enter_fdd_mode_req_struct
3768{
3769 LOCAL_PARA_HDR
3770} fdd_ul1_l1adt_enter_fdd_mode_req_struct;
3771
3772typedef struct _fdd_ul1_l1adt_enter_fdd_mode_ind_struct
3773{
3774 LOCAL_PARA_HDR
3775} fdd_ul1_l1adt_enter_fdd_mode_ind_struct;
3776
3777/*****************************************************************************
3778 confirm from ADT Task to UL1
3779*****************************************************************************/
3780typedef struct _fdd_ul1_l1adt_enter_connected_cnf_struct
3781{
3782 LOCAL_PARA_HDR
3783 kal_int32 adt_dl_result;
3784 /*
3785 {//PASS_DL_(UN)COMPLETE_xxx -> xxx means the current RAT mode
3786 FAIL_OTHER_RAT_IS_CONN,
3787 PASS_DL_COMPLETE_CONN,
3788 PASS_DL_NOT_YET_FINISHED_CONN,
3789 PASS_DL_COMPLETE_IDLE,
3790 PASS_DL_NOT_YET_FINISHED_IDLE,
3791 PASS_STOP_N_RESTART_DL_IDLE,
3792 PASS_START_DL_IDLE
3793 }
3794 */
3795} fdd_ul1_l1adt_enter_connected_cnf_struct;
3796
3797typedef struct _fdd_ul1_l1adt_leave_connected_cnf_struct
3798{
3799 LOCAL_PARA_HDR
3800 kal_int32 idle_result;
3801 /*
3802 {
3803 NORMAL,
3804 ABNORMAL_IDLE,
3805 ABNORMAL_OTHER_CONN
3806 }
3807 */
3808} fdd_ul1_l1adt_leave_connected_cnf_struct;
3809
3810typedef struct _fdd_ul1_l1adt_enter_fdd_mode_cnf_struct
3811{
3812 LOCAL_PARA_HDR
3813} fdd_ul1_l1adt_enter_fdd_mode_cnf_struct;
3814
3815#endif
3816
3817/******************************************************************************
3818 * MSG_ID_UL1D_LOOPBACK_REQ primptive
3819 * FROM : TST
3820 * TO : Dummy UPS
3821 * DESCRIPTION :
3822 *
3823 ******************************************************************************/
3824typedef struct
3825{
3826 LOCAL_PARA_HDR
3827 kal_uint16 test_id;
3828 kal_uint16 case_id;
3829 kal_uint16 pattern_id;
3830 void *pattern_address;
3831 kal_uint32 pattern_size; // unit: byte
3832 kal_uint32 pm[10];
3833 kal_uint32 sz[30];
3834 kal_uint32 ad[30];
3835} ul1d_loopback_req_struct;
3836
3837typedef struct
3838{
3839 LOCAL_PARA_HDR
3840 kal_uint16 test_id;
3841 kal_uint16 case_id;
3842 kal_uint16 pattern_id;
3843 void *pattern_address;
3844 kal_uint32 pattern_size; // unit: byte
3845 kal_uint32 pm[10];
3846 kal_uint32 sz[30];
3847 kal_uint32 ad[30];
3848} modem_loopback_req_struct;
3849
3850typedef struct
3851{
3852 LOCAL_PARA_HDR
3853 kal_uint16 test_id;
3854 kal_uint16 case_id;
3855 kal_uint16 pattern_id;
3856 kal_bool result; // true=pass, false=fail
3857 char trace_msg[256]; // null-terminated string
3858} modem_loopback_result_ind_struct;
3859/* Yuda.lee added for Android M */
3860typedef struct
3861{
3862 LOCAL_PARA_HDR
3863
3864 kal_uint8 srcid; /* srcid is set by REQUEST */
3865 kal_uint32 lce_mode; /* STOP: 0, PUSH MODE: 1, PULL_MODE: 2 */
3866 kal_uint32 lce_rpt_interval_ms; /* flexible time unit [ms] */
3867} l4cul1_hspa_lce_report_req_struct;
3868
3869typedef struct
3870{
3871 LOCAL_PARA_HDR
3872
3873 kal_uint8 srcid; /* srcid is set by REQUEST */
3874} l4cul1_hspa_lce_report_pulldata_req_struct;
3875
3876
3877typedef struct
3878{
3879 LOCAL_PARA_HDR
3880
3881 kal_uint8 srcid; /* srcid is same as REQUEST */
3882 kal_int8 lce_status; /* stopped:0, active: 1 */
3883 kal_uint32 lce_act_interval_ms; /* actually reporting interval, unit [ms]*/
3884} l4cul1_hspa_lce_report_cnf_struct;
3885
3886typedef struct
3887{
3888 LOCAL_PARA_HDR
3889
3890 kal_uint8 srcid; /* PUSH MODE: 0xFF, otherwise srcid is same as REQUEST */
3891 kal_uint8 conf_level; /* confidence level of capacity estimate (0~100)*/
3892 kal_uint8 lce_suspend; /* 0: not suspended, 1: suspended, radio idle, handover, outage, and etc.*/
3893 kal_uint32 last_hop_cap_kbps; /* capacity:kilobits/second, kbps*/
3894} l4cul1_hspa_lce_report_ind_struct;
3895
3896#endif
3897