mcu/interface/middleware/hif/tmc_struct.h

/*****************************************************************************
*  Copyright Statement:
*  --------------------
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/*******************************************************************************
 * Filename:
 * ---------
 *   tmc_struct.h
 *
 * Project:
 * --------
 *   UMOLY
 *
 * Description:
 * ------------
 *   Thermal Management Controller ILM structure and interface definition.
 *
 * Author:
 * -------
 * -------
 *
 *==============================================================================
 *                 HISTORY
 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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 *==============================================================================
 *******************************************************************************/
#ifndef __INC_TMC_STRUCT_H
#define __INC_TMC_STRUCT_H

#include "kal_public_defs.h"

/* Macro & Enum definition for Gen97 */
#define MAX_SUPPORTED_CC_NB  5
#define MAX_BAND_NB          MAX_SUPPORTED_CC_NB /* max. supported band number at same time should be algin max supported CC number */
#define MAX_CELL_NB          8
#define TMC_CTRL_MAX_CG_NUM  2

/* Define invalid value */
#define INVALID_SUPPORTED_CC_INDEX  MAX_SUPPORTED_CC_NB
#define INVALID_CELL_INDEX          0xFF
#define INVALID_BAND_INDEX          0
#define TMC_INVALID_NW_STATUS_ID    0xFF

typedef enum tmc_ctrl_cg_enum {
    TMC_CTRL_CG_NA,     /* none */
    TMC_CTRL_CG_MCG,    /* refer as MCG */
    TMC_CTRL_CG_SCG     /* refer as SCG */
} tmc_ctrl_cg_enum;

typedef enum tmc_ctrl_cmd_enum {
    TMC_CTRL_CMD_THROTTLING = 0,
    TMC_CTRL_CMD_CA_CTRL,
    TMC_CTRL_CMD_PA_CTRL,
    TMC_CTRL_CMD_COOLER_LV,
    TMC_CTRL_CMD_CELL,            /* MD internal use : refer as del_cell */
    TMC_CTRL_CMD_BAND,            /* MD internal use : refer as del_band */
    TMC_CTRL_CMD_INTER_BAND_OFF,  /* MD internal use : similar to PA_OFF on Gen95 */
    TMC_CTRL_CMD_CA_OFF,          /* MD internal use : similar to CA_OFF on Gen95 */
    TMC_CTRL_CMD_SCG_OFF,         /* Fall back to 4G */
    TMC_CTRL_CMD_SCG_ON,          /* Enabled 5G */
    TMC_CTRL_CMD_TX_POWER,
    TMC_CTRL_CMD_LOW_POWER_IND,
    TMC_CTRL_CMD_SELF_CC_CTRL,
    TMC_CTRL_CMD_DEFAULT
} tmc_ctrl_cmd_enum;

typedef enum tmc_ctrl_result_enum {
    TMC_CTRL_RESULT_SUCCESS = 0,
    TMC_CTRL_RESULT_STATUS_IND_ID_MISMATCH,
    TMC_CTRL_RESULT_MAC_RESET_ONGOING,
    TMC_CTRL_RESULT_FAIL_INCORRECT_CMD,
    TMC_CTRL_RESULT_REJECT,
    TMC_CTRL_RESULT_OTHERS
} tmc_ctrl_result_enum;

typedef enum tmc_ctrl_nw_status_enum {
    TMC_CTRL_STATUS_SESSION_ESTABLISH = 0,
    TMC_CTRL_STATUS_UPDATE,
    TMC_CTRL_STATUS_SPCELL_CHANGE,
    TMC_CTRL_STATUS_OTHERS
} tmc_ctrl_nw_status_enum;

typedef enum tmc_throt_ctrl_enum {
    TMC_THROT_ENABLE_IMS_ENABLE = 0,
    TMC_THROT_ENABLE_IMS_DISABLE,
    TMC_THROT_DISABLE,
} tmc_throt_ctrl_enum;

typedef enum tmc_ca_ctrl_enum {
    TMC_CA_ON = 0, /* leave thermal control */
    TMC_CA_OFF,
} tmc_ca_ctrl_enum;

typedef enum tmc_pa_ctrl_enum {
    TMC_PA_ALL_ON = 0, /* leave thermal control */
    TMC_PA_OFF_1PA,
} tmc_pa_ctrl_enum;

typedef enum tmc_cc_ctrl_enum {
    TMC_SELF_CC_CTRL_ENABLED = 0, /* step by step remove cc */
    TMC_SELF_CC_CTRL_ENABLED_MCG_CA_OFF,
    TMC_SELF_CC_CTRL_ENABLED_SCG_CA_OFF,
    TMC_SELF_CC_CTRL_ENABLED_ALL_CA_OFF,
    TMC_SELF_CC_CTRL_ENABLED_SCG_OFF,
    TMC_SELF_CC_CTRL_ENABLED_MCG_CA_OFF_SCG_OFF,
    TMC_SELF_CC_CTRL_ENABLED_LTE_ONLY,
    TMC_SELF_CC_CTRL_DISABLED,
} tmc_cc_ctrl_enum;

typedef enum tmc_cooler_lv_ctrl_enum {
    TMC_COOLER_LV_ENABLE = 0,
    TMC_COOLER_LV_DISABLE,
} tmc_cooler_lv_ctrl_enum;

typedef enum tmc_cooler_lv_enum {
    TMC_COOLER_LV0 = 0,
    TMC_COOLER_LV1,
    TMC_COOLER_LV2,
    TMC_COOLER_LV3,
    TMC_COOLER_LV4,
    TMC_COOLER_LV5,
    TMC_COOLER_LV6,
    TMC_COOLER_LV7,
    TMC_COOLER_LV8,
    TMC_COOLER_MAX
} tmc_cooler_lv_enum;

typedef enum tmc_nw_stat_enum {
    TMC_NW_STAT_MCG = 0,
    TMC_NW_STAT_SCG,
    TMC_NW_STAT_MAX_NUM
} tmc_nw_stat_enum;

typedef enum tmc_ctrl_nl1_frq_enum {
    TMC_NR_FRE_FR1 = 0,
    TMC_NR_FRE_FR2,
    TMC_NR_FRE_MAX_NUM
} tmc_ctrl_nl1_frq_enum;

typedef enum tmc_tx_pwr_event_enum {
    TMC_TW_PWR_VOLTAGE_LOW_EVENT = 0,
    TMC_TW_PWR_LOW_BATTERY_EVENT,
    TMC_TW_PWR_OVER_CURRENT_EVENT,
    TMC_TW_PWR_REDUCE_OTHER_MAX_TX_EVENT, /* reserved for reduce 2G/3G/4G/C2K max TX power for certain value */
    TMC_TW_PWR_REDUCE_NR_MAX_TX_EVENT,    /* reserved for reduce 5G max TX power for certain value */
    TMC_TW_PWR_EVENT_MAX_NUM
} tmc_lpower_event_enum;

typedef enum tmc_tx_pwr_status_lv_enum {
    TMC_TX_PWR_STATUS_LV0 = 0,
    TMC_TX_PWR_STATUS_LV1,
    TMC_TX_PWR_STATUS_LV2,
    TMC_TX_PWR_STATUS_MAX
} tmc_tx_pwr_status_lv_enum;

typedef enum tmc_overheated_rat_enum {
    TMC_OVERHEATED_LTE = 0,
    TMC_OVERHEATED_NR,
    TMC_OVERHEATED_NA,
    TMC_OVERHEATED_MAX
} tmc_overheated_rat_enum;

typedef enum tmc_cooler_tbl_enum {
    TMC_UL_THROTTLE_COOLER = 0,
    TMC_OTHER_RAT_REDUCE_TX_COOLER,
    TMC_NR_REDUCE_TX_COOLER,
    TMC_CC_CONTROL_COOLER,
    TMC_SW_SHUTDOWN_COOLER,
    TMC_FLIHT_MODE_COOLER,
    TMC_MAX_COOLER
} tmc_cooler_tbl_enum;

typedef enum tmc_ctrl_req_enum {
    TMC_CTRL_REQ_SET_ACTUATOR = 0,
    TMC_CTRL_REQ_SET_COOLER,
    TMC_CTRL_REQ_MAX_NUM
} tmc_ctrl_req_enum;

typedef enum tmc_req_result_enum {
    TMC_RESULT_SUCCESS,
    TMC_RESULT_FAILED,
    TMC_RESULT_UNSUPPORTED_LV,
    TMC_RESULT_UNSUPPORTED_ACTUATOR_ID,
    TMC_RESULT_L5_ACTION_SW_SHUTDOWN_ENABLED,
    TMC_RESULT_L5_ACTION_SW_SHUTDOWN_DISABLED,
    TMC_RESULT_L5_ACTION_FLIGHT_MODE_ENABLED,
    TMC_RESULT_L5_ACTION_FLIGHT_MODE_DISABLED,
    TMC_RESULT_MAX
} tmc_req_result_enum;

typedef enum tmc_ctrl_low_pwr_enum {
    TMC_CTRL_LOW_POWER_LOW_BATTERY_EVENT = 0,  /* battery less than threshold (ex : 20%) */
    TMC_CTRL_LOW_POWER_RECHARGE_BATTERY_EVENT, /* battery recharge over threshold (ex : 25%) */
    TMC_CTRL_LOW_POWER_MAX
} tmc_ctrl_low_pwr_enum;

typedef enum tmc_req_reason_enum {
    TMC_OVERHEATED_START = 0,
    TMC_OVERHEATED_END,
    TMC_LOW_POWER,
    TMC_RECHARGE,
    TMC_REQ_REASON_MAX
} tmc_req_reason_enum;

/* Structure definition */
typedef struct tmc_ctrl_cell_rt_info_struct {
    kal_uint32                      dl_throughput;
    kal_uint32                      ul_throughput;
    kal_uint8                       dl_bandwidth;
    kal_uint8                       ul_bandwidth;
} tmc_ctrl_cell_rt_info_struct;

typedef struct tmc_ctrl_cell_info_struct {
    kal_uint8                       cell_idx;
    kal_bool                        is_specll;
    kal_bool                        is_DLonly;
} tmc_ctrl_cell_info_struct;

typedef struct tmc_ctrl_band_info_struct {
    kal_uint8                       band_id;
    kal_uint8                       cell_info_idx[MAX_SUPPORTED_CC_NB];
} tmc_ctrl_band_info_struct;

typedef struct tmc_ctrl_cg_info_struct {
    tmc_ctrl_cg_enum                cg_type;
    kal_uint8                       band_num;
    tmc_ctrl_band_info_struct       band[MAX_BAND_NB];
    tmc_ctrl_cell_info_struct       cell[MAX_SUPPORTED_CC_NB];
    tmc_ctrl_cell_rt_info_struct    cell_info[MAX_CELL_NB];
} tmc_ctrl_cg_info_struct;

typedef struct tmc_emac_nw_status_struct {
    kal_uint8                       status_ind_id;
    tmc_ctrl_nw_status_enum         status_cause;
    tmc_ctrl_cg_info_struct         cell_group[TMC_CTRL_MAX_CG_NUM];
    kal_uint8                       total_cell;
    kal_uint8                       sim_idx;
} tmc_emac_nw_status_struct;

typedef struct tmc_emac_nw_status_ind_struct {
    LOCAL_PARA_HDR
    tmc_emac_nw_status_struct       nw_status;
} tmc_emac_nw_status_ind_struct;

typedef struct tmc_emac_thermal_control_req_struct {
    LOCAL_PARA_HDR
    kal_uint8                       status_ind_id;
    tmc_ctrl_cmd_enum               ctrl_cmd;
    tmc_ctrl_cg_enum                cg_type;
    kal_uint8                       band_num;
    kal_uint8                       forbidden_band[MAX_BAND_NB];
    kal_uint8                       cell_num;
    kal_uint32                      forbidden_cell_bitmap;
    kal_bool                        is_scg_release_signature;  /*< only valid for TMC_CTRL_CMD_SCG_OFF ctrl */
} tmc_emac_thermal_control_req_struct;

typedef struct tmc_emac_thermal_control_cnf_struct {
    LOCAL_PARA_HDR
    tmc_ctrl_result_enum            result;
    tmc_emac_nw_status_struct       nw_status;
} tmc_emac_thermal_control_cnf_struct;

typedef struct tmc_nmac_nw_status_struct{
    kal_uint8                       status_ind_id;
    tmc_ctrl_nw_status_enum         status_cause;
    tmc_ctrl_cg_info_struct         cell_group[TMC_CTRL_MAX_CG_NUM];
    kal_uint8                       total_cell;
    kal_uint8                       sim_idx;
}tmc_nmac_nw_status_struct;

typedef struct tmc_nmac_nw_status_ind_struct{
    LOCAL_PARA_HDR
    tmc_nmac_nw_status_struct       nw_status;
} tmc_nmac_nw_status_ind_struct;

typedef struct tmc_nmac_thermal_control_req_struct {
    LOCAL_PARA_HDR
    kal_uint8                       status_ind_id;
    tmc_ctrl_cmd_enum               ctrl_cmd;
    tmc_ctrl_cg_enum                cg_type;
    kal_uint8                       band_num;
    kal_uint8                       forbidden_band[MAX_BAND_NB];
    kal_uint8                       cell_num;
    kal_uint32                      forbidden_cell_bitmap;
    kal_bool                        is_scg_release_signature;  /*< only valid for TMC_CTRL_CMD_SCG_OFF ctrl */
} tmc_nmac_thermal_control_req_struct;

typedef struct tmc_nmac_thermal_control_cnf_struct {
    LOCAL_PARA_HDR
    tmc_ctrl_result_enum            result;
    tmc_nmac_nw_status_struct       nw_status;
} tmc_nmac_thermal_control_cnf_struct;

typedef struct tmc_ctrl_config
{
    kal_uint8  ctrl_cmd;  /* tmc_ctrl_cmd_enum */
    union {
        struct tmc_throttling {
            kal_uint8  thrott_ctrl; /* tmc_throt_ctrl_enum */
            kal_uint8  active_period_100ms;
            kal_uint8  suspend_period_100ms;
        } tmc_throttling;

        struct tmc_ca_ctrl {
            kal_uint8  ca_ctrl;    /* tmc_ca_ctrl_enum */
            kal_uint8  reserved1;
            kal_uint8  reserved2;
        } tmc_ca_ctrl;

        struct tmc_pa_ctrl {
            kal_uint8  pa_ctrl;    /* tmc_pa_ctrl_enum */
            kal_uint8  reserved1;
            kal_uint8  reserved2;
        } tmc_pa_ctrl;

        struct tmc_cooler_lv {
            kal_uint8  enable;         /* tmc_cooler_lv_ctrl_enum */
            kal_uint8  cooler_lv;      /* tmc_cooler_lv_enum */
            kal_uint8  overheated_rat; /* tmc_overheated_rat_enum */
        } tmc_cooler_lv;

        struct tmc_tx_power {
            kal_uint8  status;            /* tmc_tx_pwr_status_lv_enum */
            kal_uint8  event;             /* tmc_tx_pwr_event_enum */
            kal_uint8  reduce_max_tx_pwr; /* reserved for reduce max tx_pwer value (unit : 1/8 db) */
        } tmc_tx_power;

        struct tmc_cc_ctrl {
            kal_uint8  cc_ctrl;         /* tmc_cc_ctrl_enum */
            kal_uint8  overheated_rat;  /* tmc_overheated_rat_enum */
            kal_uint8  reserved1;
        } tmc_cc_ctrl;

        struct tmc_low_power {
            kal_uint8  event;	/* tmc_ctrl_low_pwr_enum */
            kal_uint8  reserved1;
            kal_uint8  reserved2;
        } tmc_low_power;
    } u;
} tmc_ctrl_config;

typedef struct tmc_nw_stat_struct {
    module_type               mod_id;
    tmc_emac_nw_status_struct nw_stat;
} tmc_nw_stat_struct;

typedef struct tmc_control_req_struct {
    LOCAL_PARA_HDR
    kal_uint32 ap_req_cmd;
} tmc_control_req_struct;

typedef struct tmc_nl1_nw_status_ind_struct {
    LOCAL_PARA_HDR
    kal_uint32 max_dl_bw[TMC_NR_FRE_MAX_NUM];
    kal_uint32 max_dl_mimo_layer[TMC_NR_FRE_MAX_NUM];
    kal_uint32 max_ul_bw[TMC_NR_FRE_MAX_NUM];
    kal_uint32 max_ul_mimo_layer [TMC_NR_FRE_MAX_NUM];
} tmc_nl1_nw_status_ind_struct;

typedef struct tmc_lv_cfg {
    kal_uint32 zone_id;
    kal_uint32 user_impact;
    kal_uint32 efficiency;
    kal_uint32 value1;
    kal_uint32 value2;
} tmc_lv_cfg;

typedef struct tmc_lv_tbl {
    tmc_lv_cfg lv_cfg[TMC_COOLER_MAX];
} tmc_lv_tbl;

typedef struct tmc_ctrl_req_struct {
    LOCAL_PARA_HDR
    kal_uint32 status_id;
    tmc_ctrl_req_enum ctrl_cmd;
    union {
        struct {
            kal_uint32 actuator_id;
            kal_uint32 lv;
        } tmc_actuator_cfg;

        struct {
            tmc_ctrl_config tmc_ctrl_req;
        } tmc_cooler_cfg;
    } u;
} tmc_ctrl_req_struct;

typedef struct tmc_ctrl_rsp_struct {
    LOCAL_PARA_HDR
    kal_uint32 status_id;
    tmc_req_result_enum result;
} tmc_ctrl_rsp_struct;

typedef struct tmc_l4bpwr_battery_status_req_struct {
    LOCAL_PARA_HDR
    kal_bool is_low_battery;
} tmc_l4bpwr_battery_status_req_struct;

/*
 * Bitmap for tmc_emac_thermal_control_req enhance functions.
 * Need to sync with WCT/SE3/PS2 YK.Liu before modification.
 */
#define TMC_ENHANCE_FUNC_DISABLE_CA             0x00000001
#define TMC_ENHANCE_FUNC_TX_POWER_BACKOFF       0x00000002

/*
 * Local parameter structure for MSG_ID_TMC_EMAC_THERMAL_CONTROL_REQ for Gen93
 */
typedef struct
{
    LOCAL_PARA_HDR
#if defined(__MD93__)
    kal_bool     overheat_flg;    /* TMC notify mobile phone temperature is too high, need to cool down */
    kal_uint8    enhance_func_bitmap;
#else
    tmc_ctrl_config tmc_ctrl_cfg;
#endif
} tmc_emac_thermal_control_req;

/*------------------------------------------------------------------------------
 * DHL logging structure
 *----------------------------------------------------------------------------*/
//typedef tmc_emac_thermal_control_req tmc_emac_thermal_control_req_struct;

#endif /* __INC_TMC_STRUCT_H */