| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | #ifndef __IDC_SUART_H__ |
| 2 | #define __IDC_SUART_H__ |
| 3 | |
| 4 | #include "reg_base.h" |
| 5 | |
| 6 | |
| 7 | #define REG_PERISYS_IDC_SUART_RBR_THR_DLL_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x00) |
| 8 | #define REG_PERISYS_IDC_SUART_IER_DLM_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x04) |
| 9 | #define REG_PERISYS_IDC_SUART_IIR_FCR_EFR_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x08) |
| 10 | #define REG_PERISYS_IDC_SUART_LCR_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x0C) |
| 11 | #define REG_PERISYS_IDC_SUART_MCR_XON1_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x10) |
| 12 | #define REG_PERISYS_IDC_SUART_LSR_XON2_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x14) |
| 13 | #define REG_PERISYS_IDC_SUART_MSR_XOFF1_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x18) |
| 14 | #define REG_PERISYS_IDC_SUART_SCR_XOFF2_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x1C) |
| 15 | #define REG_PERISYS_IDC_SUART_AUTOBAUD_EN_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x20) |
| 16 | #define REG_PERISYS_IDC_SUART_RATE_STEP_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x24) |
| 17 | #define REG_PERISYS_IDC_SUART_STEP_COUNT_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x28) |
| 18 | #define REG_PERISYS_IDC_SUART_SAMPLE_COUNT_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x2C) |
| 19 | #define REG_PERISYS_IDC_SUART_AUTOBAUD_DATA_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x30) |
| 20 | #define REG_PERISYS_IDC_SUART_RATE_FIX_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x34) |
| 21 | #define REG_PERISYS_IDC_SUART_AUTOBAUD_RATE_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x38) |
| 22 | #define REG_PERISYS_IDC_SUART_GUARD_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x3C) |
| 23 | #define REG_PERISYS_IDC_SUART_ESC_CHAR_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x40) |
| 24 | #define REG_PERISYS_IDC_SUART_ESC_EN_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x44) |
| 25 | #define REG_PERISYS_IDC_SUART_SLEEP_EN_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x48) |
| 26 | #define REG_PERISYS_IDC_SUART_RXDMA_EN_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x4C) |
| 27 | #define REG_PERISYS_IDC_SUART_RXTRIG_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x50) |
| 28 | #define REG_PERISYS_IDC_SUART_RXTIMEOUT_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x54) |
| 29 | #define REG_PERISYS_IDC_SUART_RXDMA_CTRL_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x58) |
| 30 | #define REG_PERISYS_IDC_SUART_DUMMY (BASE_ADDR_PERISYS_IDC_SUART+0x5c) |
| 31 | #define REG_PERISYS_IDC_SUART_START_PRI (BASE_ADDR_PERISYS_IDC_SUART+0x60) |
| 32 | #define REG_PERISYS_IDC_SUART_START_PRI_BITEN (BASE_ADDR_PERISYS_IDC_SUART+0x64) |
| 33 | #define REG_PERISYS_IDC_SUART_START_PAT (BASE_ADDR_PERISYS_IDC_SUART+0x68) |
| 34 | #define REG_PERISYS_IDC_SUART_START_PAT_BITEN (BASE_ADDR_PERISYS_IDC_SUART+0x6C) |
| 35 | #define REG_PERISYS_IDC_SUART_FINISH_PRI (BASE_ADDR_PERISYS_IDC_SUART+0x70) |
| 36 | #define REG_PERISYS_IDC_SUART_FINISH_PRI_BITEN (BASE_ADDR_PERISYS_IDC_SUART+0x74) |
| 37 | #define REG_PERISYS_IDC_SUART_FINISH_PAT (BASE_ADDR_PERISYS_IDC_SUART+0x78) |
| 38 | #define REG_PERISYS_IDC_SUART_FINISH_PAT_BITEN (BASE_ADDR_PERISYS_IDC_SUART+0x7C) |
| 39 | |
| 40 | #endif |