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192.168.1.100 / T800_MD / 0b80c7188a6089ae59f523c5d460adad05960e1d / . / mcu / driver / devdrv / uart / inc / uart_internal.h
blob: cb0c0f76ddb5b6abf77e438ee8d43d255fdca9cc [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2001
8*
9*****************************************************************************/
10
11/*****************************************************************************
12 *
13 * Filename:
14 * ---------
15 * dcl_uart.h
16 *
17 * Project:
18 * --------
19 * Maui
20 *
21 * Description:
22 * ------------
23 * Header file of DCL (Driver Common Layer) for UART.
24 *
25 * Author:
26 * -------
27 * -------
28 *
29 ****************************************************************************/
30#ifndef __UART_INTERNAL_H__
31#define __UART_INTERNAL_H__
32
33#include "uart_sw.h"
34#include "dcl.h"
35
36#include "kal_general_types.h"
37#include "drv_comm.h"
38
39#include "qmu_bm.h"
40#include "qmu_bm_size.h"
41#include "qmu_bm_util.h"
42
43typedef enum {
44 UART_ON_VFIFO,
45 UART_ON_DMA,
46 UART_ON_MCU,
47 UART_ON_UNKNOWN
48} UART_WORKING_MODE;
49
50#define UART_STAT_EscDet 0x01
51#define UART_STAT_Break 0x02
52
53#define UART_RecNormal 0
54#define UART_Get3EscChar 1
55#define UART_StartCheckESC 2
56
57#define UART1_HDMA_TX_CHANNEL 2
58#define UART1_HDMA_RX_CHANNEL 3
59
60/*TY adds these to expand flexibility 2004/10/15*/
61typedef void (*UART_TX_FUNC)(UART_PORT port);
62typedef void (*UART_RX_FUNC)(UART_PORT port) ;
63
64
65typedef struct
66{
67 UART_PORT port_no;
68 kal_bool initialized;
69 kal_bool power_on;
70 module_type ownerid;
71 module_type UART_id;
72 kal_bool breakDet;
73 kal_bool EscFound;
74 UARTDCBStruct DCB;
75 UART_RingBufferStruct RingBuffers;
76 UART_ESCDetectStruct ESCDet;
77 BUFFER_INFO Tx_Buffer_ISR; /* receive buffer */
78 BUFFER_INFO Rx_Buffer; /* receive buffer */
79 BUFFER_INFO Tx_Buffer; /* transmit buffer */
80 kal_hisrid hisr;
81 IO_level DSR;
82 /*detect Escape*/
83 DCL_HANDLE handle; /*GPT handle*/
84 kal_uint8 EscCount;
85 kal_uint8 Rec_state; /**/
86 UART_SLEEP_ON_TX sleep_on_tx;
87 kal_bool EnableTX;
88 /*TY adds these to expand flexibility 2004/10/15*/
89 UART_TX_FUNC tx_cb;
90 UART_RX_FUNC rx_cb;
91 //#ifdef __DMA_UART_VIRTUAL_FIFO__
92 kal_uint8 Rx_DMA_Ch;
93 kal_uint8 Tx_DMA_Ch;
94 //#endif
95
96#if defined(DRV_UART_VFIFO_V2)
97#if defined(DRV_UART_VFIFO_V2_USE_GPT)
98 DCL_HANDLE uart_flush_timer_handle; /*GPT handle*/
99 DCL_HANDLE uart_isr_flush_timer_handle; /*GPT handle*/
100#else
101 kal_timerid uart_flush_timer_id;
102#endif //DRV_UART_VFIFO_V2_USE_GPT
103#endif /* defined(DRV_UART_VFIFO_V1) */
104
105
106 // added by ansel for new TTY API
107 kal_bool need_tx_done_cb;
108} UARTStruct;
109
110// for uart dispatch table
111typedef enum
112{
113 UART_TYPE = 0,
114 IRDA_TYPE,
115 USB_TYPE,
116 BLUETOOTH_TYPE,
117 CMUX_TYPE
118}UartType_enum;
119
120typedef struct
121{
122 kal_uint32 timer_old;
123 kal_uint32 timer_now;
124 kal_uint32 timer_during;
125 kal_uint32 timer_start;
126}UART_ecpt_timer_t;
127
128typedef struct _uartdriver
129{
130
131 kal_bool (*Open)(UART_PORT port, module_type ownerid);
132 void (*Close)(UART_PORT port, module_type ownerid);
133 kal_uint16 (*GetBytes)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, kal_uint8 *status, module_type ownerid);
134 kal_uint16 (*PutBytes)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
135 kal_uint16 (*GetRxAvail)(UART_PORT port);
136 kal_uint16 (*GetTxAvail)(UART_PORT port);
137 kal_uint16 (*PutISRBytes)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
138 kal_uint16 (*GetISRTxAvail)(UART_PORT port);
139 void (*Purge)(UART_PORT port, UART_buffer dir, module_type ownerid);
140 //void (*SetOwner)(UART_PORT port, kal_uint8 ownerid);
141 void (*SetOwner)(UART_PORT port, module_type ownerid);
142 void (*SetFlowCtrl)(UART_PORT port, kal_bool XON, module_type ownerid);
143 void (*ConfigEscape)(UART_PORT port, kal_uint8 EscChar, kal_uint16 ESCGuardtime, module_type ownerid);
144 void (*SetDCBConfig)(UART_PORT port, UARTDCBStruct *UART_Config, module_type ownerid);
145 void (*CtrlDCD)(UART_PORT port, IO_level SDCD, module_type ownerid);
146 void (*CtrlBreak)(UART_PORT port, IO_level SBREAK, module_type ownerid);
147 void (*ClrRxBuffer)(UART_PORT port, module_type ownerid);
148 void (*ClrTxBuffer)(UART_PORT port, module_type ownerid);
149 void (*SetBaudRate)(UART_PORT port, UART_baudrate baudrate, module_type ownerid);
150 kal_uint16 (*SendISRData)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode, kal_uint8 escape_char, module_type ownerid);
151 kal_uint16 (*SendData)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid);
152 module_type (*GetOwnerID)(UART_PORT port);
153 void (*SetAutoBaud_Div)(UART_PORT port, module_type ownerid);
154 /*TY adds these to expand flexibility 2004/10/15*/
155 void (*UART_Register_TX_cb)(UART_PORT port, module_type ownerid, UART_TX_FUNC func);
156 void (*UART_Register_RX_cb)(UART_PORT port, module_type ownerid, UART_RX_FUNC func);
157 /*TY adds these to let virtual COM port can retrive exception log 2005/3/8*/
158 kal_uint8 (*GetUARTByte)(UART_PORT port);
159 void (*PutUARTByte)(UART_PORT port, kal_uint8 data);
160 void (*PutUARTBytes)(UART_PORT port, kal_uint8 *data, kal_uint16 len);
161 /*for virtual com port to return DCB configuration*/
162 void (*ReadDCBConfig)(UART_PORT port, UARTDCBStruct *UART_Config);
163 void (*CtrlRI)(UART_PORT port, IO_level SRI, module_type ownerid);
164 void (*CtrlDTR)(UART_PORT port, IO_level SDTR, module_type ownerid);
165 void (*ReadHWStatus)(UART_PORT port, IO_level *SDSR, IO_level *SCTS);
166 kal_uint8 (*GetUARTByte_WithTimeOut)(UART_PORT port, kal_uint8* ch, kal_uint32 timeout_value);
167}UartDriver_strcut;
168
169/*Function Declaration*/
170extern UartDriver_strcut UartDriver;
171
172
173extern kal_bool UART_VFIFO_support[MAX_UART_PORT_NUM];
174#ifdef __DMA_UART_VIRTUAL_FIFO__
175extern UartDriver_strcut UartDriver_VFIFO;
176#endif
177
178extern UartDriver_strcut* pUart_CMD_FUNC[];
179
180
181
182extern void UART1_PDN_ENABLE(void);
183extern void UART1_PDN_DISABLE(void);
184extern void UART2_PDN_ENABLE(void);
185extern void UART2_PDN_DISABLE(void);
186
187/*ISR handler for VFIFO*/
188extern void UART_RecTimeOutHandler(UART_PORT port);
189extern void UART_TrxHandler_VFIFO(UART_PORT port);
190extern void UART_RecHandler_VFIFO(UART_PORT port);
191extern void UART_THRE_hdr_VFIFO(UART_PORT port);
192/*API for VFIFO*/
193extern void U_configure_DMA_VFIFO(void);
194extern kal_uint16 U_GetTxISRRoomLeft_VFIFO(UART_PORT port);
195extern kal_uint16 U_GetTxRoomLeft_VFIFO(UART_PORT port);
196extern kal_uint16 U_GetBytesAvail_VFIFO(UART_PORT port);
197extern kal_uint8 U_GetUARTByte_VFIFO(UART_PORT port);
198extern void U_PutUARTByte_VFIFO(UART_PORT port, kal_uint8 data);
199extern void PutUARTData_VFIFO(UART_PORT port, kal_uint8 escape_char, kal_uint8 data);
200extern kal_uint16 U_GetBytes_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, kal_uint8 *status, module_type ownerid);
201extern kal_uint16 U_PutBytes_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
202extern kal_uint16 U_PutISRBytes_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
203extern kal_uint16 U_SendData_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid);
204extern kal_uint16 U_SendISRData_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid);
205extern kal_bool UART_UseVFIFO(UART_PORT port, kal_bool use_vfifo);
206
207extern void UART_DriverInit(UART_PORT port);
208extern void UART_set_FIFO_trigger(UART_PORT port, kal_uint16 tx_level, kal_uint16 rx_level);
209
210/* Note: for ROM code start */
211#ifdef __ROMSA_SUPPORT__
212/*for mcu rom*/
213extern kal_uint16 U_GetTxISRRoomLeft(UART_PORT port);
214extern kal_uint16 U_PutISRBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
215extern kal_uint16 U_ROM_GetTxISRRoomLeft(UART_PORT port);
216extern UARTStruct *U_ROM_GetUARTPort(UART_PORT port);
217extern kal_uint8 *U_ROM_GetUART_TXilm(UART_PORT port);
218extern void U_ROM_InformUARTOwner(UART_PORT port);
219extern void U_ROM_PushDataToBuf(UART_PORT port, kal_uint8 *data, kal_uint32 real_count);
220extern void U_ROM_EnableTxIntr(UART_PORT port);
221//extern void DRVPDN_Disable(kal_uint32 addr,kal_uint16 code,kal_uint8 handle);
222#endif
223/* Note: for ROM code end */
224
225// Used under ASSERT condition
226// This has effect only when the port does NOT support VFIFO and used as Catcher port
227extern void UART_AssertWaitPrevDataSentOut(UART_PORT port);
228
229
230extern kal_bool UART1DMA_Ini(kal_bool Tx);
231extern kal_bool UART2DMA_Ini(kal_bool Tx);
232extern kal_uint8 GetUARTByte(UART_PORT port);
233extern void PutUARTByte(UART_PORT port, kal_uint8 data);
234extern void UART_SetBaudRate(UART_PORT port, UART_baudrate baud_rate, module_type ownerid);
235extern void UART_SetDCBConfig(UART_PORT port, UARTDCBStruct *UART_Config, module_type ownerid);
236extern void UART_ReadDCBConfig (UART_PORT port, UARTDCBStruct *DCB);
237extern void UART_loopback(UART_PORT port);
238extern void UART_HWInit(UART_PORT port);
239extern kal_bool UART_Open(UART_PORT port, module_type ownerid);
240extern void UART_Close(UART_PORT port, module_type ownerid);
241//extern void UART_SetOwner (UART_PORT port, kal_uint8 ownerid);
242extern void UART_SetOwner (UART_PORT port, module_type ownerid);
243extern void UART_ConfigEscape (UART_PORT port, kal_uint8 EscChar, kal_uint16 ESCGuardtime, module_type ownerid);
244extern void UART_CtrlDTR (UART_PORT port, IO_level SDTR, module_type ownerid);
245extern void UART_ReadHWStatus(UART_PORT port, IO_level *SDSR, IO_level *SCTS);
246extern void UART_CtrlBreak(UART_PORT port, IO_level SBREAK, module_type ownerid);
247extern void UART_Purge(UART_PORT port, UART_buffer dir, module_type ownerid);
248extern void UART_Register_RX_cb(UART_PORT port, module_type ownerid, UART_RX_FUNC func);
249extern void UART_Register_TX_cb(UART_PORT port, module_type ownerid, UART_TX_FUNC func);
250
251//API for single tunnel VFIFO
252extern kal_uint16 U_GetBytesAvail(UART_PORT port);
253extern kal_uint16 U_GetBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, kal_uint8 *status, module_type ownerid);
254extern kal_uint8 U_GetUARTByte(UART_PORT port);
255extern kal_uint16 U_PutBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid );
256extern kal_uint16 U_GetTxRoomLeft(UART_PORT port);
257extern kal_uint16 U_SendISRData(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode, kal_uint8 escape_char, module_type ownerid);
258extern kal_uint16 U_SendData(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid);
259extern void U_PutUARTByte(UART_PORT port, kal_uint8 data);
260
261extern void UART_Boot_PutUARTBytes(UART_PORT port, kal_uint8 *data,kal_uint16 len);
262extern void UART_Bootup_Init(void);
263extern kal_uint16 UART_GetBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, kal_uint8 *status, module_type ownerid);
264extern kal_uint16 UART_PutBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
265extern kal_uint16 UART_PutISRBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
266extern kal_uint16 UART_SendISRData(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode, kal_uint8 escape_char, module_type ownerid);
267extern kal_uint16 UART_SendData(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid );
268extern void UART_SetFlowCtrl(UART_PORT port, kal_bool XON, module_type ownerid);
269extern void UART_CtrlDCD(UART_PORT port, IO_level SDCD, module_type ownerid);
270extern void UART_CtrlRI (UART_PORT port, IO_level SRI, module_type ownerid);
271extern kal_uint16 UART_GetBytesAvail(UART_PORT port);
272extern void UART_SleepOnTx_Enable(UART_PORT port, UART_SLEEP_ON_TX enable_flag);
273extern void UART_SetSleepEnable(UART_PORT port, kal_bool enable);
274extern void UART_SwitchPort(UART_PORT *APP_port, UART_PORT new_uart_port);
275extern void UART_dafault_tx_cb(UART_PORT port);
276extern void UART_dafault_rx_cb(UART_PORT port);
277extern void UART_TurnOnPower(UART_PORT port, kal_bool enable);
278extern kal_bool UART_CheckTxBufferEmpty(UART_PORT port);
279extern kal_bool UART_CheckTxAllSentOut(UART_PORT port);
280extern void UART_GetTxBufferSize(UART_PORT port, kal_uint32 *total_size, kal_uint32 *rest_size);
281extern void UART1_HISR(void);
282extern void UART2_HISR(void);
283extern void UART3_HISR(void);
284extern void UART1_LISR(kal_uint32 vector);
285extern void UART2_LISR(kal_uint32 vector);
286extern void UART3_LISR(kal_uint32 vector);
287extern void uart_hdma_lisr(kal_uint32 vector);
288extern void uart_hdma_hisr(void);
289extern kal_bool uart_support_autoescape(void);
290
291extern void uart_ecpt_timer_reset(UART_PORT port);
292extern void uart_ecpt_timer_start(UART_PORT port);
293extern kal_uint32 uart_ecpt_get_timer_during(UART_PORT port);
294
295void UART_VFIFO_TX_DMA_Enable(UART_PORT port,kal_bool enable);
296void UART_dsp_dafault_rx_cb(UART_PORT port);
297void UART_dsp_dafault_tx_cb(UART_PORT port);
298kal_uint16 BMT_PutBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length);
299kal_uint32 UART_Get_Maxbaudrate(UART_PORT port);
300
301kal_uint32 UART_PutBytesIor(UART_PORT port, void *putIor);
302kal_uint32 UART_PutBytesIor_LIGHT(UART_PORT port, void *putIor);
303kal_uint32 UART_GetBytesIor(UART_PORT port, void *ior);
304void UART_SetNeedTxDoneCb(UART_PORT port, kal_bool needTxDoneCb, module_type ownerid);
305
306kal_uint32 U_GetFlowCtrl(UART_PORT port, module_type ownerid);
307kal_uint32 uart_cal_tgpd_buf_length(void *head, void *tail);
308void uart_en_q_de_q_with_mutex(UART_PORT port, kal_bool tx_or_rx, kal_uint8 en_q_or_de_q, void *p_ior_head, void *p_ior_tail);
309DCL_STATUS uart_en_q_de_q_for_ecpt(UART_PORT port, kal_bool tx_or_rx, kal_uint8 en_q_or_de_q, void **p_ior_head, void **p_ior_tail, kal_uint32 *num);
310void uart_cal_chksum_and_flush_gpd_list(void *gpd_head, void *gpd_tail);
311void uart_clear_hwo_of_gpd_list(void *gpd_head, void *gpd_tail);
312
313DCL_STATUS uart_ecpt_init_hif(UART_PORT port);
314DCL_STATUS uart_ecpt_clear_ch(UART_PORT port);
315DCL_STATUS uart_ecpt_tx_gpd(UART_PORT port, void *p_first_gpd, void *p_last_gpd);
316DCL_STATUS uart_ecpt_tx_done_info(UART_PORT port, void **p_first_gpd, void **p_last_gpd, kal_uint32 *gpd_num);
317DCL_STATUS uart_ecpt_assign_rx_gpd(UART_PORT port, void *p_first_gpd, void *p_last_gpd);
318DCL_STATUS uart_ecpt_get_rx_gpd(UART_PORT port, void **p_first_gpd, void **p_last_gpd, kal_uint32 *gpd_num);
319
320/*end of local parameter struct */
321#define EnableRxIntr(_baseaddr) \
322{\
323 kal_uint32 _savedMask;\
324 kal_uint16 _IER;\
325 _savedMask = SaveAndSetIRQMask();\
326 _IER = DRV_Reg(UART_IER(_baseaddr));\
327 _IER |= (UART_IER_ERBFI | UART_IER_ELSI);\
328 DRV_WriteReg(UART_IER(_baseaddr),_IER);\
329 RestoreIRQMask(_savedMask);\
330}
331
332#define DisableRxIntr(_baseaddr) \
333{\
334 kal_uint16 _IER;\
335 kal_uint32 _savedMask;\
336 _savedMask = SaveAndSetIRQMask();\
337 _IER = DRV_Reg(UART_IER(_baseaddr));\
338 _IER &= ~(UART_IER_ERBFI|UART_IER_ELSI);\
339 DRV_WriteReg(UART_IER(_baseaddr),_IER);\
340 RestoreIRQMask(_savedMask);\
341}
342
343
344#define EnableTxIntr(_baseaddr) \
345{\
346 kal_uint16 _IER;\
347 kal_uint32 _savedMask;\
348 _savedMask = SaveAndSetIRQMask();\
349 _IER = DRV_Reg(UART_IER(_baseaddr));\
350 _IER |= UART_IER_ETBEI;\
351 DRV_WriteReg(UART_IER(_baseaddr),_IER);\
352 RestoreIRQMask(_savedMask);\
353}
354
355#define DisableTxIntr(_baseaddr) \
356{\
357 kal_uint16 _IER;\
358 kal_uint32 _savedMask;\
359 _savedMask = SaveAndSetIRQMask();\
360 _IER = DRV_Reg(UART_IER(_baseaddr));\
361 _IER &= ~UART_IER_ETBEI;\
362 DRV_WriteReg(UART_IER(_baseaddr),_IER);\
363 RestoreIRQMask(_savedMask);\
364}
365
366#define UART_SetDMAIntr(_baseaddr) \
367{\
368 kal_uint16 _IER;\
369 kal_uint32 _savedMask;\
370 _savedMask = SaveAndSetIRQMask();\
371 _IER = DRV_Reg(UART_IER(_baseaddr));\
372 _IER &= ~(UART_IER_ETBEI);\
373 DRV_WriteReg(UART_IER(_baseaddr),_IER);\
374 RestoreIRQMask(_savedMask);\
375}
376
377#define DisableRLSIntr(_baseaddr) \
378{\
379 kal_uint16 _IER;\
380 kal_uint32 _savedMask;\
381 _savedMask = SaveAndSetIRQMask();\
382 _IER = DRV_Reg(UART_IER(_baseaddr));\
383 _IER &= ~(UART_IER_ELSI);\
384 DRV_WriteReg(UART_IER(_baseaddr),_IER);\
385 RestoreIRQMask(_savedMask);\
386}
387
388
389extern UART_WORKING_MODE UART_GetTxWorkingMode(UART_PORT port);
390
391#if defined(__MTK_INTERNAL__) && !defined(__MAUI_BASIC__) && defined(__DRV_DBG_MEMORY_TRACE_SUPPORT__)
392#define DRV_UART_MEMORY_TRACE
393typedef struct{
394 kal_uint16 tag;
395 kal_uint32 time;
396 kal_uint32 data1;
397 kal_uint32 data2;
398}UART_DRV_DBG_DATA;
399#define MAX_UART_DRV_DBG_INFO_SIZE 512
400typedef struct{
401 UART_DRV_DBG_DATA dbg_data[MAX_UART_DRV_DBG_INFO_SIZE];
402 kal_uint16 dbg_data_idx;
403}UART_DRV_DBG_STRUCT;
404extern void uart_drv_dbg_trace(kal_uint16 index, kal_uint32 time, kal_uint32 data1, kal_uint32 data2);
405#define UART_DBG(a,b,c,d) uart_drv_dbg_trace(a,b,c,d);
406#include "us_timer.h"
407extern kal_uint32 L1I_GetTimeStamp(void);
408#define UART_GetTimeStamp L1I_GetTimeStamp
409#else //#if defined(__MTK_INTERNAL__) && !defined(LOW_COST_SUPPORT)
410#define UART_DBG(a,b,c,d) ;
411#endif //#if defined(__MTK_INTERNAL__) && !defined(LOW_COST_SUPPORT)
412
413
414
415#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_UART_REG_DBG__)
416#define DRV_UART_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
417#define DRV_UART_Reg(addr) DRV_DBG_Reg(addr)
418#define DRV_UART_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
419#define DRV_UART_Reg32(addr) DRV_DBG_Reg32(addr)
420#define DRV_UART_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
421#define DRV_UART_Reg8(addr) DRV_DBG_Reg8(addr)
422#define DRV_UART_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
423#define DRV_UART_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
424#define DRV_UART_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
425#define DRV_UART_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
426#define DRV_UART_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
427#define DRV_UART_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
428#define DRV_UART_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
429#define DRV_UART_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
430#define DRV_UART_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
431#else
432#define DRV_UART_WriteReg(addr,data) DRV_WriteReg(addr,data)
433#define DRV_UART_Reg(addr) DRV_Reg(addr)
434#define DRV_UART_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
435#define DRV_UART_Reg32(addr) DRV_Reg32(addr)
436#define DRV_UART_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
437#define DRV_UART_Reg8(addr) DRV_Reg8(addr)
438#define DRV_UART_ClearBits(addr,data) DRV_ClearBits(addr,data)
439#define DRV_UART_SetBits(addr,data) DRV_SetBits(addr,data)
440#define DRV_UART_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
441#define DRV_UART_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
442#define DRV_UART_SetBits32(addr,data) DRV_SetBits32(addr,data)
443#define DRV_UART_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
444#define DRV_UART_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
445#define DRV_UART_SetBits8(addr,data) DRV_SetBits8(addr,data)
446#define DRV_UART_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
447#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_UART_REG_DBG__)
448
449
450
451#define GDMA_BASE_ADDR BASE_ADDR_MDGDMA
452#define APGDMA_BASE_ADDR BASE_ADDR_APGDMA
453
454#if defined(__MD93__) ||defined(__MD95__)
455#define UART_HDMA_INTR_ID MD_IRQID_MDGDMA3
456#elif defined(MT6297)
457#define UART_HDMA_INTR_ID MD_IRQID_MDGDMA5
458#elif defined(MT6885) ||defined(__MD97P__) ||defined(MT6873) ||defined(MT6853)||defined(MT6893)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)
459#define UART_HDMA_INTR_ID MD_IRQID_MDGDMA_HDMA2_3
460#endif
461
462#define HDMA_BURST_SIZE_DEFAULT (HDMA_BURST_SIZE_16B)
463#define HDMA_DEV_BUS_WIDTH_DEFAULT (HDMA_DEV_BUS_WIDTH_1B)
464#define HDMA_MEM_BUS_WIDTH_DEFAULT (HDMA_MEM_BUS_WIDTH_4B)
465#define HDMA_MODE_DEFAULT (HDMA_BASIC_MODE)
466#define HDMA_CKSUM_EN_DEFAULT (HDMA_CKSUM_ON)
467#define HDMA_CKSUM_MODE_DEFAULT (HDMA_CKSUM_16B)
468
469/* HDMA registers */
470#define GDMA_HDCSR(_n) (GDMA_BASE_ADDR + 0x100 + (_n/2 * 0x4))
471#define GDMA_HDSR (GDMA_BASE_ADDR + 0x120)
472#define GDMA_HDCPR (GDMA_BASE_ADDR + 0x124)
473#define GDMA_HDCTRR(_n) (GDMA_BASE_ADDR + 0x140 + (_n * 0x20))
474#define GDMA_HDC0R(_n) (GDMA_BASE_ADDR + 0x144 + (_n * 0x20))
475#define GDMA_HDC1R(_n) (GDMA_BASE_ADDR + 0x148 + (_n * 0x20))
476#define GDMA_HPRGA0R(_n) (GDMA_BASE_ADDR + 0x14C + (_n * 0x20))
477#define GDMA_HPRGA1R(_n) (GDMA_BASE_ADDR + 0x150 + (_n * 0x20))
478#define GDMA_HCCR(_n) (GDMA_BASE_ADDR + 0x154 + (_n * 0x20))
479#define GDMA_HDCPRN(_n) (GDMA_BASE_ADDR + 0x158 + (_n * 0x20))
480#if defined(__MD93__)|| defined(__MD95__)
481#define GDMA_GISAR_UART (GDMA_BASE_ADDR + 0x60c) //GDMA_GISAR3
482#define GDMA_GIMRK_UART (GDMA_BASE_ADDR + 0x62c) //GDMA_GIMRK3
483#elif defined(__MD97__)||defined(__MD97P__)
484#define GDMA_GISAR_UART (GDMA_BASE_ADDR + 0x614) //GDMA_GISAR5
485#define GDMA_GIMRK_UART (GDMA_BASE_ADDR + 0x634) //GDMA_GIMRK5
486#endif
487#define APGDMA_HDCSR(_n) (APGDMA_BASE_ADDR + 0x100 + (_n/2 * 0x4))
488#define APGDMA_HDSR (APGDMA_BASE_ADDR + 0x120)
489#define APGDMA_HDCPR (APGDMA_BASE_ADDR + 0x124)
490#define APGDMA_HDCTRR(_n) (APGDMA_BASE_ADDR + 0x140 + (_n * 0x20))
491#define APGDMA_HDC0R(_n) (APGDMA_BASE_ADDR + 0x144 + (_n * 0x20))
492#define APGDMA_HDC1R(_n) (APGDMA_BASE_ADDR + 0x148 + (_n * 0x20))
493#define APGDMA_HPRGA0R(_n) (APGDMA_BASE_ADDR + 0x14C + (_n * 0x20))
494#define APGDMA_HPRGA1R(_n) (APGDMA_BASE_ADDR + 0x150 + (_n * 0x20))
495#define APGDMA_HCCR(_n) (APGDMA_BASE_ADDR + 0x154 + (_n * 0x20))
496#define APGDMA_HDCPRN(_n) (APGDMA_BASE_ADDR + 0x158 + (_n * 0x20))
497#define APGDMA_GISAR_UART (APGDMA_BASE_ADDR + 0x60C) //GDMA_GISAR3
498#define APGDMA_GIMRK_UART (APGDMA_BASE_ADDR + 0x62C) //GDMA_GIMRK3
499
500#define HDMA_START_BIT (0x1)
501#define HDMA_STOP_BIT (0x4)
502#define HDMA_RESUME_BIT (0x2)
503
504#define HDMA_STAT (0x1)
505#define HDMA_RX_SEL_MASK (0xC0000000)
506#define HDMA_CONFIG_MASK (0x3FFFF)
507#define HDMA_MODE_MASK(_n) (0xFFFF << (16 *(_n %2)))
508
509#define HDMA_INTR_CHL_MASK(_n) (1 << (_n -2))
510
511typedef enum{
512 HDMA_BURST_SIZE_4B = 2,
513 HDMA_BURST_SIZE_8B = 3,
514 HDMA_BURST_SIZE_16B = 4,
515 HDMA_BURST_SIZE_MAX,
516}drv_uart_hdma_burst_size_t;
517
518typedef enum{
519 HDMA_DEV_BUS_WIDTH_1B = 0,
520 HDMA_DEV_BUS_WIDTH_MAX,
521}drv_uart_hdma_dev_bus_width;
522
523typedef enum{
524 HDMA_MEM_BUS_WIDTH_1B = 0,
525 HDMA_MEM_BUS_WIDTH_2B = 1,
526 HDMA_MEM_BUS_WIDTH_4B = 2,
527 HDMA_MEM_BUS_WIDTH_MAX,
528}drv_uart_hdma_mem_bus_width;
529
530typedef enum{
531 HDMA_LIST_MODE = 0,
532 HDMA_BASIC_MODE = 1,
533 HDMA_DESCRIPTOR_MODE = 2,
534}drv_uart_hdma_mode;
535
536typedef enum{
537 HDMA_CKSUM_OFF = 0,
538 HDMA_CKSUM_ON = 1,
539}drv_uart_hdma_cksum_en;
540
541typedef enum{
542 HDMA_CKSUM_12B = 0,
543 HDMA_CKSUM_16B = 1,
544}drv_uart_hdma_cksum_mode;
545
546typedef enum{
547 UART_EN_Q = 0,
548 UART_DE_Q = 1,
549 UART_EN_Q_LIGHT = 2,
550 UART_DE_Q_ALL = 3,
551} drv_uart_en_q_or_de_q;
552
553typedef struct{
554 drv_uart_hdma_burst_size_t bst_size;
555 drv_uart_hdma_dev_bus_width dev_bus_width;
556 drv_uart_hdma_mem_bus_width mem_bus_width;
557 drv_uart_hdma_mode mode;
558 drv_uart_hdma_cksum_en cksum_en;
559 drv_uart_hdma_cksum_mode cksum_mode;
560}drv_uart_hdma_config_t;
561
562#define HDMA_CONFIG_INIT(_bst, _devbus, _membus, _mode, _cksum_en,_cksum) \
563 { _bst, _devbus, _membus, _mode, _cksum_en, _cksum}
564
565typedef enum{
566 GDMA_MODE_HDMA = 0,
567 GDMA_MODE_VDMA = 1,
568}drv_uart_gdma_mode;
569
570
571/* HDMA commands */
572#define HDMA_CONFIG_RX_SEL(_n, _v) \
573 DRV_WriteReg32(GDMA_HDCTRR(_n), (DRV_Reg32(GDMA_HDCTRR(_n))& ~HDMA_RX_SEL_MASK)|((_v)&0x3)<<30)
574#define HDMA_CONFIG(_n, _bst, _devbus, _membus) \
575 DRV_WriteReg32_NPW(GDMA_HDCTRR(_n), (DRV_Reg32(GDMA_HDCTRR(_n)) & ~HDMA_CONFIG_MASK) | (_bst << 12) |( _devbus << 6) |(_membus << 4))
576#define HDMA_MODE_CONFIG(_n, _cksum_en,_mode, _cksum) \
577 DRV_WriteReg32_NPW(GDMA_HDCSR(_n), (DRV_Reg32(GDMA_HDCSR(_n)) & ~(HDMA_MODE_MASK(_n))) |(_cksum_en << (15 + (16 *(_n %2))))| (_mode << (9 + (16 *(_n %2)))) |(_cksum << (8 + (16 *(_n %2)))))
578#define APHDMA_CONFIG(_n, _bst, _devbus, _membus) \
579 DRV_WriteReg32_NPW(APGDMA_HDCTRR(_n), (DRV_Reg32(APGDMA_HDCTRR(_n)) & ~HDMA_CONFIG_MASK) | (_bst << 13) |( _devbus << 6) |(_membus << 4))
580#define APHDMA_MODE_CONFIG(_n, _cksum_en,_mode, _cksum) \
581 DRV_WriteReg32_NPW(APGDMA_HDCSR(_n), (DRV_Reg32(APGDMA_HDCSR(_n)) & ~(HDMA_MODE_MASK(_n))) |(_cksum_en << (15 + (16 *(_n %2))))| (_mode << (9 + (16 *(_n %2)))) |(_cksum << (8 + (16 *(_n %2)))))
582
583
584#define HDMA_BUF0_XFER_SIZE_CONFIG(_n, _xfer) \
585 DRV_WriteReg32(GDMA_HDC0R(_n), (_xfer << 16))
586#define HDMA_BUF0_PROG_ADDR_CONFIG(_n, _addr) \
587 DRV_WriteReg32(GDMA_HPRGA0R(_n), _addr)
588#define HDMA_BUF0_START(_n) \
589 DRV_WriteReg32_NPW(GDMA_HDC0R(_n), DRV_Reg32(GDMA_HDC0R(_n)) | HDMA_START_BIT)
590#define HDMA_BUF0_RESUME(_n) \
591 DRV_WriteReg32_NPW(GDMA_HDC0R(_n), DRV_Reg32(GDMA_HDC0R(_n)) | HDMA_RESUME_BIT)
592#define HDMA_BUF0_STOP(_n) \
593 DRV_WriteReg32_NPW(GDMA_HDCTRR(_n), DRV_Reg32(GDMA_HDCTRR(_n)) | HDMA_STOP_BIT)
594#define HDMA_BUF0_IS_ACTIVE(_n) \
595 (DRV_Reg32(GDMA_HDSR) & (HDMA_STAT << (_n)))
596#define HDMA_CHANNEL_CUR_BUF(_n) \
597 ( (DRV_Reg32(GDMA_HDCPR) >> (_n)) & 0x1 )
598#define HDMA_INT_CLEAR_ALL() \
599 (DRV_WriteReg32(GDMA_GISAR_UART, 0xFFFFFFFF))
600
601#define APHDMA_BUF0_XFER_SIZE_CONFIG(_n, _xfer) \
602 DRV_WriteReg32_NPW(APGDMA_HDC0R(_n), (_xfer << 16))
603#define APHDMA_BUF0_PROG_ADDR_CONFIG(_n, _addr) \
604 DRV_WriteReg32_NPW(APGDMA_HPRGA0R(_n), _addr)
605#define APHDMA_BUF0_START(_n) \
606 DRV_WriteReg32(APGDMA_HDC0R(_n), DRV_Reg32(APGDMA_HDC0R(_n)) | HDMA_START_BIT)
607#define APHDMA_BUF0_RESUME(_n) \
608 DRV_WriteReg32(APGDMA_HDC0R(_n), DRV_Reg32(APGDMA_HDC0R(_n)) | HDMA_RESUME_BIT)
609#define APHDMA_BUF0_STOP(_n) \
610 DRV_WriteReg32(APGDMA_HDCTRR(_n), DRV_Reg32(APGDMA_HDCTRR(_n)) | HDMA_STOP_BIT)
611#define APHDMA_BUF0_IS_ACTIVE(_n) \
612 (DRV_Reg32(APGDMA_HDSR) & (HDMA_STAT << (_n)))
613#define APHDMA_CHANNEL_CUR_BUF(_n) \
614 ( (DRV_Reg32(APGDMA_HDCPR) >> (_n)) & 0x1 )
615#define APHDMA_INT_CLEAR_ALL() \
616 (DRV_WriteReg32(APGDMA_GISAR_UART, 0xFFFFFFFF))
617
618/* HDMA Interrupt Related Macros*/
619#define IS_HDMA_DONE_INTR(_val, _chl) \
620 ( _val & HDMA_INTR_CHL_MASK(_chl))
621#define IS_HDMA_QE_INTR(_val, _chl) \
622 ( _val & (HDMA_INTR_CHL_MASK(_chl) << 8))
623#define IS_HDMA_LENERR_INTR(_val, _chl) \
624 ( _val & (HDMA_INTR_CHL_MASK(_chl) << 16))
625#define IS_HDMA_BD_CSERR_INTR(_val, _chl) \
626 ( _val & (HDMA_INTR_CHL_MASK(_chl) << 24))
627#define IS_HDMA_GPD_CSERR_INTR(_val, _chl) \
628 ( _val & (HDMA_INTR_CHL_MASK(_chl) << 28))
629#define HDMA_INTR_MASK_ALL() \
630 (DRV_WriteReg32(GDMA_GIMRK_UART, 0xFFFFFFFF))
631#define HDMA_INTR_UNMASK_ALL() \
632 (DRV_WriteReg32(GDMA_GIMRK_UART, 0x0))
633#define HDMA_DONE_INTR_MASK(_chl) \
634 DRV_WriteReg32(GDMA_GIMRK_UART, DRV_Reg32(GDMA_GIMRK_UART) | HDMA_INTR_CHL_MASK(_chl))
635#define HDMA_DONE_INTR_UNMASK(_chl) \
636 DRV_WriteReg32(GDMA_GIMRK_UART, DRV_Reg32(GDMA_GIMRK_UART) & ~(HDMA_INTR_CHL_MASK(_chl)))
637#define HDMA_QE_INTR_MASK(_chl) \
638 DRV_WriteReg32(GDMA_GIMRK_UART, DRV_Reg32(GDMA_GIMRK_UART) | (HDMA_INTR_CHL_MASK(_chl) << 8))
639#define HDMA_QE_INTR_UNMASK(_chl) \
640 DRV_WriteReg32(GDMA_GIMRK_UART, DRV_Reg32(GDMA_GIMRK_UART) & ~((HDMA_INTR_CHL_MASK(_chl)) << 8))
641#define HDMA_LENERR_INTR_MASK(_chl) \
642 DRV_WriteReg32(GDMA_GIMRK_UART, DRV_Reg32(GDMA_GIMRK_UART) | (HDMA_INTR_CHL_MASK(_chl) << 16))
643#define HDMA_LENERR_INTR_UNMASK(_chl) \
644 DRV_WriteReg32(GDMA_GIMRK_UART, DRV_Reg32(GDMA_GIMRK_UART) & ~((HDMA_INTR_CHL_MASK(_chl)) << 16))
645#define HDMA_BD_CSERR_INTR_MASK(_chl) \
646 DRV_WriteReg32(GDMA_GIMRK_UART, DRV_Reg32(GDMA_GIMRK_UART) | (HDMA_INTR_CHL_MASK(_chl) << 24))
647#define HDMA_BD_CSERR_INTR_UNMASK(_chl) \
648 DRV_WriteReg32(GDMA_GIMRK_UART, DRV_Reg32(GDMA_GIMRK_UART) & ~((HDMA_INTR_CHL_MASK(_chl)) << 24))
649#define HDMA_GPD_CSERR_INTR_MASK(_chl) \
650 DRV_WriteReg32(GDMA_GIMRK_UART, DRV_Reg32(GDMA_GIMRK_UART) | (HDMA_INTR_CHL_MASK(_chl) << 28))
651#define HDMA_GPD_CSERR_INTR_UNMASK(_chl) \
652 DRV_WriteReg32(GDMA_GIMRK_UART, DRV_Reg32(GDMA_GIMRK_UART) & ~((HDMA_INTR_CHL_MASK(_chl)) << 28))
653
654// UART exception mode
655#define UART_ECPT_QBM_BPS_NUM 15
656#define UART_ECPT_QBM_BPS_BUF_SZ QBM_QUEUE_GET_MEM_SIZE(QBM_SIZE_TGPD_BPS, UART_ECPT_QBM_BPS_NUM)
657
658typedef struct _uart_bps_gpd{
659 void *bps_ptr[UART_ECPT_QBM_BPS_NUM];
660 kal_uint32 bps_cur_idx;
661 kal_uint32 remain_bps_gpd;
662} uart_bps_gpd_t;
663
664#endif
665