blob: c197502e7bde70780c58e4846ec2b6f305067111 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +08001/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * dcl_pmu6251_hw.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file is intended for PMIC 6251 driver.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
59 * removed!
60 * removed!
61 *
62 * removed!
63 * removed!
64 * removed!
65 *
66 * removed!
67 * removed!
68 * removed!
69 *
70 * removed!
71 * removed!
72 * removed!
73 *
74 * removed!
75 * removed!
76 * removed!
77 *
78 * removed!
79 * removed!
80 * removed!
81 *
82 * removed!
83 * removed!
84 * removed!
85 *
86 *------------------------------------------------------------------------------
87 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
88 *============================================================================
89 ****************************************************************************/
90
91#ifndef __PMU6252_HW_H__
92#define __PMU6252_HW_H__
93
94
95#if defined(PMIC_6252_REG_API)
96
97#define PMU_BASE MIXED_base
98#define PMU_END (PMU_BASE+0x1000)
99
100///////////////////////////////////////////////////////////////////////////////
101// LDO group
102#define VRF_CON0 (PMU_BASE + 0x0800)
103#define VTCXO_CON0 (PMU_BASE + 0x0810)
104#define VA_CON0 (PMU_BASE + 0x0820)
105#define VCAMA_CON0 (PMU_BASE + 0x0830)
106#define VCAMD_CON0 (PMU_BASE + 0x0840)
107#define VIO_CON0 (PMU_BASE + 0x0850)
108#define VUSB_CON0 (PMU_BASE + 0x0860)
109#define VSIM_CON0 (PMU_BASE + 0x0880)
110#define VSIM2_CON0 (PMU_BASE + 0x0890)
111#define VRTC_CON0 (PMU_BASE + 0x08A0)
112#define VIBR_CON0 (PMU_BASE + 0x08B0)
113#define VM_CON0 (PMU_BASE + 0x08C0)
114#define VCORE_CON0 (PMU_BASE + 0x08D0)
115
116// iSINK group
117#define ISINK0_CON0 (PMU_BASE + 0x0980)
118#define ISINK1_CON0 (PMU_BASE + 0x0990)
119#define ISINK2_CON0 (PMU_BASE + 0x09A0)
120#define ISINK3_CON0 (PMU_BASE + 0x09B0)
121
122// KPLED group
123#define KPLED_CON0 (PMU_BASE + 0x09C0)
124
125// SPK
126#define SPK_CON0 (PMU_BASE + 0x09D0)
127
128// CHR
129#define CHR_CON0 (PMU_BASE + 0x0A00)
130
131// STARTUP
132#define STRUP_CON0 (PMU_BASE + 0x0900)
133
134// INT EN
135#define INT_EN0 (PMU_BASE + 0x08F0)
136#define INT_EN1 (PMU_BASE + 0x08F4)
137#define INT_CHR_DET_MASK 0x0008
138#define INT_CHR_DET_SHIFT 3
139
140///////////////////////////////////////////////////////////////////////////////
141
142// BC11 VSRC_EN
143#define MT6251_E1_BC11_VSRC_EN_MASK 0x0030
144#define MT6251_E1_BC11_VSRC_EN_SHIFT 4
145
146
147#define CON0_OFFSET 0x00
148#define CON1_OFFSET 0x04
149#define CON2_OFFSET 0x08
150#define CON3_OFFSET 0x0C
151#define CON4_OFFSET 0x10
152#define CON5_OFFSET 0x14
153#define CON6_OFFSET 0x18
154#define CON7_OFFSET 0x1C
155#define CON8_OFFSET 0x20
156#define CON9_OFFSET 0x24
157
158// LDO and BUCK cmds
159#define LDO_BUCK_EN_OFFSET CON0_OFFSET
160#define LDO_BUCK_EN_MASK 0x0001
161#define LDO_BUCK_EN_SHIFT 0
162
163#define LDO_BUCK_RS_OFFSET CON0_OFFSET
164#define LDO_BUCK_RS_MASK 0x0004
165#define LDO_BUCK_RS_SHIFT 2
166
167#define LDO_BUCK_VOL_SEL_OFFSET CON0_OFFSET
168#define LDO_BUCK_VOL_SEL_MASK 0x01F0
169#define LDO_BUCK_VOL_SEL_SHIFT 4
170
171#define LDO_BUCK_OC_AUTO_OFF_OFFSET CON0_OFFSET
172#define LDO_BUCK_OC_AUTO_OFF_MASK 0x1000
173#define LDO_BUCK_OC_AUTO_OFF_SHIFT 12
174
175/*
176#define LDO_BUCK_STB_EN_OFFSET CON0_OFFSET
177#define LDO_BUCK_STB_EN_MASK 0x0800
178#define LDO_BUCK_STB_EN_SHIFT 11
179*/
180
181#define LDO_BUCK_ON_SEL_OFFSET CON0_OFFSET
182#define LDO_BUCK_ON_SEL_MASK 0x0002
183#define LDO_BUCK_ON_SEL_SHIFT 1
184
185
186#define LDO_BUCK_NDIS_EN_OFFSET CON0_OFFSET
187#define LDO_BUCK_NDIS_EN_MASK 0x0400
188#define LDO_BUCK_NDIS_EN_SHIFT 10
189
190/*
191#define LDO_BUCK_OCFB_EN_OFFSET CON0_OFFSET
192#define LDO_BUCK_OCFB_EN_MASK 0x2000
193#define LDO_BUCK_OCFB_EN_SHIFT 13
194*/
195
196// LDO cmds
197#define LDO_CAL_OFFSET CON1_OFFSET
198#define LDO_CAL_MASK 0x01F0
199#define LDO_CAL_SHIFT 4
200
201#define LDO_OC_TD_OFFSET CON2_OFFSET
202#define LDO_OC_TD_MASK 0x0030
203#define LDO_OC_TD_SHIFT 4
204
205#define LDO_STB_TD_OFFSET CON2_OFFSET
206#define LDO_STB_TD_MASK 0x00c0
207#define LDO_STB_TD_SHIFT 6
208
209
210// BUCK cmds
211#define BUCK_VFBADJ_SLEEP_OFFSET CON1_OFFSET
212#define BUCK_VFBADJ_SLEEP_MASK 0x01F0
213#define BUCK_VFBADJ_SLEEP_SHIFT 4
214
215#define BUCK_ICAL_EN_OFFSET CON3_OFFSET
216#define BUCK_ICAL_EN_MASK 0x3000
217#define BUCK_ICAL_EN_SHIFT 12
218
219/*
220#define BUCK_STB_TD_OFFSET CON3_OFFSET
221#define BUCK_STB_TD_MASK 0x00C0
222#define BUCK_STB_TD_SHIFT 6
223
224#define BUCK_OC_THD_OFFSET CON3_OFFSET
225#define BUCK_OC_THD_MASK 0x0300
226#define BUCK_OC_THD_SHIFT 8
227
228#define BUCK_CSL_OFFSET CON5_OFFSET
229#define BUCK_CSL_MASK 0x0700
230#define BUCK_CSL_SHIFT 8
231
232#define BUCK_BURST_OFFSET CON5_OFFSET
233#define BUCK_BURST_MASK 0x3000
234#define BUCK_BURST_SHIFT 12
235*/
236
237// SPK
238#define SPK_EN_OFFSET CON0_OFFSET
239#define SPK_EN_MASK 0x0001
240#define SPK_EN_SHIFT 0
241
242#define SPK_VOL_OFFSET CON0_OFFSET
243#define SPK_VOL_MASK 0x001E
244#define SPK_VOL_SHIFT 1
245
246#define SPK_OC_EN_OFFSET CON0_OFFSET
247#define SPK_OC_EN_MASK 0x0040
248#define SPK_OC_EN_SHIFT 6
249
250#define SPK_OC_THD_OFFSET CON1_OFFSET
251#define SPK_OC_THD_MASK 0x0003 // OC_TRG
252#define SPK_OC_THD_SHIFT 0
253
254#define SPK_OC_WND_OFFSET CON1_OFFSET
255#define SPK_OC_WND_MASK 0x000C
256#define SPK_OC_WND_SHIFT 2
257
258//ISINK
259#define ISINK_EN_OFFSET CON0_OFFSET
260#define ISINK_EN_MASK 0x0001
261#define ISINK_EN_SHIFT 0
262
263#define ISINK_MODE_OFFSET CON0_OFFSET
264#define ISINK_MODE_MASK 0x0002
265#define ISINK_MODE_SHIFT 1
266
267#define ISINK_STEP_OFFSET CON0_OFFSET
268#define ISINK_STEP_MASK 0x01F0
269#define ISINK_STEP_SHIFT 4
270
271#define ISINK_VREF_CAL_OFFSET CON1_OFFSET
272#define ISINK_VREF_CAL_MASK 0x1F00
273#define ISINK_VREF_CAL_SHIFT 8
274
275/*
276//BOOST
277#define BOOST_TYPE_OFFSET CON0_OFFSET
278#define BOOST_TYPE_MASK 0x0002
279#define BOOST_TYPE_SHIFT 1
280
281#define BOOST_HW_SEL_OFFSET CON6_OFFSET
282#define BOOST_HW_SEL_MASK 0x0001
283#define BOOST_HW_SEL_SHIFT 0
284*/
285
286//KPLED
287#define KPLED_EN_OFFSET CON0_OFFSET
288#define KPLED_EN_MASK 0x0001
289#define KPLED_EN_SHIFT 0
290
291#define KPLED_MODE_OFFSET CON0_OFFSET
292#define KPLED_MODE_MASK 0x0002
293#define KPLED_MODE_SHIFT 1
294
295#define KPLED_SEL_OFFSET CON0_OFFSET
296#define KPLED_SEL_MASK 0x0070
297#define KPLED_SEL_SHIFT 4
298
299
300//CHR
301#define CSDAC_EN_OFFSET CON0_OFFSET
302#define CSDAC_EN_MASK 0x0800
303#define CSDAC_EN_SHIFT 11
304
305#define CHR_EN_OFFSET CON0_OFFSET
306#define CHR_EN_MASK 0x1000
307#define CHR_EN_SHIFT 12
308
309#define CHRDET_OFFSET CON0_OFFSET
310#define CHRDET_MASK 0x2000
311#define CHRDET_SHIFT 13
312
313#define VCDT_HV_VTH_OFFSET CON0_OFFSET
314#define VCDT_HV_VTH_MASK 0x00F0
315#define VCDT_HV_VTH_SHIFT 4
316
317#define VCDT_HV_EN_OFFSET CON0_OFFSET
318#define VCDT_HV_EN_MASK 0x0100
319#define VCDT_HV_EN_SHIFT 8
320
321#define VBAT_CV_VTH_OFFSET CON1_OFFSET
322#define VBAT_CV_VTH_MASK 0x001F
323#define VBAT_CV_VTH_SHIFT 0
324
325#define VBAT_CV_EN_OFFSET CON1_OFFSET
326#define VBAT_CV_EN_MASK 0x0100
327#define VBAT_CV_EN_SHIFT 8
328
329#define VBAT_CV_DET_OFFSET CON1_OFFSET
330#define VBAT_CV_DET_MASK 0x4000
331#define VBAT_CV_DET_SHIFT 14
332
333#define CS_VTH_OFFSET CON2_OFFSET
334#define CS_VTH_MASK 0x0700
335#define CS_VTH_SHIFT 8
336
337#define BATON_HT_EN_OFFSET CON3_OFFSET
338#define BATON_HT_EN_MASK 0x0400
339#define BATON_HT_EN_SHIFT 10
340
341#define CSDAC_DLY_OFFSET CON3_OFFSET
342#define CSDAC_DLY_MASK 0x0030
343#define CSDAC_DLY_SHIFT 4
344
345#define CSDAC_STP_OFFSET CON3_OFFSET
346#define CSDAC_STP_MASK 0x0003
347#define CSDAC_STP_SHIFT 0
348
349#define BATON_UNDET_OFFSET CON3_OFFSET
350#define BATON_UNDET_MASK 0x8000
351#define BATON_UNDET_SHIFT 15
352
353#define OTG_BVALID_EN_OFFSET CON5_OFFSET
354#define OTG_BVALID_EN_MASK 0x1000
355#define OTG_BVALID_EN_SHIFT 12
356
357#define CHRWDT_EN_OFFSET CON6_OFFSET
358#define CHRWDT_EN_MASK 0x0010
359#define CHRWDT_EN_SHIFT 4
360
361#define CHRWDT_TD_OFFSET CON6_OFFSET
362#define CHRWDT_TD_MASK 0x000F // TTTTTTTTT
363#define CHRWDT_TD_SHIFT 0
364
365#define CHRWDT_OUT_OFFSET CON7_OFFSET
366#define CHRWDT_OUT_MASK 0x8000
367#define CHRWDT_OTU_SHIFT 15
368
369#define CHRWDT_INT_EN_OFFSET CON7_OFFSET
370#define CHRWDT_INT_EN_MASK 0x0001
371#define CHRWDT_INT_EN_SHIFT 0
372
373#define CHRWDT_FLAG_WR_OFFSET CON7_OFFSET
374#define CHRWDT_FLAG_WR_MASK 0x0002
375#define CHRWDT_FLAG_WR_SHIFT 1
376
377#define ADC_EN_OFFSET CON8_OFFSET
378#define ADC_EN_MASK 0x7000 // All ADC channels are enabled at same time
379#define ADC_EN_SHIFT 12
380
381#define BC11_VREF_VTH_OFFSET CON9_OFFSET
382#define BC11_VREF_VTH_MASK 0x0001
383#define BC11_VREF_VTH_SHIFT 0
384
385#define BC11_CMP_EN_OFFSET CON9_OFFSET
386#define BC11_CMP_EN_MASK 0x0006
387#define BC11_CMP_EN_SHIFT 1
388
389#define BC11_IPD_EN_OFFSET CON9_OFFSET
390#define BC11_IPD_EN_MASK 0x0018
391#define BC11_IPD_EN_SHIFT 3
392
393#define BC11_IPU_EN_OFFSET CON9_OFFSET
394#define BC11_IPU_EN_MASK 0x0060
395#define BC11_IPU_EN_SHIFT 5
396
397#define BC11_BIAS_EN_OFFSET CON9_OFFSET
398#define BC11_BIAS_EN_MASK 0x0080
399#define BC11_BIAS_EN_SHIFT 7
400
401#define BC11_BB_CTRL_OFFSET CON9_OFFSET
402#define BC11_BB_CTRL_MASK 0x0100
403#define BC11_BB_CTRL_SHIFT 8
404
405#define BC11_RST_OFFSET CON9_OFFSET
406#define BC11_RST_MASK 0x0200
407#define BC11_RST_SHIFT 9
408
409#define BC11_VSRC_EN_OFFSET CON9_OFFSET
410#define BC11_VSRC_EN_MASK 0x0C00
411#define BC11_VSRC_EN_SHIFT 10
412
413#define BC11_CMP_OUT_OFFSET CON9_OFFSET
414#define BC11_CMP_OUT_MASK 0x8000
415#define BC11_CMP_OUT_SHIFT 15
416
417
418// STRUP
419// STRUP_XXX CON0
420#define USBDL_EN_OFFSET CON0_OFFSET
421#define USBDL_EN_MASK 0x0010
422#define USBDL_EN_SHIFT 4
423
424/*
425// BOOST
426#define BOOST_CKS_PRG_OFFSET CON3_OFFSET
427#define BOOST_CKS_PRG_MASK 0x003F
428#define BOOST_CKS_PRG_SHIFT 0
429*/
430
431//MISC
432#define CCI_SRCLKEN_OFFSET CON2_OFFSET
433#define CCI_SRCLKEN_MASK 0x0002
434#define CCI_SRCLKEN_SHIFT 1
435
436#endif // #if defined(PMIC_6252_REG_API)
437
438#endif // #ifndef __PMU6252_HW_H__