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192.168.1.100 / T800_MD / 0b80c7188a6089ae59f523c5d460adad05960e1d / . / mcu / driver / peripheral / inc / uart_internal.h
blob: 5128c68f93ff88ec5259276eb285bdb2dc257a1a [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2001
8*
9*****************************************************************************/
10
11/*****************************************************************************
12 *
13 * Filename:
14 * ---------
15 * dcl_uart.h
16 *
17 * Project:
18 * --------
19 * Maui
20 *
21 * Description:
22 * ------------
23 * Header file of DCL (Driver Common Layer) for UART.
24 *
25 * Author:
26 * -------
27 * -------
28 *
29 *============================================================================
30 * HISTORY
31 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
32 *------------------------------------------------------------------------------
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125 *
126 *------------------------------------------------------------------------------
127 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
128 *============================================================================
129 ****************************************************************************/
130#ifndef __UART_INTERNAL_H__
131#define __UART_INTERNAL_H__
132
133#include "uart_sw.h"
134#include "dcl.h"
135
136#include "kal_general_types.h"
137#include "drv_comm.h"
138//#include "btif_sw.h"
139
140typedef enum {
141 UART_ON_VFIFO,
142 UART_ON_DMA,
143 UART_ON_MCU,
144 UART_ON_UNKNOWN
145} UART_WORKING_MODE;
146
147#define UART_STAT_EscDet 0x01
148#define UART_STAT_Break 0x02
149
150#define UART_RecNormal 0
151#define UART_Get3EscChar 1
152#define UART_StartCheckESC 2
153
154//Size = 8bit, sinc en, dinc disable, hw management,
155//1 trans/dma cycle, UART1 master,Interrupt enable
156#define DMA_CON_UART1TxNormal 0x8034
157//Size = 8bit, sinc disable, dinc enable, hw management,
158//1 trans/dma cycle, UART1 master,Interrupt enable
159#define DMA_CON_UART1RxNormal 0x8038
160//Size = 8bit, sinc en, dinc disable, hw management,
161//1 trans/dma cycle, UART2 master,Interrupt enable
162#define DMA_CON_UART2TxNormal 0x8054
163//Size = 8bit, sinc disable, dinc enable, hw management,
164//1 trans/dma cycle, UART2 master,Interrupt enable
165#define DMA_CON_UART2RxNormal 0x8058
166
167
168
169/*TY adds these to expand flexibility 2004/10/15*/
170typedef void (*UART_TX_FUNC)(UART_PORT port);
171typedef void (*UART_RX_FUNC)(UART_PORT port) ;
172
173
174typedef struct
175{
176 UART_PORT port_no;
177 kal_bool initialized;
178 kal_bool power_on;
179 module_type ownerid;
180 module_type UART_id;
181 kal_bool breakDet;
182 kal_bool EscFound;
183 UARTDCBStruct DCB;
184 UART_RingBufferStruct RingBuffers;
185 UART_ESCDetectStruct ESCDet;
186 BUFFER_INFO Tx_Buffer_ISR; /* receive buffer */
187 BUFFER_INFO Rx_Buffer; /* receive buffer */
188 BUFFER_INFO Tx_Buffer; /* transmit buffer */
189 kal_hisrid hisr;
190 IO_level DSR;
191 /*detect Escape*/
192 DCL_HANDLE handle; /*GPT handle*/
193#if defined(DRV_UART_COMPENSATE_AT)
194 UART_Compensate_enum CompensateAT;
195#endif
196 kal_uint8 EscCount;
197 kal_uint8 Rec_state; /**/
198 UART_SLEEP_ON_TX sleep_on_tx;
199 kal_bool EnableTX;
200 /*TY adds these to expand flexibility 2004/10/15*/
201 UART_TX_FUNC tx_cb;
202 UART_RX_FUNC rx_cb;
203 //#ifdef __DMA_UART_VIRTUAL_FIFO__
204 kal_uint8 Rx_DMA_Ch;
205 kal_uint8 Tx_DMA_Ch;
206 //#endif
207
208#if defined(DRV_UART_VFIFO_V2)
209#if defined(DRV_UART_VFIFO_V2_USE_GPT)
210 DCL_HANDLE uart_flush_timer_handle; /*GPT handle*/
211 DCL_HANDLE uart_isr_flush_timer_handle; /*GPT handle*/
212#else
213 kal_timerid uart_flush_timer_id;
214#endif //DRV_UART_VFIFO_V2_USE_GPT
215#endif /* defined(DRV_UART_VFIFO_V1) */
216
217} UARTStruct;
218
219// for uart dispatch table
220typedef enum
221{
222 UART_TYPE = 0,
223 IRDA_TYPE,
224 USB_TYPE,
225 BLUETOOTH_TYPE,
226 CMUX_TYPE
227}UartType_enum;
228
229typedef struct _uartdriver
230{
231
232 kal_bool (*Open)(UART_PORT port, module_type ownerid);
233 void (*Close)(UART_PORT port, module_type ownerid);
234 kal_uint16 (*GetBytes)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, kal_uint8 *status, module_type ownerid);
235 kal_uint16 (*PutBytes)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
236 kal_uint16 (*GetRxAvail)(UART_PORT port);
237 kal_uint16 (*GetTxAvail)(UART_PORT port);
238 kal_uint16 (*PutISRBytes)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
239 kal_uint16 (*GetISRTxAvail)(UART_PORT port);
240 void (*Purge)(UART_PORT port, UART_buffer dir, module_type ownerid);
241 //void (*SetOwner)(UART_PORT port, kal_uint8 ownerid);
242 void (*SetOwner)(UART_PORT port, module_type ownerid);
243 void (*SetFlowCtrl)(UART_PORT port, kal_bool XON, module_type ownerid);
244 void (*ConfigEscape)(UART_PORT port, kal_uint8 EscChar, kal_uint16 ESCGuardtime, module_type ownerid);
245 void (*SetDCBConfig)(UART_PORT port, UARTDCBStruct *UART_Config, module_type ownerid);
246 void (*CtrlDCD)(UART_PORT port, IO_level SDCD, module_type ownerid);
247 void (*CtrlBreak)(UART_PORT port, IO_level SBREAK, module_type ownerid);
248 void (*ClrRxBuffer)(UART_PORT port, module_type ownerid);
249 void (*ClrTxBuffer)(UART_PORT port, module_type ownerid);
250 void (*SetBaudRate)(UART_PORT port, UART_baudrate baudrate, module_type ownerid);
251 kal_uint16 (*SendISRData)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode, kal_uint8 escape_char, module_type ownerid);
252 kal_uint16 (*SendData)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid);
253 module_type (*GetOwnerID)(UART_PORT port);
254 void (*SetAutoBaud_Div)(UART_PORT port, module_type ownerid);
255 /*TY adds these to expand flexibility 2004/10/15*/
256 void (*UART_Register_TX_cb)(UART_PORT port, module_type ownerid, UART_TX_FUNC func);
257 void (*UART_Register_RX_cb)(UART_PORT port, module_type ownerid, UART_RX_FUNC func);
258 /*TY adds these to let virtual COM port can retrive exception log 2005/3/8*/
259 kal_uint8 (*GetUARTByte)(UART_PORT port);
260 void (*PutUARTByte)(UART_PORT port, kal_uint8 data);
261 void (*PutUARTBytes)(UART_PORT port, kal_uint8 *data, kal_uint16 len);
262 /*for virtual com port to return DCB configuration*/
263 void (*ReadDCBConfig)(UART_PORT port, UARTDCBStruct *UART_Config);
264 void (*CtrlRI)(UART_PORT port, IO_level SRI, module_type ownerid);
265 void (*CtrlDTR)(UART_PORT port, IO_level SDTR, module_type ownerid);
266 void (*ReadHWStatus)(UART_PORT port, IO_level *SDSR, IO_level *SCTS);
267 kal_uint8 (*GetUARTByte_WithTimeOut)(UART_PORT port, kal_uint8* ch, kal_uint32 timeout_value);
268}UartDriver_strcut;
269
270/*Function Declaration*/
271extern UartDriver_strcut UartDriver;
272
273#if defined(__DMA_UART_VFIFO_SINGLE_TUNNEL__)
274extern kal_bool UART_SINGLE_VFIFO_support[MAX_UART_TUNNEL_NUM] ; //toy add for single tunnel vfifo
275extern kal_bool UART_IsVfifoSetting(UART_PORT port, UART_TxRx_VFIFO_support vs);
276#ifdef __DMA_UART_VIRTUAL_FIFO__
277extern UartDriver_strcut UartDriver_VFIFO;
278extern UartDriver_strcut UartDriver_VFIFO_RX;
279extern UartDriver_strcut UartDriver_VFIFO_TX;
280#endif
281#else
282extern kal_bool UART_VFIFO_support[MAX_UART_PORT_NUM];
283#ifdef __DMA_UART_VIRTUAL_FIFO__
284extern UartDriver_strcut UartDriver_VFIFO;
285#endif
286#endif
287
288extern UartDriver_strcut* pUart_CMD_FUNC[];
289
290
291#if defined(DRV_UART_COMPENSATE_AT)
292extern void UART_CompensateAT(UART_PORT port);
293extern void UART_CheckAT_Callback(void *parameter);
294#endif //#if defined(DRV_UART_COMPENSATE_AT)
295
296extern void UART1_PDN_ENABLE(void);
297extern void UART1_PDN_DISABLE(void);
298extern void UART2_PDN_ENABLE(void);
299extern void UART2_PDN_DISABLE(void);
300#ifdef __UART3_SUPPORT__
301extern void UART3_PDN_ENABLE(void);
302extern void UART3_PDN_DISABLE(void);
303#endif //#ifdef __UART3_SUPPORT__
304
305/*ISR handler for VFIFO*/
306extern void UART_RecTimeOutHandler(UART_PORT port);
307extern void UART_TrxHandler_VFIFO(UART_PORT port);
308extern void UART_RecHandler_VFIFO(UART_PORT port);
309extern void UART_THRE_hdr_VFIFO(UART_PORT port);
310/*API for VFIFO*/
311extern void U_configure_DMA_VFIFO(void);
312extern kal_uint16 U_GetTxISRRoomLeft_VFIFO(UART_PORT port);
313extern kal_uint16 U_GetTxRoomLeft_VFIFO(UART_PORT port);
314extern kal_uint16 U_GetBytesAvail_VFIFO(UART_PORT port);
315extern kal_uint8 U_GetUARTByte_VFIFO(UART_PORT port);
316extern void U_PutUARTByte_VFIFO(UART_PORT port, kal_uint8 data);
317extern void PutUARTData_VFIFO(UART_PORT port, kal_uint8 escape_char, kal_uint8 data);
318extern kal_uint16 U_GetBytes_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, kal_uint8 *status, module_type ownerid);
319extern kal_uint16 U_PutBytes_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
320extern kal_uint16 U_PutISRBytes_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
321extern kal_uint16 U_SendData_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid);
322extern kal_uint16 U_SendISRData_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid);
323extern kal_bool UART_UseVFIFO(UART_PORT port, kal_bool use_vfifo);
324
325extern void UART_DriverInit(UART_PORT port,kal_uint32 flag);
326extern void UART_Boot_Trace_Release(kal_bool flag);//for bootup trace
327
328extern void UART_set_FIFO_trigger(UART_PORT port, kal_uint16 tx_level, kal_uint16 rx_level);
329
330#ifdef __UART3_SUPPORT__
331 extern void UART3_HISR(void);
332 extern void UART3_LISR(void);
333#endif /*MT6218*/
334// for Uart Dispatch
335//extern void UART_Register(UART_PORT port, UartType_enum type, UartDriver_strcut* drv);
336
337/* Note: for ROM code start */
338#ifdef __ROMSA_SUPPORT__
339/*for mcu rom*/
340extern kal_uint16 U_GetTxISRRoomLeft(UART_PORT port);
341extern kal_uint16 U_PutISRBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
342extern kal_uint16 U_ROM_GetTxISRRoomLeft(UART_PORT port);
343extern UARTStruct *U_ROM_GetUARTPort(UART_PORT port);
344extern kal_uint8 *U_ROM_GetUART_TXilm(UART_PORT port);
345extern void U_ROM_InformUARTOwner(UART_PORT port);
346extern void U_ROM_PushDataToBuf(UART_PORT port, kal_uint8 *data, kal_uint32 real_count);
347extern void U_ROM_EnableTxIntr(UART_PORT port);
348//extern void DRVPDN_Disable(kal_uint32 addr,kal_uint16 code,kal_uint8 handle);
349#endif
350/* Note: for ROM code end */
351
352// Used under ASSERT condition
353// This has effect only when the port does NOT support VFIFO and used as Catcher port
354extern void UART_AssertWaitPrevDataSentOut(UART_PORT port);
355
356
357extern kal_bool UART1DMA_Ini(kal_bool Tx);
358extern kal_bool UART2DMA_Ini(kal_bool Tx);
359extern kal_uint8 GetUARTByte(UART_PORT port);
360extern void PutUARTByte(UART_PORT port, kal_uint8 data);
361extern void UART_SetBaudRate(UART_PORT port, UART_baudrate baud_rate, module_type ownerid);
362extern void UART_SetDCBConfig(UART_PORT port, UARTDCBStruct *UART_Config, module_type ownerid);
363extern void UART_ReadDCBConfig (UART_PORT port, UARTDCBStruct *DCB);
364extern void UART_loopback(UART_PORT port);
365extern void UART_HWInit(UART_PORT port);
366extern kal_bool UART_Open(UART_PORT port, module_type ownerid);
367extern void UART_Close(UART_PORT port, module_type ownerid);
368//extern void UART_SetOwner (UART_PORT port, kal_uint8 ownerid);
369extern void UART_SetOwner (UART_PORT port, module_type ownerid);
370extern void UART_ConfigEscape (UART_PORT port, kal_uint8 EscChar, kal_uint16 ESCGuardtime, module_type ownerid);
371extern void UART_CtrlDTR (UART_PORT port, IO_level SDTR, module_type ownerid);
372extern void UART_ReadHWStatus(UART_PORT port, IO_level *SDSR, IO_level *SCTS);
373extern void UART_CtrlBreak(UART_PORT port, IO_level SBREAK, module_type ownerid);
374extern void UART_Purge(UART_PORT port, UART_buffer dir, module_type ownerid);
375extern void UART_Register_RX_cb(UART_PORT port, module_type ownerid, UART_RX_FUNC func);
376extern void UART_Register_TX_cb(UART_PORT port, module_type ownerid, UART_TX_FUNC func);
377extern void UART_PDN_Disable(UART_PORT port);
378extern void UART_PDN_Enable(UART_PORT port);
379
380
381//API for single tunnel VFIFO
382extern kal_uint16 U_GetBytesAvail(UART_PORT port);
383extern kal_uint16 U_GetBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, kal_uint8 *status, module_type ownerid);
384extern kal_uint8 U_GetUARTByte(UART_PORT port);
385extern kal_uint16 U_PutBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid );
386extern kal_uint16 U_GetTxRoomLeft(UART_PORT port);
387extern kal_uint16 U_SendISRData(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode, kal_uint8 escape_char, module_type ownerid);
388extern kal_uint16 U_SendData(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid);
389extern void U_PutUARTByte(UART_PORT port, kal_uint8 data);
390
391extern void UART_Boot_PutUARTBytes(UART_PORT port, kal_uint8 *data,kal_uint16 len);
392extern void UART_Bootup_Init(void);
393extern kal_uint16 UART_GetBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, kal_uint8 *status, module_type ownerid);
394extern kal_uint16 UART_PutBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
395extern kal_uint16 UART_PutISRBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
396extern kal_uint16 UART_SendISRData(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode, kal_uint8 escape_char, module_type ownerid);
397extern kal_uint16 UART_SendData(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid );
398extern void UART_SetFlowCtrl(UART_PORT port, kal_bool XON, module_type ownerid);
399extern void UART_CtrlDCD(UART_PORT port, IO_level SDCD, module_type ownerid);
400extern void UART_CtrlRI (UART_PORT port, IO_level SRI, module_type ownerid);
401extern kal_uint16 UART_GetBytesAvail(UART_PORT port);
402extern void UART_SleepOnTx_Enable(UART_PORT port, UART_SLEEP_ON_TX enable_flag);
403extern void UART_SetSleepEnable(kal_bool enable);
404extern void UART_SwitchPort(UART_PORT *APP_port, UART_PORT new_uart_port);
405extern void UART_dafault_tx_cb(UART_PORT port);
406extern void UART_dafault_rx_cb(UART_PORT port);
407extern void UART_TurnOnPower(UART_PORT port, kal_bool enable);
408extern kal_bool UART_CheckTxBufferEmpty(UART_PORT port);
409extern kal_bool UART_CheckTxAllSentOut(UART_PORT port);
410extern void UART_GetTxBufferSize(UART_PORT port, kal_uint32 *total_size, kal_uint32 *rest_size);
411extern void UART1_HISR(void);
412extern void UART2_HISR(void);
413extern void UART1_LISR(void);
414extern void UART2_LISR(void);
415extern kal_bool uart_support_autoescape(void);
416extern void UART_VFIFO_TX_DMA_Enable(UART_PORT port,kal_bool enable);
417extern void UART_dsp_dafault_rx_cb(UART_PORT port);
418extern void UART_dsp_dafault_tx_cb(UART_PORT port);
419extern kal_uint32 UART_Get_Maxbaudrate(UART_PORT port);
420
421
422
423/*end of local parameter struct */
424#define EnableRxIntr(_baseaddr) \
425{\
426 kal_uint32 _savedMask;\
427 kal_uint16 _IER;\
428 _savedMask = SaveAndSetIRQMask();\
429 _IER = DRV_Reg(UART_IER(_baseaddr));\
430 _IER |= (UART_IER_ERBFI | UART_IER_ELSI);\
431 DRV_WriteReg(UART_IER(_baseaddr),_IER);\
432 RestoreIRQMask(_savedMask);\
433}
434
435#define DisableRxIntr(_baseaddr) \
436{\
437 kal_uint16 _IER;\
438 kal_uint32 _savedMask;\
439 _savedMask = SaveAndSetIRQMask();\
440 _IER = DRV_Reg(UART_IER(_baseaddr));\
441 _IER &= ~(UART_IER_ERBFI|UART_IER_ELSI);\
442 DRV_WriteReg(UART_IER(_baseaddr),_IER);\
443 RestoreIRQMask(_savedMask);\
444}
445
446
447#define EnableTxIntr(_baseaddr) \
448{\
449 kal_uint16 _IER;\
450 kal_uint32 _savedMask;\
451 _savedMask = SaveAndSetIRQMask();\
452 _IER = DRV_Reg(UART_IER(_baseaddr));\
453 _IER |= UART_IER_ETBEI;\
454 DRV_WriteReg(UART_IER(_baseaddr),_IER);\
455 RestoreIRQMask(_savedMask);\
456}
457
458#define DisableTxIntr(_baseaddr) \
459{\
460 kal_uint16 _IER;\
461 kal_uint32 _savedMask;\
462 _savedMask = SaveAndSetIRQMask();\
463 _IER = DRV_Reg(UART_IER(_baseaddr));\
464 _IER &= ~UART_IER_ETBEI;\
465 DRV_WriteReg(UART_IER(_baseaddr),_IER);\
466 RestoreIRQMask(_savedMask);\
467}
468
469#define UART_SetDMAIntr(_baseaddr) \
470{\
471 kal_uint16 _IER;\
472 kal_uint32 _savedMask;\
473 _savedMask = SaveAndSetIRQMask();\
474 _IER = DRV_Reg(UART_IER(_baseaddr));\
475 _IER &= ~(UART_IER_ETBEI);\
476 DRV_WriteReg(UART_IER(_baseaddr),_IER);\
477 RestoreIRQMask(_savedMask);\
478}
479
480#define DisableRLSIntr(_baseaddr) \
481{\
482 kal_uint16 _IER;\
483 kal_uint32 _savedMask;\
484 _savedMask = SaveAndSetIRQMask();\
485 _IER = DRV_Reg(UART_IER(_baseaddr));\
486 _IER &= ~(UART_IER_ELSI);\
487 DRV_WriteReg(UART_IER(_baseaddr),_IER);\
488 RestoreIRQMask(_savedMask);\
489}
490
491
492extern UART_WORKING_MODE UART_GetTxWorkingMode(UART_PORT port);
493
494#if defined(__MTK_INTERNAL__) && !defined(__MAUI_BASIC__) && defined(__DRV_DBG_MEMORY_TRACE_SUPPORT__)
495#define DRV_UART_MEMORY_TRACE
496typedef struct{
497 kal_uint16 tag;
498 kal_uint32 time;
499 kal_uint32 data1;
500 kal_uint32 data2;
501}UART_DRV_DBG_DATA;
502#define MAX_UART_DRV_DBG_INFO_SIZE 512
503typedef struct{
504 UART_DRV_DBG_DATA dbg_data[MAX_UART_DRV_DBG_INFO_SIZE];
505 kal_uint16 dbg_data_idx;
506}UART_DRV_DBG_STRUCT;
507extern void uart_drv_dbg_trace(kal_uint16 index, kal_uint32 time, kal_uint32 data1, kal_uint32 data2);
508#define UART_DBG(a,b,c,d) uart_drv_dbg_trace(a,b,c,d);
509#include "us_timer.h"
510extern kal_uint32 L1I_GetTimeStamp(void);
511#define UART_GetTimeStamp L1I_GetTimeStamp
512#else //#if defined(__MTK_INTERNAL__) && !defined(LOW_COST_SUPPORT)
513#define UART_DBG(a,b,c,d) ;
514#endif //#if defined(__MTK_INTERNAL__) && !defined(LOW_COST_SUPPORT)
515
516
517#if defined(__SSDVT_TEST__) /* add for SSDVT , make sure that UART init Value is satisfied for DVT's need */
518#define DRV_UART_WriteReg(addr,data)
519#define DRV_UART_Reg(addr) DRV_Reg(addr)
520#define DRV_UART_WriteReg32(addr,data)
521#define DRV_UART_Reg32(addr) DRV_Reg32(addr)
522#define DRV_UART_WriteReg8(addr,data)
523#define DRV_UART_Reg8(addr) DRV_Reg8(addr)
524#define DRV_UART_ClearBits(addr,data)
525#define DRV_UART_SetBits(addr,data)
526#define DRV_UART_SetData(addr, bitmask, value)
527#define DRV_UART_ClearBits32(addr,data)
528#define DRV_UART_SetBits32(addr,data)
529#define DRV_UART_SetData32(addr, bitmask, value)
530#define DRV_UART_ClearBits8(addr,data)
531#define DRV_UART_SetBits8(addr,data)
532#define DRV_UART_SetData8(addr, bitmask, value)
533#elif defined(__DRV_COMM_REG_DBG__) && defined(__DRV_UART_REG_DBG__) /*normal case */
534#define DRV_UART_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
535#define DRV_UART_Reg(addr) DRV_DBG_Reg(addr)
536#define DRV_UART_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
537#define DRV_UART_Reg32(addr) DRV_DBG_Reg32(addr)
538#define DRV_UART_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
539#define DRV_UART_Reg8(addr) DRV_DBG_Reg8(addr)
540#define DRV_UART_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
541#define DRV_UART_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
542#define DRV_UART_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
543#define DRV_UART_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
544#define DRV_UART_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
545#define DRV_UART_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
546#define DRV_UART_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
547#define DRV_UART_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
548#define DRV_UART_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
549#else
550#define DRV_UART_WriteReg(addr,data) DRV_WriteReg(addr,data)
551#define DRV_UART_Reg(addr) DRV_Reg(addr)
552#define DRV_UART_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
553#define DRV_UART_Reg32(addr) DRV_Reg32(addr)
554#define DRV_UART_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
555#define DRV_UART_Reg8(addr) DRV_Reg8(addr)
556#define DRV_UART_ClearBits(addr,data) DRV_ClearBits(addr,data)
557#define DRV_UART_SetBits(addr,data) DRV_SetBits(addr,data)
558#define DRV_UART_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
559#define DRV_UART_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
560#define DRV_UART_SetBits32(addr,data) DRV_SetBits32(addr,data)
561#define DRV_UART_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
562#define DRV_UART_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
563#define DRV_UART_SetBits8(addr,data) DRV_SetBits8(addr,data)
564#define DRV_UART_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
565#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_UART_REG_DBG__)
566
567
568#endif
569