Gitiles
Code Review Sign In
192.168.1.100 / T800_MD / 0b80c7188a6089ae59f523c5d460adad05960e1d / . / mcu / interface / driver / hwdrv / sccb_v2.h_
blob: 53481b80b6cb68c50ae77219ae751cbddbf226d6 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * sccb_v2.h
41 *
42 *
43 * Description:
44 * ------------
45 * SCCB/I2C V2 Driver
46 *
47 * Author:
48 * -------
49 * Scott Hung (mtk01235)
50 *
51 *============================================================================
52 * HISTORY
53 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
54 *------------------------------------------------------------------------------
55 * $Revision: $
56 * $Modtime: $
57 * $Log: $
58 *
59 * 04 24 2012 wcpuser_integrator
60 * [MAUI_03155806] [MSBB2] Global Revise Clear and Uniform Legacy Header File Inclusion Requested by JI Huang
61 * .
62 *
63 * 11 30 2010 guoxin.hong
64 * [MAUI_02841708] [Drv] MAUI HAL Peripheral Create
65 * .
66 *
67 * 11 23 2010 shuang.han
68 * [MAUI_02840976] [HAL][Drv] driver feature option files merge back to MAUI
69 * .
70 *
71 * 10 18 2010 shuang.han
72 * [MAUI_02637814] [RHR][MAUIW1038OF_RHR] Integration to W10.43
73 * .
74 *
75 * May 19 2010 mtk01845
76 * [MAUI_02529366] [Drv] I2C patch for MT6236 sanity failed
77 *
78 *
79 * May 15 2010 mtk02787
80 * [MAUI_02524954] I2C "write then read" fail
81 *
82 *
83 * May 6 2010 mtk02787
84 * [MAUI_02416501] add function definition in sccb_v2.h to avoid build warning
85 *
86 *
87 * Apr 15 2010 mtk02787
88 * [MAUI_02397396] I2C V1 phase out
89 *
90 *
91 * Apr 14 2010 mtk02787
92 * [MAUI_02392155] [MEUT] Check in driver on/off function to Maui
93 *
94 *
95 * Mar 31 2010 mtk02787
96 * [MAUI_02385929] I2C DMA mode
97 *
98 *
99 * Feb 22 2010 mtk01845
100 * [MAUI_02360180] [Drv][I2C] I2C driver revision for new DMA architecture from MT6276
101 *
102 *
103 * Feb 20 2010 mtk01845
104 * [MAUI_02360180] [Drv][I2C] I2C driver revision for new DMA architecture from MT6276
105 *
106 *
107 * Oct 12 2009 mtk01845
108 * [MAUI_01963866] [Drv][I2C] sccb.h define I2C pins
109 *
110 *
111 * May 9 2009 mtk01845
112 * [MAUI_01319629] [Drv] MEUT check in
113 *
114 *
115 * Jan 12 2009 mtk01845
116 * [MAUI_01307296] MT6235 charger constant current CC6 and CC7 change to internal use
117 *
118 *
119 * Nov 6 2008 mtk01845
120 * [MAUI_01269587] [Drv] MT6253T merge back to MAUI
121 *
122 *
123 * Jun 21 2008 mtk01845
124 * [MAUI_00791553] [Drv] MT6268A merge DVT code back to MAUI
125 *
126 *
127 * Jun 20 2008 mtk01845
128 * [MAUI_00791553] [Drv] MT6268A merge DVT code back to MAUI
129 *
130 *
131 * Apr 22 2008 mtk01845
132 * [MAUI_00760971] [Drv][MoDIS] Add driver API functions into MoDIS dummy driver
133 *
134 *
135 * Nov 9 2007 mtk01283
136 * [MAUI_00573819] [Drv][Compile option] Check in MT6235 compile option to Maui
137 *
138 *
139 * Aug 6 2007 mtk01283
140 * [MAUI_00529681] [Drv] Remove compile warning in driver codes
141 *
142 *
143 * Mar 19 2007 mtk01235
144 * [MAUI_00359681] [Drv][Compile Option] Add MT6223 and MT6223P compile option
145 *
146 *
147 * Jan 30 2007 MTK01235
148 * [MAUI_00363041] [Drv]Driver Feature Management
149 *
150 *
151 * Nov 20 2006 MTK01235
152 * [MAUI_00338437] [I2C] Check in I2C/SCCB V2 driver
153 *
154 *
155 * Oct 25 2006 mtk01235
156 * [MAUI_00338437] [I2C] Check in I2C/SCCB V2 driver
157 *
158 *------------------------------------------------------------------------------
159 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
160 *============================================================================
161 *****************************************************************************/
162#ifndef __SCCB_V2_H__
163#define __SCCB_V2_H__
164
165
166#include "drv_features_i2c.h"
167
168#if (defined(DRV_I2C_25_SERIES))
169//#if (defined(MT6225))
170
171#include "sccb.h"
172#include "intrCtrl.h"
173#include "drv_comm.h"
174#include "sccb_v2_custom.h"
175#define SCCB_OWNER_HEADER_FILE_INCLUDED
176
177//MSBB remove #include "kal_non_specific_general_types.h"
178#include "reg_base.h"
179
180
181#ifndef __DRV_DEBUG_I2C_REG_READ_WRITE__
182#define DRV_I2C_ClearBits16(addr, data) DRV_ClearBits(addr,data)
183#define DRV_I2C_SetBits16(addr, data) DRV_SetBits(addr,data)
184#define DRV_I2C_WriteReg16(addr, data) DRV_WriteReg(addr, data)
185#define DRV_I2C_ReadReg16(addr) DRV_Reg(addr)
186#define DRV_I2C_SetData16(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
187#else // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
188#define DRV_I2C_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
189#define DRV_I2C_SetBits16(addr) DRV_DBG_SetBits(addr)
190#define DRV_I2C_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
191#define DRV_I2C_ReadReg16(addr) DRV_DBG_Reg(addr)
192#define DRV_I2C_SetData16(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
193#endif // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
194
195#define I2C_MODULE_FIFO_DEPTH 8
196
197
198#define SCCB_MAXIMUM_TRANSACTION_LENGTH 8 // SCCB backward compatible
199
200
201#if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
202#define SCCB_CLOCK_RATE 15360 //15.36MHz
203#elif defined(DRV_I2C_CLOCK_RATE_3_000_MHZ)
204#define SCCB_CLOCK_RATE 3000 //3.0MHz
205#else // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
206#define SCCB_CLOCK_RATE 13000 //13MHz
207#endif // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
208
209
210
211#if defined(__MEUT__)
212#define I2C_V2_DVT
213#endif // #if defined(__MEUT__)
214
215#ifdef I2C_V2_DVT
216 #if !defined(DRV_I2C_DMA_ENABLED)
217 #define DRV_I2C_DMA_ENABLED //Only used in DVT
218 #endif // #if !defined(DRV_I2C_DMA_ENABLED)
219#endif // #ifdef I2C_V2_DVT
220
221#if (defined(DRV_I2C_DMA_ENABLED))
222#include "dma_hw.h"
223#endif // #if (defined(DRV_I2C_DMA_ENABLED))
224
225// Some common structures are defined in sccb.h
226
227typedef enum
228{
229 SCCB_TRANSACTION_COMPLETE,
230 SCCB_TRANSACTION_FAIL
231}SCCB_TRANSACTION_RESULT;
232
233
234typedef enum
235{
236 SCCB_READY_STATE,
237 SCCB_BUSY_STATE
238}SCCB_STATE;
239
240/* Transaction mode for new SCCB APIs */
241typedef enum
242{
243 SCCB_TRANSACTION_FAST_MODE,
244 SCCB_TRANSACTION_HIGH_SPEED_MODE
245}SCCB_TRANSACTION_MODE;
246
247typedef enum
248{
249#if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
250 // Module source clock is 15.36Mhz
251 SCCB_100KB, //99.74KB
252 SCCB_200KB, //196.9KB
253 SCCB_300KB, //295.4KB
254 SCCB_400KB, //384.0KB
255 /* HS Mode */
256 SCCB_960KB, //960.0KB
257 SCCB_1280KB, //1280.0KB
258 SCCB_1536KB, //1536.0KB
259 SCCB_1920KB, //1920.0KB
260 SCCB_2560KB, //2560.0KB
261 SCCB_3840KB //3840.0KB
262#elif defined(DRV_I2C_CLOCK_RATE_3_000_MHZ)
263 // Module source clock is 3.0Mhz
264 SCCB_100KB, //100.0KB
265 SCCB_200KB, //196.9KB
266 SCCB_400KB, //384.0KB
267 /* HS Mode */
268 SCCB_750KB, //750.0KB
269 SCCB_1500KB //1500.0KB
270#else // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
271 // Module source clock is 13Mhz
272 SCCB_100KB, //101.5KB
273 SCCB_200KB, //203.1KB
274 SCCB_300KB, //295.5KB
275 SCCB_400KB, //382.4KB
276 /* HS Mode */
277 SCCB_460KB, //464.3KB
278 SCCB_540KB, //541.7KB
279 SCCB_650KB, //650.0KB
280 SCCB_720KB, //722.0KB
281
282 SCCB_810KB, //812.5KB
283 SCCB_930KB, //928.6KB
284 SCCB_1100KB, //1083.3KB
285 SCCB_1300KB, //1300.0KB
286 SCCB_1625KB, //1625.0KB
287 SCCB_2150KB, //2166.6KB
288 SCCB_3250KB //3250.6KB
289#endif // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
290}SCCB_SPEED_ENUM;
291
292typedef struct
293{
294 kal_uint8 sccb_mode; // Transaction mode for existing SCCB APIs
295
296 kal_bool get_handle_wait; //When get handle wait until the sccb is avaliable
297
298 kal_uint8 slave_address; //the address of the slave device
299
300 kal_uint8 delay_len; //number of half pulse between transfers in a trasaction
301
302 SCCB_TRANSACTION_MODE transaction_mode; //SCCB_TRANSACTION_FAST_MODE or SCCB_TRANSACTION_HIGH_SPEED_MODE
303
304 kal_uint32 Fast_Mode_Speed; //The speed of sccb fast mode(Kb)
305
306 kal_uint32 HS_Mode_Speed; //The speed of sccb high speed mode(Kb)
307
308 #if (defined(DRV_I2C_DMA_ENABLED))
309 kal_bool is_DMA_enabled; //Transaction via DMA instead of 8-byte FIFO
310 #endif // #if (defined(DRV_I2C_DMA_ENABLED))
311
312}sccb_config_struct;
313
314typedef struct
315{
316 sccb_config_struct sccb_config;
317
318 kal_uint8 fs_sample_cnt_div; //these two parameters are used to specify sccb clock rate
319 kal_uint8 fs_step_cnt_div; //half pulse width=step_cnt_div*sample_cnt_div*(1/13Mhz)
320
321 kal_uint8 hs_sample_cnt_div; //these two parameters are used to specify sccb clock rate
322 kal_uint8 hs_step_cnt_div; //half pulse width=step_cnt_div*sample_cnt_div*(1/13Mhz)
323
324 SCCB_TRANSACTION_RESULT transaction_result; /* The result of the end of transaction
325 (SCCB_TRANSACTION_COMPLETE|SCCB_TRANSACTION_FAIL) */
326
327}sccb_handle_struct;
328
329typedef struct
330{
331 volatile SCCB_STATE state;
332 kal_uint8 owner;
333
334 kal_uint8 number_of_read;
335 kal_uint8* read_buffer;
336
337 #if (defined(DRV_I2C_DMA_ENABLED))
338 kal_bool is_DMA_enabled;
339 #endif // #if (defined(DRV_I2C_DMA_ENABLED))
340
341}sccb_status_struct;
342
343
344#if defined(__SUPPORT_SCCB_XXX_API__)
345
346#if(defined(DRV_GPIO_6223_SERIES))
347 // Need to check the history
348 // When platform is 6223, without __CUST_NEW__
349 // The SCL and SDA in sccb.h is 15, 19
350 // In spec, the SCL, SDA is 45, 46
351 #if defined(SCCB_SERIAL_CLK_PIN)
352 // It means someone include sccb_v2.h
353 // Driver should use the SCL, SDA defined in sccb_v2.h
354 #undef SCCB_SERIAL_CLK_PIN
355 #undef SCCB_SERIAL_DATA_PIN
356 #undef SCCB_GPIO_SCL_MODE
357 #undef SCCB_GPIO_SDA_MODE
358 #endif // #if defined(SCCB_SERIAL_CLK_PIN)
359
360 #define SCCB_SERIAL_CLK_PIN 45
361 #define SCCB_SERIAL_DATA_PIN 46
362 #define SCCB_GPIO_SCL_MODE 3
363 #define SCCB_GPIO_SDA_MODE 3
364#endif // #if(defined(DRV_GPIO_6223_SERIES))
365
366#endif // #if defined(__SUPPORT_SCCB_XXX_API__)
367
368 #ifndef DRV_I2C_OFF
369/* Register Definitions */
370#define REG_I2C_DATA_PORT (I2C_base + 0x00)
371#define REG_I2C_SLAVE_ADDR (I2C_base + 0x04)
372#define REG_I2C_INT_MASK (I2C_base + 0x08)
373#define REG_I2C_INT_STA (I2C_base + 0x0c)
374#define REG_I2C_CONTROL (I2C_base + 0x10)
375#define REG_I2C_TRANSFER_LEN (I2C_base + 0x14)
376#define REG_I2C_TRANSAC_LEN (I2C_base + 0x18)
377#define REG_I2C_DELAY_LEN (I2C_base + 0x1c)
378#define REG_I2C_TIMING (I2C_base + 0x20)
379#define REG_I2C_START (I2C_base + 0x24)
380#define REG_I2C_FIFO_STAT (I2C_base + 0x30)
381#define REG_I2C_FIFO_THRESH (I2C_base + 0x34)
382#define REG_I2C_FIFO_ADDR_CLR (I2C_base + 0x38)
383#define REG_I2C_IO_CONFIG (I2C_base + 0x40)
384#define REG_I2C_MULTI_MASTER (I2C_base + 0x44)
385#define REG_I2C_HS_MODE (I2C_base + 0x48)
386#define REG_I2C_SOFTRESET (I2C_base + 0x50)
387#endif // DRV_I2C_OFF
388
389/* Register masks */
390#define I2C_1_BIT_MASK 0x01
391#define I2C_3_BIT_MASK 0x07
392#define I2C_4_BIT_MASK 0x0f
393#define I2C_6_BIT_MASK 0x3f
394#define I2C_8_BIT_MASK 0xff
395
396#define I2C_RX_FIFO_THRESH_MASK 0x0007
397#define I2C_RX_FIFO_THRESH_SHIFT 0
398#define I2C_TX_FIFO_THRESH_MASK 0x0700
399#define I2C_TX_FIFO_THRESH_SHIFT 8
400
401#define I2C_AUX_LEN_MASK 0x1f00
402#define I2C_AUX_LEN_SHIFT 8
403
404#define I2C_SAMPLE_CNT_DIV_MASK 0x0700
405#define I2C_SAMPLE_CNT_DIV_SHIFT 8
406#define I2C_DATA_READ_TIME_MASK 0x7000
407#define I2C_DATA_READ_TIME_SHIFT 12
408
409#define I2C_MASTER_READ 0x01
410#define I2C_MASTER_WRITE 0x00
411
412//#define I2C_CTL_MODE_BIT 0x01
413#define I2C_CTL_RS_STOP_BIT 0x02
414#define I2C_CTL_DMA_EN_BIT 0x04
415#define I2C_CTL_CLK_EXT_EN_BIT 0x08
416#define I2C_CTL_DIR_CHANGE_BIT 0x10
417#define I2C_CTL_ACK_ERR_DET_BIT 0x20
418#define I2C_CTL_TRANSFER_LEN_CHG_BIT 0x40
419
420#define I2C_DATA_READ_ADJ_BIT 0x8000
421
422#define I2C_SCL_MODE_BIT 0x01
423#define I2C_SDA_MODE_BIT 0x02
424#define I2C_BUS_DETECT_EN_BIT 0x04
425
426#define I2C_ARBITRATION_BIT 0x01
427#define I2C_CLOCK_SYNC_BIT 0x02
428#define I2C_BUS_BUSY_DET_BIT 0x04
429
430#define I2C_HS_EN_BIT 0x01
431#define I2C_HS_NACK_ERR_DET_EN_BIT 0x02
432#define I2C_HS_MASTER_CODE_MASK 0x0070
433#define I2C_HS_MASTER_CODE_SHIFT 4
434#define I2C_HS_STEP_CNT_DIV_MASK 0x0700
435#define I2C_HS_STEP_CNT_DIV_SHIFT 8
436#define I2C_HS_SAMPLE_CNT_DIV_MASK 0x7000
437#define I2C_HS_SAMPLE_CNT_DIV_SHIFT 12
438
439/* I2C Status */
440#define I2C_FIFO_FULL_STATUS 0x01
441#define I2C_FIFO_EMPTY_STATUS 0x02
442
443/* Register Settings */
444#define SET_I2C_SLAVE_ADDRESS(n,rw) do{DRV_I2C_SetData16(REG_I2C_SLAVE_ADDR, I2C_8_BIT_MASK, (((n>>1)<<1) + rw));} while(0);
445
446#define DISABLE_I2C_INT do{DRV_I2C_WriteReg16(REG_I2C_INT_MASK, 0);} while(0);
447#define ENABLE_I2C_INT do{DRV_I2C_WriteReg16(REG_I2C_INT_MASK,I2C_1_BIT_MASK);} while(0);
448
449#define CLEAR_I2C_STA do{DRV_I2C_WriteReg16(REG_I2C_INT_STA, I2C_4_BIT_MASK);} while(0);
450
451//#define SET_I2C_FAST_SPEED_MODE REG_I2C_CONTROL &= ~I2C_CTL_MODE_BIT;
452//#define SET_I2C_HIGH_SPEED_MODE REG_I2C_CONTROL |= I2C_CTL_MODE_BIT;
453
454#define SET_I2C_ST_BETWEEN_TRANSFER do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_RS_STOP_BIT);} while(0);
455#define SET_I2C_RS_BETWEEN_TRANSFER do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_RS_STOP_BIT);} while(0);
456#define ENABLE_I2C_DMA_TRANSFER do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_DMA_EN_BIT);} while(0);
457#define ENABLE_I2C_CLOCK_EXTENSION do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_CLK_EXT_EN_BIT);} while(0);
458#define ENABLE_I2C_DIR_CHANGE do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_DIR_CHANGE_BIT);} while(0);
459#define ENABLE_I2C_ACK_ERR_DET do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_ACK_ERR_DET_BIT);} while(0);
460#define ENABLE_I2C_TRANSFER_LEN_CHG do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_TRANSFER_LEN_CHG_BIT);} while(0);
461
462#define DISABLE_I2C_DMA_TRANSFER do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_DMA_EN_BIT);} while(0);
463#define DISABLE_I2C_CLOCK_EXTENSION do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_CLK_EXT_EN_BIT);} while(0);
464#define DISABLE_I2C_DIR_CHANGE do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_DIR_CHANGE_BIT);} while(0);
465#define DISABLE_I2C_ACK_ERR_DET do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_ACK_ERR_DET_BIT);} while(0);
466#define DISABLE_I2C_TRANSFER_LEN_CHG do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_TRANSFER_LEN_CHG_BIT);} while(0);
467
468#define SET_I2C_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_8_BIT_MASK, (n));} while(0);
469#define SET_I2C_AUX_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_AUX_LEN_MASK, ((n)<<I2C_AUX_LEN_SHIFT));} while(0);
470
471#define SET_I2C_TRANSACTION_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSAC_LEN, I2C_8_BIT_MASK, (n));} while(0);
472#define SET_I2C_DELAY_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_DELAY_LEN, I2C_8_BIT_MASK, (n));} while(0);
473
474#define SET_I2C_STEP_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_6_BIT_MASK, (n));} while(0);
475#define SET_I2C_SAMPLE_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_SAMPLE_CNT_DIV_MASK, ((n)<<I2C_SAMPLE_CNT_DIV_SHIFT));} while(0);
476#define SET_I2C_DATA_READ_TIME(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_DATA_READ_TIME_MASK, ((n)<<I2C_DATA_READ_TIME_SHIFT));} while(0);
477#define ENABLE_I2C_DATA_READ_ADJ do{DRV_I2C_SetBits16(REG_I2C_TIMING, I2C_DATA_READ_ADJ_BIT);} while(0);
478#define DISABLE_I2C_DATA_READ_ADJ do{DRV_I2C_ClearBits16(REG_I2C_TIMING, I2C_DATA_READ_ADJ_BIT);} while(0);
479
480#define START_I2C_TRANSACTION do{DRV_I2C_WriteReg16(REG_I2C_START, 0x01);} while(0);
481
482// #define I2C_FIFO_FULL ((REG_I2C_FIFO_STAT>>1)&0x01)
483// #define I2C_FIFO_EMPTY (REG_I2C_FIFO_STAT & 0x01)
484
485#define SET_I2C_RX_FIFO_THRESH(n) do{DRV_I2C_SetData16(REG_I2C_FIFO_THRESH, I2C_RX_FIFO_THRESH_MASK, ((n)<< I2C_RX_FIFO_THRESH_SHIFT));} while(0);
486#define SET_I2C_TX_FIFO_THRESH(n) do{DRV_I2C_SetData16(REG_I2C_FIFO_THRESH, I2C_TX_FIFO_THRESH_MASK, ((n)<< I2C_TX_FIFO_THRESH_SHIFT));} while(0);
487
488#define CLEAR_I2C_FIFO do{DRV_I2C_WriteReg16(REG_I2C_FIFO_ADDR_CLR, 0x01);} while(0);
489
490#define SET_I2C_SCL_NORMAL_MODE do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_SCL_MODE_BIT);} while(0);
491#define SET_I2C_SCL_WIRED_AND_MODE do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_SCL_MODE_BIT);} while(0);
492#define SET_I2C_SDA_NORMAL_MODE do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_SDA_MODE_BIT);} while(0);
493#define SET_I2C_SDA_WIRED_AND_MODE do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_SDA_MODE_BIT);} while(0);
494#define ENABLE_I2C_BUS_DETECT do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_BUS_DETECT_EN_BIT);} while(0);
495#define DISABLE_I2C_BUS_DETECT do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_BUS_DETECT_EN_BIT);} while(0);
496
497#define ENABLE_I2C_CLOCK_SYNC do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_ARBITRATION_BIT);} while(0);
498#define ENABLE_DATA_ARBITION do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_CLOCK_SYNC_BIT);} while(0);
499#define ENABLE_I2C_BUS_BUSY_DET do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_BUS_BUSY_DET_BIT);} while(0);
500#define DISABLE_I2C_CLOCK_SYNC do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_ARBITRATION_BIT);} while(0);
501#define DISABLE_DATA_ARBITION do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_CLOCK_SYNC_BIT);} while(0);
502#define DISABLE_I2C_BUS_BUSY_DET do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_BUS_BUSY_DET_BIT);} while(0);
503
504#define SET_I2C_HIGH_SPEED_MODE_800KB do{DRV_I2C_WriteReg16(REG_I2C_HS_MODE, 0x0703);} while(0);
505#define SET_I2C_HIGH_SPEED_MODE_1000KB do{DRV_I2C_WriteReg16(REG_I2C_HS_MODE, 0x0503);} while(0);
506
507#define SET_I2C_FAST_MODE do{DRV_I2C_ClearBits16(REG_I2C_HS_MODE, I2C_HS_EN_BIT);} while(0);
508#define SET_I2C_HS_MODE do{DRV_I2C_SetBits16(REG_I2C_HS_MODE, I2C_HS_EN_BIT);} while(0);
509#define ENABLE_I2C_NAKERR_DET do{DRV_I2C_SetBits16(REG_I2C_HS_MODE, I2C_HS_NACK_ERR_DET_EN_BIT);} while(0);
510#define DISABLE_I2C_NAKERR_DET do{DRV_I2C_ClearBits16(REG_I2C_HS_MODE, I2C_HS_NACK_ERR_DET_EN_BIT);} while(0);
511#define SET_I2C_HS_MASTER_CODE(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_MASTER_CODE_MASK, ((n)<<I2C_HS_MASTER_CODE_SHIFT));} while(0);
512
513#define SET_I2C_HS_STEP_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_STEP_CNT_DIV_MASK, ((n)<<I2C_HS_STEP_CNT_DIV_SHIFT));} while(0);
514#define SET_I2C_HS_SAMPLE_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_SAMPLE_CNT_DIV_MASK, ((n)<<I2C_HS_SAMPLE_CNT_DIV_SHIFT));} while(0);
515
516#define RESET_I2C do{DRV_I2C_WriteReg16(REG_I2C_SOFTRESET, 0x01);} while(0);
517
518//---------------- DMA ----------------
519#if defined(DRV_I2C_DIRECT_CONFIG_DMA_REGISTER)
520
521//#define DMA_base 0x80030000 -->defined in /inc/reg_base.h
522
523/* Regidter Definitions */
524#define REG_DMA_CHANNEL_CONTROL(c) *((volatile unsigned int *) (DMA_base + 0x14+ (c<<8)))
525#define REG_DMA_CHANNEL_START(c) *((volatile unsigned int *) (DMA_base + 0x18+ (c<<8)))
526#define REG_DMA_PROG_ADDR(c) *((volatile unsigned int *) (DMA_base + 0x2c+ (c<<8)))
527#define REG_DMA_TRANSFER_COUNT(c) *((volatile unsigned int *) (DMA_base + 0x10+ (c<<8)))
528
529/* Master Definitions*/
530#define DMA_MASTER_I2C_TX DMA_CON_MASTER_I2CTX
531#define DMA_MASTER_I2C_RX DMA_CON_MASTER_I2CRX
532#define DMA_MASTER_IRDA_TX 0x02
533#define DMA_MASTER_IRDA_RX 0x03
534
535#define DMA_I2C_TX_CHANNEL 4
536#define DMA_I2C_RX_CHANNEL 5
537
538/* Register masks */
539#define DMA_CON_DIR_MASK 0x40000
540#define DMA_CON_MAS_MASK 0x01f00000
541
542#define I2C_SET_TX_DMA_CONTROL(c,m) REG_DMA_CHANNEL_CONTROL(c) = 0x00000014;\
543 REG_DMA_CHANNEL_CONTROL(c) |= (((m)<<20) & DMA_CON_MAS_MASK);
544
545#define I2C_SET_RX_DMA_CONTROL(c,m) REG_DMA_CHANNEL_CONTROL(c) = 0x00040018;\
546 REG_DMA_CHANNEL_CONTROL(c) |= (((m)<<20) & DMA_CON_MAS_MASK);
547
548#define I2C_SET_DMA_PROGRAMMABLE_ADDR(c,addr) REG_DMA_PROG_ADDR(c) = (addr);
549#define I2C_SET_DMA_TRANSFER_COUNT(c,size) REG_DMA_TRANSFER_COUNT(c)= size ;
550#define I2C_START_DMA_TRANSFER(c) REG_DMA_CHANNEL_START(c) = 0x8000;
551#define I2C_STOP_DMA_TRANSFER(c) REG_DMA_CHANNEL_START(c) = 0;
552
553#endif // #if defined(DRV_I2C_DIRECT_CONFIG_DMA_REGISTER)
554
555/****** SW definitions******/
556#define I2C_READ_BIT 0x01
557#define I2C_WRITE_BIT 0x00
558
559#define I2C_TRANSAC_COMPLETE 0x01
560#define I2C_TRANSAC_ACK_ERR 0x02
561#define I2C_HS_NACK_ERR 0x04
562
563void i2c_init(void);
564void i2c_set_transaction_speed(SCCB_OWNER owner,SCCB_TRANSACTION_MODE mode,kal_uint32* Fast_Mode_Speed,kal_uint32* HS_Mode_Speed);
565void i2c_config(SCCB_OWNER owner,sccb_config_struct* para);
566void i2c_set_slave_address(SCCB_OWNER owner,kal_uint8 slave_address);
567void i2c_set_get_handle_wait(SCCB_OWNER owner,kal_bool enable);
568SCCB_TRANSACTION_MODE i2c_get_transaction_mode(SCCB_OWNER owner);
569SCCB_TRANSACTION_RESULT i2c_write(SCCB_OWNER owner,kal_uint8* para,kal_uint32 datalen);
570SCCB_TRANSACTION_RESULT i2c_read(SCCB_OWNER owner,kal_uint8* para,kal_uint32 datalen);
571SCCB_TRANSACTION_RESULT i2c_cont_write(SCCB_OWNER owner, kal_uint8* para, kal_uint32 datalen_in_transfer, kal_uint32 transfer_num);
572SCCB_TRANSACTION_RESULT i2c_cont_read(SCCB_OWNER owner, kal_uint8* para, kal_uint32 datalen_in_transfer, kal_uint32 transfer_num);
573SCCB_TRANSACTION_RESULT i2c_write_and_read(SCCB_OWNER owner, kal_uint8* write_buffer, kal_uint32 write_len, kal_uint8* read_buffer, kal_uint32 read_len);
574#if (defined(DRV_I2C_DMA_ENABLED))
575void i2c_set_DMA(SCCB_OWNER owner, kal_bool enable);
576#endif // #if (defined(DRV_I2C_DMA_ENABLED))
577
578#if defined(DRV_I2C_25_SERIES)
579#if defined(__SUPPORT_SCCB_XXX_API__)
580void sccb_write(SCCB_OWNER owner,kal_uint32 cmd, kal_uint32 param);
581void sccb_multi_write(SCCB_OWNER owner,kal_uint32 cmd, kal_uint32 *param, kal_uint8 num);
582void sccb_cont_write(SCCB_OWNER owner,kal_uint32 cmd, kal_uint32 spec_cmd, kal_uint32 param);
583kal_uint32 sccb_read (SCCB_OWNER owner,kal_uint32 cmd);
584kal_uint32 sccb_phase3_read (SCCB_OWNER owner,kal_uint32 cmd);
585kal_uint32 sccb_cont_read (SCCB_OWNER owner,kal_uint32 cmd, kal_uint32 spec_cmd);
586kal_uint8 sccb_multi_read (SCCB_OWNER owner, kal_uint32 cmd, kal_uint32 *param, kal_uint8 num);
587#endif // #if defined(__SUPPORT_SCCB_XXX_API__)
588#endif // #if defined(DRV_I2C_25_SERIES)
589
590
591
592
593#endif // #if (defined(DRV_I2C_25_SERIES))
594
595#endif // #ifndef __SCCB_V2_H__
596