Gitiles
Code Review Sign In
192.168.1.100 / T800_MD / 0b80c7188a6089ae59f523c5d460adad05960e1d / . / mcu / interface / driver / peripheral / adc.h
blob: a8002155c2f41185a007a917ea70d2b44b082906 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * adc.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file is intends for GPT driver.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
59 * removed!
60 * removed!
61 *
62 * removed!
63 * removed!
64 * removed!
65 *
66 * removed!
67 * removed!
68 * removed!
69 *
70 * removed!
71 * removed!
72 * removed!
73 *
74 * removed!
75 * removed!
76 * removed!
77 *
78 * removed!
79 * removed!
80 * removed!
81 *
82 * removed!
83 * removed!
84 * removed!
85 *
86 * removed!
87 * removed!
88 * removed!
89 *
90 * removed!
91 * removed!
92 * removed!
93 *
94 * removed!
95 * removed!
96 * removed!
97 *
98 * removed!
99 * removed!
100 * removed!
101 *
102 * removed!
103 * removed!
104 * removed!
105 *
106 * removed!
107 * removed!
108 * removed!
109 *
110 * removed!
111 * removed!
112 * removed!
113 *
114 * removed!
115 * removed!
116 * removed!
117 *
118 * removed!
119 * removed!
120 * removed!
121 *
122 * removed!
123 * removed!
124 * removed!
125 *
126 * removed!
127 * removed!
128 * removed!
129 *
130 * removed!
131 * removed!
132 * removed!
133 *
134 * removed!
135 * removed!
136 * removed!
137 *
138 * removed!
139 * removed!
140 * removed!
141 *
142 * removed!
143 * removed!
144 * removed!
145 *
146 * removed!
147 * removed!
148 * removed!
149 *
150 * removed!
151 * removed!
152 * removed!
153 *
154 * removed!
155 * removed!
156 * removed!
157 *
158 * removed!
159 * removed!
160 * removed!
161 *
162 * removed!
163 * removed!
164 * removed!
165 * removed!
166 * removed!
167 * removed!
168 * removed!
169 * removed!
170 * removed!
171 * removed!
172 * removed!
173 * removed!
174 * removed!
175 * removed!
176 * removed!
177 * removed!
178 * removed!
179 * removed!
180 * removed!
181 * removed!
182 * removed!
183 * removed!
184 * removed!
185 * removed!
186 * removed!
187 * removed!
188 * removed!
189 * removed!
190 * removed!
191 * removed!
192 * removed!
193 * removed!
194 * removed!
195 * removed!
196 * removed!
197 * removed!
198 * removed!
199 * removed!
200 * removed!
201 * removed!
202 * removed!
203 * removed!
204 * removed!
205 * removed!
206 * removed!
207 * removed!
208 * removed!
209 * removed!
210 * removed!
211 * removed!
212 * removed!
213 * removed!
214 * removed!
215 * removed!
216 * removed!
217 * removed!
218 * removed!
219 * removed!
220 * removed!
221 * removed!
222 * removed!
223 * removed!
224 * removed!
225 * removed!
226 * removed!
227 * removed!
228 *
229 *------------------------------------------------------------------------------
230 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
231 *============================================================================
232 ****************************************************************************/
233#ifndef _ADC_H
234#define _ADC_H
235
236//#include "adc_hw.h"
237//#include "adc_sw.h"
238//#include "adc_channel.h" //remove this when check in MAUI. remind UEM not use ADC_VBAT
239
240//#include "drv_features.h"
241//#include "adc_channel.h"
242//
243//typedef enum {
244// vbat_adc_channel=0,
245// visense_adc_channel,
246// vbattmp_adc_channel,
247// battype_adc_channel,
248// vcharger_adc_channel,
249// pcbtmp_adc_channel,
250// aux_adc_channel,
251// chr_usb_adc_channel,
252// otg_vbus_adc_channel,
253// rftmp_adc_channel
254//} adc_channel_type;
255//
256///*
257//1. Check bit of ADC (1b), *(0x80000020)[18]=[210]
258//2. ADC_B (6b), *(0x80000020)[17:12]=[209:204]
259//3. ADC_A (7b), *(0x80000020)[11:5]=[203:197]
260//*/
261//#define EFUSE_ADC_BASE 0x80000020
262//#define EFUSE_ADC_A 0x80000020
263//#define EFUSE_ADC_B 0x80000020
264//#define EFUSE_ADC_ENABLE 0x40000
265//#define EFUSE_ADC_A_MASK 0xFE0
266//#define EFUSE_ADC_B_MASK 0x3F000
267//#define EFUSE_ADC_A_SHIFT 5
268//#define EFUSE_ADC_B_SHIFT 12
269//
270//
271//#if defined(DRV_ADC_LIMIT_REG) || defined(FPGA)
272//#if !defined(DRV_ADC_OFF)
273// /*******************
274// * GPADC Registers *
275// *******************/
276// #define AUXADC_DATA (AUXADC_base+0x0000) /* Sampled data */
277// #define AUXADC_CTRL (AUXADC_base+0x0004) /* Control of A/D Converter */
278// #define AUXADC_STAT (AUXADC_base+0x0008) /* A/D Status..reg=0,if write AUXADC_CTRL reg*/
279// #define AUXADC_CTRL2 (AUXADC_base+0x000c) /* Special Control of A/D Converter */
280//
281// #define AUXADC_STAT_RDY 0x0001 /*ADC ready*/
282//
283// #define AUXADC_CTRL2_CALI 0x0001 /*ADC Calibration*/
284// #define AUXADC_CTRL2_MON 0x0020 /*DACMON*/
285// #define AUXADC_CTRL2_BYP 0x0040 /*DACBYP*/
286//#endif // #if !defined(DRV_ADC_OFF)
287//
288// /*ADC pin selection, ADC phy. channel*/
289//
290// #define ADC_MAX_CHANNEL 5
291// #define ADC_ERR_CHANNEL_NO 50
292//#endif /*(DRV_ADC_LIMIT_REG,FPGA)*/
293///*************************************************************************/
294//#if defined(DRV_ADC_BASIC_REG)
295//#if !defined(DRV_ADC_OFF)
296// #define AUXADC_SYNC (AUXADC_base+0x0000)
297// #define AUXADC_IMM (AUXADC_base+0x0004)
298// #define AUXADC_SYN (AUXADC_base+0x0008)
299// #define AUXADC_CON (AUXADC_base+0x000c)
300// #define AUXADC_DAT(_line) (AUXADC_base+0x0010+(4*_line))
301//
302// /*AUXADC_SYNC*/
303// #define AUXADC_SYNC_CHAN(_line) (0x0001<<_line) /*Time event 1*/
304//
305// /*AUXADC_IMM*/
306// #define AUXADC_IMM_CHAN(_line) (0x0001<<_line)
307//
308// /*AUXADC_SYN*/
309// #define AUXADC_SYN_BIT (0x0001) /*Time event 0*/
310//
311// /*AUXADC_CON*/
312// #define AUXADC_CON_RUN (0x0001)
313//#ifndef DRV_ADC_NO_TEST_DACMON
314// #define AUXADC_CON_CALI_MASK (0x007c)
315// #define AUXADC_CON_TESTDACMON (0x0080)
316//#endif // #ifndef DRV_ADC_NO_TEST_DACMON
317//#if defined(DRV_ADC_SW_RESET)
318// #define AUXADC_CON_SW_RESET (0x0080)
319//#endif // #if defined(DRV_ADC_SW_RESET)
320// #define AUXADC_CON_AUTOCLR0 (0x0100)
321// #define AUXADC_CON_AUTOCLR1 (0x0200)
322// #define AUXADC_CON_PUWAIT_EN (0x0800)
323// #define AUXADC_CON_AUTOSET (0x8000)
324//#endif // #if !defined(DRV_ADC_OFF)
325//
326//
327//
328// #if defined(DRV_ADC_MAX_CH_5)
329// #define ADC_MAX_CHANNEL 5
330// #endif /*DRV_ADC_MAX_CH_5*/
331//
332// #if defined(DRV_ADC_MAX_CH_6)
333// #define ADC_MAX_CHANNEL 6
334// #endif /*DRV_ADC_MAX_CH_6*/
335//
336// #if defined(DRV_ADC_MAX_CH_7)
337// #define ADC_MAX_CHANNEL 7
338// #endif /*DRV_ADC_MAX_CH_7*/
339//
340// #if defined(DRV_ADC_MAX_CH_8)
341// #define ADC_MAX_CHANNEL 8
342// #endif /*DRV_ADC_MAX_CH_8*/
343//
344// #if defined(DRV_ADC_MAX_CH_9)
345// #define ADC_MAX_CHANNEL 9
346// #endif /*DRV_ADC_MAX_CH_9*/
347//
348// #if defined(DRV_ADC_MAX_CH_10)
349// #define ADC_MAX_CHANNEL 10
350// #endif /*DRV_ADC_MAX_CH_10*/
351//
352// #if defined(DRV_ADC_MAX_CH_13)
353// #define ADC_MAX_CHANNEL 13
354// #endif /*DRV_ADC_MAX_CH_10*/
355//
356// #define ADC_ERR_CHANNEL_NO 50
357//#endif /*(MT6205B,MT6218)*/
358//
359//#if ( defined(DRV_ADC_BASIC_REG) || defined(DRV_ADC_TDMA_TIME) )
360//#if !defined(DRV_ADC_OFF)
361// #if defined(DRV_ADC_TDMA_EVENT_REG_POS1)
362// #define AUXADC_TDMA_EVENT0 (TDMA_base+0x1c0)
363// #define AUXADC_TDMA_EVENT1 (TDMA_base+0x1c4)
364// #elif defined(DRV_ADC_TDMA_EVENT_REG_POS2)
365// #define AUXADC_TDMA_EVENT0 (TDMA_base+0x400)
366//
367// #if defined(MT6229_S00)
368// #define AUXADC_TDMA_EVENT1 (TDMA_base+0x400)/*HW bug*/
369// #else
370// #define AUXADC_TDMA_EVENT1 (TDMA_base+0x404)/**/
371// #endif
372//
373// #else
374// #define AUXADC_TDMA_EVENT0 (TDMA_base+0x1b0)
375// #define AUXADC_TDMA_EVENT1 (TDMA_base+0x1b4)
376// #endif
377//
378// #if defined(DRV_ADC_TDMA_EN_REG_POS1)
379// #define AUXADC_TDMA_EN (TDMA_base+0x16C)
380// #else
381// #define AUXADC_TDMA_EN (TDMA_base+0x164)
382// #endif
383// /*AUXADC_TDMA_EN*/
384// #define AUXADC_TDMA_EN_EVT0 (0x0001)
385// #define AUXADC_TDMA_EN_EVT1 (0x0002)
386//#endif // #if !defined(DRV_ADC_OFF)
387//#endif // #if ( defined(DRV_ADC_BASIC_REG) || defined(DRV_ADC_TDMA_TIME) )
388//
389//
390//#if defined(DRV_ADC_NOT_EXIST)
391// #define ADC_MAX_CHANNEL 1
392// #define ADC_ERR_CHANNEL_NO 50
393//#endif // #if defined(DRV_ADC_NOT_EXIST)
394//
395//#if !defined(DRV_ADC_OFF)
396//#if !defined(ADC_MAX_CHANNEL)
397// #define ADC_MAX_CHANNEL 1
398// #define ADC_ERR_CHANNEL_NO 50
399//#endif // #if defined(DRV_ADC_NOT_EXIST)
400//#endif // #if !defined(DRV_ADC_OFF)
401//
402//#if 1
403// typedef struct
404// {
405// kal_int32 ADCSlope[ADC_MAX_CHANNEL];
406// kal_int32 ADCOffset[ADC_MAX_CHANNEL];
407// }ADC_CALIDATA;
408//#else
409// typedef struct
410// {
411// kal_int32 ADCSlope[ADC_MAX_CHANNEL];
412// kal_int32 ADCOffset[ADC_MAX_CHANNEL];
413// }ADC_CALIDATA;
414//#endif
415///*************************************************************************/
416//#if defined(DRV_MISC_ADC_MEASURE_REMOVE_IRQMASK)
417//// Define to perform ADC race condition check when processing critical data process
418//#define ADC_RACE_CONDITION_CHECK
419//// Define to remove IRQ mask/restore for ADC measurement
420//#define ADC_REMOVE_IRQMASK
421//#endif // #if defined(DRV_MISC_ADC_MEASURE_REMOVE_IRQMASK)
422//
423//#if defined(ADC_RACE_CONDITION_CHECK)
424//extern kal_bool gADC_RC_Check;
425//// MoDIS parser skip start
426//// The following two APIs are private APIs, NOT exported as public APIs
427//extern void ADCRCCheckAndLock(void);
428//extern void ADCRCRelease(void);
429//// MoDIS parser skip end
430//#endif // #if defined(ADC_RACE_CONDITION_CHECK)
431//
432//#if defined(ADC_REMOVE_IRQMASK)
433//#define ADCSAVEANDSETIRQMASK(mask) {}
434//#define ADCRESTOREIRQMASK(mask) {}
435//#else // #if defined(ADC_REMOVE_IRQMASK)
436//#define ADCSAVEANDSETIRQMASK(mask) {mask = SaveAndSetIRQMask();}
437//#define ADCRESTOREIRQMASK(mask) RestoreIRQMask(mask)
438//#endif // #if defined(ADC_REMOVE_IRQMASK)
439//
440///*************************************************************************/
441//
442//// MoDIS parser skip start
443//// The following APIs are private APIs
444//extern kal_uint16 ADC_GetData(kal_uint8 sel);
445//// adc.c
446//extern kal_uint16 ADC_IMM_Data(kal_uint16 channel);
447//extern kal_uint16 ADC_SYNC_Data(kal_uint16 channel);
448//extern void ADC_Init(void);
449//
450//// MoDIS parser skip end
451//
452//#if !defined(DRV_ADC_OFF)
453//#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_ADC_REG_DBG__)
454//#define DRV_ADC_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
455//#define DRV_ADC_Reg(addr) DRV_DBG_Reg(addr)
456//#define DRV_ADC_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
457//#define DRV_ADC_Reg32(addr) DRV_DBG_Reg32(addr)
458//#define DRV_ADC_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
459//#define DRV_ADC_Reg8(addr) DRV_DBG_Reg8(addr)
460//#define DRV_ADC_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
461//#define DRV_ADC_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
462//#define DRV_ADC_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
463//#define DRV_ADC_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
464//#define DRV_ADC_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
465//#define DRV_ADC_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
466//#define DRV_ADC_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
467//#define DRV_ADC_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
468//#define DRV_ADC_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
469//#else
470//#define DRV_ADC_WriteReg(addr,data) DRV_WriteReg(addr,data)
471//#define DRV_ADC_Reg(addr) DRV_Reg(addr)
472//#define DRV_ADC_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
473//#define DRV_ADC_Reg32(addr) DRV_Reg32(addr)
474//#define DRV_ADC_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
475//#define DRV_ADC_Reg8(addr) DRV_Reg8(addr)
476//#define DRV_ADC_ClearBits(addr,data) DRV_ClearBits(addr,data)
477//#define DRV_ADC_SetBits(addr,data) DRV_SetBits(addr,data)
478//#define DRV_ADC_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
479//#define DRV_ADC_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
480//#define DRV_ADC_SetBits32(addr,data) DRV_SetBits32(addr,data)
481//#define DRV_ADC_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
482//#define DRV_ADC_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
483//#define DRV_ADC_SetBits8(addr,data) DRV_SetBits8(addr,data)
484//#define DRV_ADC_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
485//#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_ADC_REG_DBG__)
486//
487//#else //!defined(DRV_ADC_OFF)
488//
489//#define DRV_ADC_WriteReg(addr,data)
490//#define DRV_ADC_Reg(addr) drv_dummy_return()
491//#define DRV_ADC_WriteReg32(addr,data)
492//#define DRV_ADC_Reg32(addr) drv_dummy_return()
493//#define DRV_ADC_WriteReg8(addr,data)
494//#define DRV_ADC_Reg8(addr) drv_dummy_return()
495//#define DRV_ADC_ClearBits(addr,data)
496//#define DRV_ADC_SetBits(addr,data)
497//#define DRV_ADC_SetData(addr, bitmask, value)
498//#define DRV_ADC_ClearBits32(addr,data)
499//#define DRV_ADC_SetBits32(addr,data)
500//#define DRV_ADC_SetData32(addr, bitmask, value)
501//#define DRV_ADC_ClearBits8(addr,data)
502//#define DRV_ADC_SetBits8(addr,data)
503//#define DRV_ADC_SetData8(addr, bitmask, value)
504//
505//#endif //!defined(DRV_ADC_OFF)
506
507#endif /*_ADC_H*/
508