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192.168.1.100 / T800_MD / 0b80c7188a6089ae59f523c5d460adad05960e1d / . / mcu / interface / driver / sleep_drv / RM_public.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
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14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
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19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
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21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
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30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*******************************************************************************
37 *
38 * Filename:
39 * ---------
40 * RM_public.h
41 *
42 * Project:
43 * --------
44 * MT6280
45 *
46 * Description:
47 * ------------
48 * Resource Management configuration
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
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491 *------------------------------------------------------------------------------
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493 *============================================================================
494 ****************************************************************************/
495
496#ifndef RM_PUBLIC_H
497#define RM_PUBLIC_H
498
499#include "kal_general_types.h"
500#include "sleepdrv_common.h"
501#include "l1_rm_public.h" /* for modem related definition move to l1sm_public.h */
502
503
504typedef enum
505{
506 /* Resource on MCU RM */
507 //RM_MCU_BASE = 0,
508 /* Resource on MODEM RM */
509 MODEM_SLV_START = 0,
510 RM_MD2G_SPEECH = 0,
511 RM_C2K_TRIGGER = 4,
512 RM_LTE_CS = 5,
513 RM_FDD_TD = 6,/* talking & datalink */
514 RM_FDD_DL = 7, /* datalink */
515 MODEM_SLV_END = 7,
516 MODEM_DBG_START = 8,
517 RM_TDD_TD = 11,
518 RM_TDD_DL = 12,
519 MODEM_DBG_END = 12,
520 NUMBER_OF_RESOURCE,
521 /*Move original declared into RM_Module. */
522 RM_MODEM_BASE = 20,
523 RM_MODEM_DSP_1,
524 RM_MODEM_DSP_2,
525 RM_MODEM_L2_COPRO,
526 NUMBER_OF_RM_MODEM
527} RM_Module;
528
529typedef enum
530{
531#if defined(__MD93__)
532 CORE0_PWR = 0,
533 CORE1_PWR = 1,
534 USIP0_PWR = 2,
535 USIP1_PWR = 3,
536 MML2_PWR = 4,
537 MDCORE_PWR = 5,
538 MDINFRA_PWR = 6,
539 CM2_PWR = 7,
540 MAX_PWR = 8,
541#elif defined(__MD95__)
542 CORE0_PWR = 0,
543 CORE1_PWR = 1,
544 CORE2_PWR = 2,
545 USIP0_PWR = 3,
546 MDCORE_PWR = 4,
547 CM2_PWR = 5,
548 MML2_PWR = 6,
549 MAX_PWR = 7,
550#elif defined(__MD97__) || defined(__MD97P__)
551 CORE0_PWR = 0,
552 CORE1_PWR = 1,
553 CORE2_PWR = 2,
554 CORE3_PWR = 3,
555 USIP0_PWR = 4,
556 MDCORE_PWR = 5,
557 MML2_PWR = 6,
558 CM2_PWR = 11,
559 MAX_PWR = 12,
560#else
561 #error "no chip match"
562#endif
563} MDTOPSM_Power_Domain;
564
565typedef enum
566{
567 L1_COMMRES = 0,
568 EMI = 1,
569 MAX_CT = 2,
570} MDTOPSM_Cross_Trigger;
571
572//#endif
573
574void RM_Init( void );
575extern void MD_TOPSM_PWR_SW_Control(MDTOPSM_Power_Domain pwr_dom, kal_bool enable);
576extern void MD_TOPSM_CT_SW_Control(MDTOPSM_Cross_Trigger CT, kal_bool enable);
577extern void MD_TOPSM_DDR_SW_Control(kal_bool enable);
578extern void MD_TOPSM_Init_Other_Cores(void);
579extern void MD_TOPSM_SibAttach(void);
580extern kal_bool MD_TOPSM_Is_USIP_ForcedOn(void);
581extern kal_bool MD_TOPSM_Is_Pwr_Domain_Off_to_On(MDTOPSM_Power_Domain pwr_dom);
582extern void MD_TOPSM_PWR_SW_Control_CM2(kal_bool enable);
583extern void MD_TOPSM_PWR_SW_Control_MDCORE(kal_bool enable);
584extern kal_bool MD_TOPSM_Is_Pwr_Domain_on(MDTOPSM_Power_Domain pwr_dom);
585extern kal_bool MD_TOPSM_GetCsysReqSta(void);
586extern kal_bool MD_TOPSM_IsMDInfraPowerOn(void);
587extern kal_bool MD_TOPSM_IsUsipPowerOn(void);
588extern kal_uint32 MD_TOPSM_Get_F32K_Cnt(void);
589/* Should remove later */
590extern kal_uint32 MD_TOPSM_PollingTimingSyncSta(MODEM_TOPSM_TIMER_MODULE timer);
591extern kal_uint32 MD_TOPSM_GetSync26M(MODEM_TOPSM_TIMER_MODULE timer);
592extern void MD_TOPSM_ClearTimingSyncSta(MODEM_TOPSM_TIMER_MODULE timer);
593extern void MD_TOPSM_SetGPSSyncCon0(kal_uint32 value);
594extern void MD_TOPSM_SetGPSSyncCon1(kal_uint32 value);
595extern kal_bool MD_TOPSM_GetErrorStatus(void);
596#endif /* !RM_PUBLIC_H */