mcu/interface/driver/sleep_drv/sleepdrv_common.h

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/*****************************************************************************
 *
 * Filename:
 * ---------
 *   sleepdrv_common.h
 *
 * Project:
 * --------
 *   Maui_Software
 *
 * Description:
 * ------------
 *   This file is a common include file for l1core & pcore dual-core
 *
 * Author:
 * -------
 * -------
 *
 *============================================================================
 *             HISTORY
 * Below this line, this part is controlled by ClearCase. DO NOT MODIFY!!
 *------------------------------------------------------------------------------
 * $Log$
 *
 * 02 01 2021 pj.chen
 * [MOLY00622176] [Colgin][MT6880][MD_Sanity][MCD][core0,vpe0,tc0(vpe0)] Assert fail: pll_gen97.c 525 0x1 0x1a 0x2222 - 0IDLE
 * 	
 * 	Increase 26M settle time
 *
 * 01 22 2021 pj.chen
 * [MOLY00620543] [Colgin][MT6880][MD_Sanity][MCD][core0,vpe0,tc0(vpe0)] Assert fail: MD_TOPSM.c 1923 0x6 0x0 0x0 - 0IDLE
 * 	
 * 	Increase EMI settle time (MD700)
 *
 * 11 11 2020 pj.chen
 * [MOLY00554988] [Colgin] Sync code from T700.MP for sleep_drv
 * Code sync from T700.MP to MD700.MP
 *
 * 04 15 2020 guo-huei.chang
 * [MOLY00509323] [Gen97] Power Model
 * 	Power model (Sleep Driver Part)
 * 	global variable from UnCache to Cache
 *
 * 04 06 2020 guo-huei.chang
 * [MOLY00509323] [Gen97] Power Model
 * 	
 * 	Power model (Sleep Driver Part)
 *
 * 02 04 2020 owen.ho
 * [MOLY00476151] [HCR][MT6873][Margux][Q0][MP2][SQC][MTBF][ErrorTimes:4]Externel (EE),0,0,99,/data/vendor/core/,1,modem,Trigger time:[2020-01-17 18:21:13.978100] md1:(MCU_core0.vpe0.tc0(VPE0)) [ASSERT] file:mcu/driver/devdrv/pll/src/pll_gen97.c line:494
 * 	
 * 	Rollback 26m settle time due to SPMFW bug fixed
 *
 * 12 03 2019 owen.ho
 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
 * Update 26m settle for Margaux
 *
 * 09 25 2019 owen.ho
 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
 * 	
 * 	1.Update 26m and apsrc settle time
 * 	2.Check 26m ready by ack
 *
 * 09 23 2019 guo-huei.chang
 * [MOLY00442253] 5G Feature �\��API �ݨD
 * 	
 * 	MDLPM for customer
 *
 * 09 02 2019 owen.ho
 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
 * Update low power related golden settings(26m/emi settle)
 *
 * 08 28 2019 owen.ho
 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
 * Update sleep mode golden settings
 *
 * 07 01 2019 ws.yan
 * [MOLY00417187] Gen97 sleep mode development: add MD97P option amd update rf topsm golden setting
 * 	
 * 	.
 * 	[EWSP0000021808]
 *
 * 06 24 2019 owen.ho
 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
 * Unify definition for 26m settle time
 *
 * 01 30 2019 leon.yeh
 * [MOLY00381082] [Gen97] Modem Sleep UMOLYE merge back  [ERS00028734]
 * 	- add 2G slave (SW) trigger TXSYS power enum
 * 	- TOPDM setting change based on DE spec for Lafite
 * 	.
 *
 * 01 02 2019 owen.ho
 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
 * Drvtest environment
 *
 * 11 26 2018 owen.ho
 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
 * Merge from VMOLY
 *
 * 10 19 2018 owen.ho
 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
 * Update golden settings
 *
 * 08 17 2018 owen.ho
 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
 * Integrate Gen97 driver from UMOYE.Gen97.DEV
 *
 * 05 18 2018 owen.ho
 * [MOLY00312416] [Gen97] Sleep driver development
 * Gen97 sleep driver
 *
 * 03 09 2018 owen.ho
 * [MOLY00312416] [Gen97] Sleep driver development
 * Solve build error for Gen97
 * 06 14 2018 che-wei.chang
 * [MOLY00333397] [TOPSM/OST] remove legacy code and log reduction
 *
 * 05 16 2018 che-wei.chang
 * [MOLY00318930] [Eiger] topsm/ost - update 26m settle time
 *
 * 05 09 2018 che-wei.chang
 * [MOLY00318930] [Eiger] topsm/ost - modify 26m setle time to 154T
 *
 * 03 14 2018 che-wei.chang
 * [MOLY00281049] [93/95 re-arch] MD topsm/ost - update 26m settle time to 143T+4T
 *
 * 03 09 2018 che-wei.chang
 * [MOLY00281049] [93/95 re-arch] MD topsm/ost - modify 95 26m settle time
 *
 * 01 18 2018 leon.yeh
 * [MOLY00283840] [93/95 re-arch][MT6295] code merge  - modem topsm setting for pre antenna trigger modify according to Ver 2.0 (20180111) spec.
 *
 * 11 30 2017 owen.ho
 * [MOLY00293253] [MT6771][Sylvia]DCXO_RDY_WO_ACK assert after Dormant
 * Modify 26m settle time
 *
 * 03 03 2017 owen.ho
 * [MOLY00171832] [UMOLYA]
 * 	
 * 	Update sys_clk settle time
 *
 * 01 20 2017 guo-huei.chang
 * [MOLY00207227] [MT6293] Sleep Driver
 * add flight mode support for C2K
 *
 * 11 02 2016 guo-huei.chang
 * [MOLY00207227] [MT6293] Sleep Driver
 * 	
 * 	1. move OSTD, MO_TOPSM, and Sleep_driver from L1 to PS trace
 * 	2. sync log with Gen92
 *
 * 03 30 2016 hsiao-hsien.chen
 * [MOLY00171976] [GEN93] Fix sleep driver build error.
 * Add 93 option.
 *
 * 08 20 2015 shengfu.tsai
 * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus
 * 	.submit the modem topsm initial function for Elbrus
 *
 * 08 04 2015 che-wei.chang
 * [MOLY00120320] [TK6291/Jade] DVFS Code Submission
 * update ccirq cmd enum for dvfs
 *
 * 07 23 2015 ethan.hsieh
 * [MOLY00131103] Sleep Mode Debug Shared Memory Mechanism Improvement
 *
 * 07 10 2015 che-wei.chang
 * [MOLY00127376] [MT6755][UMOLY]update md 26m settle time to 4ms
 *
 * 07 10 2015 che-wei.chang
 * [MOLY00120320] [TK6291/Jade] DVFS Code Submission,add ccirq enum for DVFS
 *
 * 07 07 2015 che-wei.chang
 * [MOLY00089700] [TK6291][UMOLY]
 * sync low power Cbr
 * 	1.add stress test AT CMD (ps side)
 * 	2.add at_sleepcount AT CMD (ps side)
 * 	3.update setting for JADE
 *
 * 06 18 2015 hsiao-hsien.chen
 * [MOLY00072109] [MT6291] Sleep mode code modification.
 * Fix build error. Add CCIRQ enum for pcore stress test.
 *
 * 06 11 2015 che-wei.chang
 * [MOLY00089700] [TK6291][UMOLY]
 * update SleepDrv_CCIRQ_CMD_E for DVFS
 *
 * 05 28 2015 ethan.hsieh
 * [MOLY00085137] [TK6291] Sleep Mode Modifications - Move infinite sleep compile option to sleepdrv_common.h for both Pcore and L1core
 *
 * 05 14 2015 ethan.hsieh
 * [MOLY00085137] [TK6291] Sleep Mode Modifications - Infinite Sleep for Jade
 *
 *------------------------------------------------------------------------------
 * Upper this line, this part is controlled by ClearCase. DO NOT MODIFY!!
 *============================================================================
 ****************************************************************************/



#ifndef __SLEEPDRV_COMMON_H__
#define __SLEEPDRV_COMMON_H__

#ifndef MAX
#define MAX(a,b)  ( ( (a) > (b) ) ? (a) : (b) )
#endif

#ifndef MAX4
#define MAX4(a,b,c,d) MAX( MAX((a),(b)) , MAX((c),(d)) )
#endif

#if defined(__MD93__)
    #if defined(MT6763) || defined(MT6739)
        #define RM_SYS_CLK_SETTLE     0x8C
    #elif defined(MT6771)
        #define RM_SYS_CLK_SETTLE     0x97
    #else
        #define RM_SYS_CLK_SETTLE     0x97
    #endif
#elif defined(__MD95__)
    #if defined(MT6779)                     // Lafite
        #define RM_SYS_CLK_SETTLE     0x93  // according to 2018/10/04 DE Wayne Liu's comment
    #else
        #define RM_SYS_CLK_SETTLE     0x9E  // according to Ver 2.0 (20180111) spec
    #endif
#elif defined(__MD97__) || defined(__MD97P__)
    #if defined(MT6297) || defined(MT6297_IA)  
        #define SYS_CLK_SETTLE        0x96
        #define RM_SYS_CLK_SETTLE     SYS_CLK_SETTLE+4
        #define MD_MAS_TRIG_EMI_SETTLE       (0x12)
    #elif defined(MT6885)
        #define SYS_CLK_SETTLE        0x51
        #define RM_SYS_CLK_SETTLE     SYS_CLK_SETTLE+4
        #define MD_MAS_TRIG_EMI_SETTLE       (0x15)
    #elif defined(CHIP10992)
        #define REAL_SYS_CLK_SETTLE   0x3B
        #define TIA_SETTLE            0x5E
        #define MD_MAS_TRIG_EMI_SETTLE       (0x28)
        #define PLL_PWR_MASTRIG_TIMER_SETTLE MAX4(MD_RM_PLL_SETTLE, MD_MAX_PWR_SETTLE, MD_MAS_TRIG_MAX_SETTLE, MD_TIMER_TRIG_SETTLE)
        // 26M+EMI settle time need to cover TIA settle time
        #define SYS_CLK_SETTLE        (MAX(TIA_SETTLE, REAL_SYS_CLK_SETTLE+PLL_PWR_MASTRIG_TIMER_SETTLE) - PLL_PWR_MASTRIG_TIMER_SETTLE)
        #define RM_SYS_CLK_SETTLE     SYS_CLK_SETTLE+4
    #else
        #define SYS_CLK_SETTLE        0x53
        #define RM_SYS_CLK_SETTLE     SYS_CLK_SETTLE+4
        #define MD_MAS_TRIG_EMI_SETTLE       (0x16)
    #endif
    #define MD_MAS_TRIG_L1_COMM_SETTLE   (0xE)
    #define MD_MAS_TRIG_MAX_SETTLE       MAX(MD_MAS_TRIG_EMI_SETTLE, MD_MAS_TRIG_L1_COMM_SETTLE)
    #define MD_TIMER_TRIG_SETTLE         (0x4)
    #define MD_MAX_PWR_SETTLE            (0x2)
    #define MD_RM_PLL_SETTLE             (0x2)
#else
    #error "no chip match"
#endif

typedef enum {
    SLP_DBG_SHM_FIX_REG_PS_ISR_SM_SLV_REQ_STA,
    SLP_DBG_SHM_FIX_REG_PS_NON_F32K_WKUP_STA,
    SLP_DBG_SHM_FIX_REG_PS_F32K_WKUP_STA,
    SLP_DBG_SHM_FIX_REG_PS_F32K2_WKUP_STA,
    SLP_DBG_SHM_FIX_REG_PS_PRE_TIMESTAMP,
    SLP_DBG_SHM_FIX_REG_PS_AFT_TIMESTAMP,
    SLP_DBG_SHM_FIX_REG_PS_SW_LOCK,
    SLP_DBG_SHM_FIX_REG_PS_RM_PWR_STA,
    SLP_DBG_SHM_FIX_REG_PS_SW_PWR_CLK_FORCE_ON,
    SLP_DBG_SHM_FIX_REG_PS_PWRPLL_OFF_REC,
    SLP_DBG_SHM_FIX_REG_PS_MD_SYSCLK_GATING_STA,
    SLP_DBG_SHM_FIX_REG_PS_RESERVED1,
    SLP_DBG_SHM_FIX_REG_PS_END = SLP_DBG_SHM_FIX_REG_PS_RESERVED1,
    SLP_DBG_SHM_FIX_REG_L1_ISR_SM_SLV_REQ_STA,
    SLP_DBG_SHM_FIX_REG_L1_NON_F32K_WKUP_STA,
    SLP_DBG_SHM_FIX_REG_L1_F32K_WKUP_STA,
    SLP_DBG_SHM_FIX_REG_L1_PRE_TIMESTAMP,
    SLP_DBG_SHM_FIX_REG_L1_AFT_TIMESTAMP,
    SLP_DBG_SHM_FIX_REG_L1_SW_LOCK,
    SLP_DBG_SHM_FIX_REG_L1_SM_PWR_RDY,
    SLP_DBG_SHM_FIX_REG_L1_SM_PLL_STA,
    SLP_DBG_SHM_FIX_REG_L1_SM_DBG_REQ_STA,
    SLP_DBG_SHM_FIX_REG_L1_SM_MAS_REQ_STA,
    SLP_DBG_SHM_FIX_REG_L1_SM_PWR_ON_SW_CTRL0,
    SLP_DBG_SHM_FIX_REG_L1_SW_PLL_FORCE_ON,
    SLP_DBG_SHM_FIX_REG_L1_END = SLP_DBG_SHM_FIX_REG_L1_SW_PLL_FORCE_ON,
    SLP_DBG_SHM_FIX_REG_END
} SLP_DBG_SHM_FIX_REG_INDEX;

typedef struct {
    kal_uint32 guard_pat;
    // fix pattern of buffer selection for pscore
    kal_uint32 buf_sel_ps;
    // fix pattern of buffer selection for l1core
    kal_uint32 buf_sel_l1;
    kal_uint32 revision;
    // double size for fix pattern
    kal_uint32 fix_reg[SLP_DBG_SHM_FIX_REG_END<<1];
} slp_dbg_shm_fix_pat_t;

typedef enum {
    //SLP_DBG_SHM_LockSleep = 0x1,
    //SLP_DBG_SHM_UnLockSleep,
    SLP_DBG_SHM_2G_Sleep = 0x1,
    SLP_DBG_SHM_2G_Wakeup,
    SLP_DBG_SHM_3G_Sleep,
    SLP_DBG_SHM_3G_Wakeup,
    SLP_DBG_SHM_4G_Sleep,
    SLP_DBG_SHM_4G_Wakeup,
    SLP_DBG_SHM_RAT_InfiniteSleep_Done,
} SLP_DBG_SHM_RING_BUFFER_INDEX;

typedef struct {
    // index is for recording enumrate SLP_DBG_SHM_RING_BUFFER_INDEX
    kal_uint32 index:4;
    // Bi[0] = 1 if 2G RM_TMR_SSTA is not in pause state
    // Bi[1] = 1 if 3G RM_TMR_SSTA is not in pause state
    // Bi[2] = 1 if SM_SLV_REQ_STA shows TD is slave ready
    // Bi[3] = 1 if 4G RM_TMR_SSTA is not in pause state
    kal_uint32 status:4;
    // record for FMA global timestamp, and unit is 256 us.
    kal_uint32 timestamp:24;
    // additional debug information for user.
    kal_uint32 dbg_info;
} slp_dbg_shm_ring_buf_t;

// Now, AP only dumps 512 bytes although shared memory size is 1K bytes
#define SLP_DBG_SHM_AP_DUMP_SIZE    512
typedef struct {
    kal_uint32 guard_pat1;
    kal_uint32 guard_pat2;
    kal_uint32 guard_pat3;
    kal_uint32 revision;
    slp_dbg_shm_ring_buf_t info[(SLP_DBG_SHM_AP_DUMP_SIZE-sizeof(slp_dbg_shm_fix_pat_t)-sizeof(kal_uint32)*4)/sizeof(slp_dbg_shm_ring_buf_t)];
} slp_dbg_shm_ring_pat_t;

typedef struct {
    slp_dbg_shm_fix_pat_t fix_pat;
    slp_dbg_shm_ring_pat_t ring_pat;
} slp_dbg_shm_t;

typedef enum _slp_lock_type_e {
    SLP_IS_NO_LOCK,
    SLP_IS_SW_LOCK,
    SLP_IS_HW_LOCK
} slp_lock_type_e;

typedef enum _power_model_mdlpm_e {
    POWER_MODEL_MDLPM_RESERVED_0 = 0, // Reserve 0 for speicial purpose
    POWER_MODEL_MDLPM_UTC_0,
    POWER_MODEL_MDLPM_UTC_1,
    POWER_MODEL_MDLPM_FRC,
    POWER_MODEL_MDLPM_WALL_CLK_0,
    POWER_MODEL_MDLPM_WALL_CLK_1,
    POWER_MODEL_MDLPM_MD_SLEEP_DUR,
    POWER_MODEL_MDLPM_GL1_SLEEP_DUR,
    POWER_MODEL_MDLPM_UL1_SLEEP_DUR,
    POWER_MODEL_MDLPM_EL1_SLEEP_DUR,
    POWER_MODEL_MDLPM_NL1_SLEEP_DUR = 10,
    POWER_MODEL_MDLPM_GL1_CONNECT_DUR,
    POWER_MODEL_MDLPM_GL1_CONNECT_DRX_DUR,
    POWER_MODEL_MDLPM_GL1_RX_WINDOW_DUR,
    POWER_MODEL_MDLPM_GL1_TX_WINDOW_DUR,
    POWER_MODEL_MDLPM_GL1_TX_POWER_RATIO_0,
    POWER_MODEL_MDLPM_GL1_TX_POWER_RATIO_1,
    POWER_MODEL_MDLPM_RESERVED_20 = 20,
    POWER_MODEL_MDLPM_UL1_CONNECT_DUR,
    POWER_MODEL_MDLPM_UL1_CONNECT_DRX_DUR,
    POWER_MODEL_MDLPM_UL1_RX_WINDOW_DUR,
    POWER_MODEL_MDLPM_UL1_TX_WINDOW_DUR,
    POWER_MODEL_MDLPM_UL1_TX_POWER_RATIO_0,
    POWER_MODEL_MDLPM_UL1_TX_POWER_RATIO_1,
    POWER_MODEL_MDLPM_RESERVED_30 = 30,
    POWER_MODEL_MDLPM_EL1_CONNECT_DUR,
    POWER_MODEL_MDLPM_EL1_CONNECT_DRX_DUR,
    POWER_MODEL_MDLPM_EL1_RX_WINDOW_DUR,
    POWER_MODEL_MDLPM_EL1_TX_WINDOW_DUR,
    POWER_MODEL_MDLPM_EL1_TX_POWER_RATIO_0,
    POWER_MODEL_MDLPM_EL1_TX_POWER_RATIO_1,
    POWER_MODEL_MDLPM_EL1_CC_RATIO_0,
    POWER_MODEL_MDLPM_EL1_CC_RATIO_1,
    POWER_MODEL_MDLPM_EL1_RAS_RATIO,
    POWER_MODEL_MDLPM_RESERVED_45 = 45,
    POWER_MODEL_MDLPM_NL1_CONNECT_DUR,
    POWER_MODEL_MDLPM_NL1_CONNECT_DRX_DUR,
    POWER_MODEL_MDLPM_NL1_RX_WINDOW_DUR,
    POWER_MODEL_MDLPM_NL1_TX_WINDOW_DUR,
    POWER_MODEL_MDLPM_NL1_TX_POWER_RATIO_0,
    POWER_MODEL_MDLPM_NL1_TX_POWER_RATIO_1,
    POWER_MODEL_MDLPM_DVFS_GEAR_RATIO_0 = 61,
    POWER_MODEL_MDLPM_DVFS_GEAR_RATIO_1 = 62,
    POWER_MODEL_MDLPM_REC_INDEX = 63,
    POWER_MODEL_MDLPM_MAX_ITEM = 64
} power_model_mdlpm_e;

#endif