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192.168.1.100 / T800_MD / 0b80c7188a6089ae59f523c5d460adad05960e1d / . / mcu / interface / driver / sleep_drv / sleepdrv_interface.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
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19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
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21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
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24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
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30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * sleepdrv_interface.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file is for the public access for sleep mode operation.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by ClearCase. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * $Log$
59 *
60 * 02 11 2022 yuhao.ye
61 * [MOLY00764790] [FBC][FM350-GL][NA][NA][USB]fm350 iot USB suspend and resume problem
62 *
63 * .
64 *
65 * 08 11 2021 pj.chen
66 * [MOLY00681687] [FM350-GL][FM350-GL][Nick Zhang][memory dump][NA][NA][NA]md_self_detect_by_hmu_long_time_no_response modem dump
67 * Add MCF lock sleep enum
68 *
69 * 11 10 2020 pj.chen
70 * [MOLY00528192] [Colgin][Sleep Mode]Driver development
71 * Add lock sleep enum for LVTS whole system reset
72 *
73 * 04 15 2020 guo-huei.chang
74 * [MOLY00509323] [Gen97] Power Model
75 * Power model (Sleep Driver Part)
76 * global variable from UnCache to Cache
77 *
78 * 04 06 2020 guo-huei.chang
79 * [MOLY00509323] [Gen97] Power Model
80 *
81 * Power model (Sleep Driver Part)
82 *
83 * 12 02 2019 jack.tung
84 * [MOLY00462428] [VMOLY][Gen97 Petrus] Structure Reordering in Sleep Driver
85 *
86 * .
87 *
88 * 10 24 2019 lian-li.tsai
89 * [MOLY00452393] For Low power monitor, raw data modify
90 * [EWSP0000054581_R1]
91 * [EWSP0000054581]
92 *
93 * 08 08 2019 guo-huei.chang
94 * [MOLY00421978] [VMOLY]Sleep and low power modify
95 * add md low power monitor (OSTD part)
96 *
97 * 08 06 2019 owen.ho
98 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
99 * Solve build error for Mercury
100 *
101 * 07 18 2019 owen.ho
102 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
103 * Add compile option for MD97P
104 *
105 * 04 15 2019 owen.ho
106 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
107 * Add sleep control enum
108 *
109 * 04 11 2019 owen.ho
110 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
111 * 1.Add sleep comtrol enum
112 * 2.DDr_en settings
113 * 3.Wakeup event settings
114 * 4.Add wallclk define
115 * 5.Force on IA for early csys_req
116 * 6.Modify AT command
117 *
118 * 03 11 2019 che-wei.chang
119 * [MOLY00389209] [MT6297] topsm/ost for apollo dram power index
120 *
121 * 01 31 2019 guo-huei.chang
122 * [MOLY00353483] [GEN95] MD Low Power Monitor
123 * fix build error for GEN95
124 *
125 * 01 31 2019 guo-huei.chang
126 * [MOLY00353483] [GEN95] MD Low Power Monitor
127 *
128 * merge MD Low Power Monitor from UMOLYE (OSTD & Sleep Driver Part)
129 *
130 * 11 22 2018 guo-huei.chang
131 * [MOLY00366073] [Lafite] MD part of OPPO P80 sleep information
132 * 1.add MD sleep time and sleep count to share memory
133 * 2.add iA idle time to MD low power monitor
134 *
135 * 10 30 2018 leon.yeh
136 * [MOLY00356811] [GEN95] MD Low Power Monitor L1 modulo fill data
137 * - add debug data
138 * .
139 *
140 * 10 15 2018 leon.yeh
141 * [MOLY00356811] [GEN95] MD Low Power Monitor L1 modulo fill data
142 * - 4G TX/RX path interface modify.
143 *
144 * 09 14 2018 jack.tung
145 * [MOLY00351968] [DFR][Gen95] Assertion Removal
146 *
147 * .
148 *
149 * 09 04 2018 ej.farn
150 * [MOLY00332776] [Gen95] MD Low Power Montior Development
151 * [Gen95] MD Low Power Monitor
152 *
153 * 08 30 2018 ej.farn
154 * [MOLY00332776] [Gen95] MD Low Power Montior Development
155 * [Gen95] MD Low Power Monitor
156 *
157 * 08 28 2018 ej.farn
158 * [MOLY00332776] [Gen95] MD Low Power Montior Development
159 * [Gen95] MD Low Power Monitor
160 *
161 * 01 08 2019 owen.ho
162 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
163 * Add SLEEP_CTL_MML1 for MD95.
164 *
165 * 01 07 2019 owen.ho
166 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
167 * Modify lock 26m interface
168 *
169 * 01 02 2019 owen.ho
170 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
171 * Add lock sleep control enum for 97
172 *
173 * 09 18 2018 owen.ho
174 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
175 * Add enum for 5G NL1
176 *
177 * 08 17 2018 owen.ho
178 * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
179 * Integrate Gen97 driver from UMOYE.Gen97.DEV
180 *
181 * 05 18 2018 owen.ho
182 * [MOLY00312416] [Gen97] Sleep driver development
183 * Gen97 sleep driver
184 * Solve build error for Gen97
185 * 06 14 2018 che-wei.chang
186 * [MOLY00333397] [TOPSM/OST] remove legacy code and log reduction
187 *
188 * 05 29 2018 guo-huei.chang
189 * [MOLY00327413] [UMOLYE]Low power monitor patch sync
190 * md low power monitor (ostd part)
191 *
192 * 04 26 2018 che-wei.chang
193 * [MOLY00318930] [Eiger] topsm/ost - add lock sleep enum id for sim3/sim4
194 *
195 * 04 02 2018 leon.yeh
196 * [MOLY00316801] for legacy chips option and feature options cleanup
197 *
198 * .
199 *
200 * 09 28 2017 che-wei.chang
201 * [MOLY00281049] [93/95 re-arch] MD topsm/ost
202 *
203 * 09 08 2017 jack.tung
204 * [MOLY00274378] [MD Platform Low-Power] Check Flight Mode Condition on HW Status
205 *
206 * 08 15 2017 owen.ho
207 * [MOLY00266818] [BIANCO][MT6763][MTBF][C2K][SIM1:CTC][SIM2:CU][ASSERT] file:mcu/common/driver/devdrv/log_seq/src/logseq_drv.c line:1195
208 * Force on usip API
209 *
210 * 06 28 2017 jack.tung
211 * [MOLY00257950] [Gen93] Flight Mode Debugging Information Improvement
212 *
213 * <saved by Perforce>
214 *
215 * 06 20 2017 owen.ho
216 * [MOLY00258341] [MT6763][Bianco][N1][E2][MD issue][TW] Assert on ulsp_mod_function with PLS mode
217 *
218 * Add sleep control enum for PLS
219 *
220 * 06 12 2017 jack.tung
221 * [MOLY00256211] [Gen93][UMOLYA][SleepDrv] Step-Logging Feature
222 *
223 * <saved by Perforce>
224 *
225 * 05 08 2017 owen.ho
226 * [MOLY00247811] [Bianco] Fatal Error (0xb34, 0x90f9c520, 0xcccccccc) - SQN_EL1 when enabling ostd sleep
227 *
228 * 05 05 2017 owen.ho
229 * [MOLY00246118] [BIANCO]Assert fail: wuldch.c 1439 0x0 0x0 0x0 - (LISR)UL1D_HISR_LISR
230 *
231 * Add sleep controller enumeration
232 *
233 * 03 31 2017 guo-huei.chang
234 * [MOLY00238980] [DHL] MET timer for sync between MET & ELT
235 * add SleepDrv_GetWallClk function
236 *
237 * 03 08 2017 owen.ho
238 * [MOLY00171832] [UMOLYA]
239 *
240 * 1.Update sleep_ctl_user enum
241 * 2.Porting EMM debug info function
242 * 3.Correct sleepDisable variable index
243 *
244 * 01 19 2017 kevin-kh.liu
245 * [MOLY00173902] [MT6293][Sleep Mode]sleep mode modification
246 * xL1SIM 2G Fixed AFC support - SM part
247 *
248 * 12 30 2016 owen.ho
249 * [MOLY00171832] [UMOLYA]
250 * Update SLEEP_CTL enum list
251 *
252 * 12 20 2016 owen.ho
253 * [MOLY00171832] [UMOLYA][Bianco] Update SLEEP_CTL enum list
254 *
255 * 12 19 2016 owen.ho
256 * [MOLY00171832] [UMOLYA]
257 * Update sleep_ctl enum and md power domain enum
258 *
259 * 12 14 2016 owen.ho
260 * [MOLY00171832] [UMOLYA]
261 *
262 * Update SLEEP_CTL enum
263 *
264 * 12 12 2016 owen.ho
265 * [MOLY00171832] [UMOLYA]
266 *
267 * Update SLEEP_CTL user enum
268 *
269 * 12 09 2016 owen.ho
270 * [MOLY00171832] [UMOLYA]
271 *
272 * Add SLEEP control user enum
273 *
274 * 12 02 2016 owen.ho
275 * [MOLY00171832] [UMOLYA]
276 *
277 * Update lock/unlock core sleep control user list
278 *
279 * 11 23 2016 owen.ho
280 * [MOLY00171832] [UMOLYA]
281 *
282 * 6293 sleep driver development (Modoify Lock/Unlock Sleep API)
283 *
284 * 11 09 2016 owen.ho
285 * [MOLY00171832] [UMOLYA]
286 *
287 * Solve build error
288 *
289 * 07 20 2016 owen.ho
290 * [MOLY00171832] [UMOLYA]
291 *
292 * Gen93 topsm/ostd driver develpement
293 *
294 * 07 06 2016 owen.ho
295 * [MOLY00171832] [UMOLYA]
296 * 6293 topsm/ostd driver development
297 *
298 * 06 24 2016 owen.ho
299 * [MOLY00171832] [UMOLYA]
300 * GEN93 md topsm/ostd driver development
301 *
302 * 03 31 2016 vmick.lin
303 * [MOLY00171891] [6293] sleep driver development
304 *
305 * .
306 *
307 * 03 30 2016 vmick.lin
308 * [MOLY00171891] [6293] sleep driver development
309 *
310 * .
311 *
312 * 03 15 2016 james.pan
313 * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
314 * EL1-EL2 lock LMAC power Sleep Driver for EL1 part (without trigger CCIRQ)
315 *
316 * 03 14 2016 james.pan
317 * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
318 * 1. MSBB Violation
319 * 2. Remove EL1D DVFS avtive window check
320 * 3. 4G sleep mode locker for DVFS drivers
321 * 4. Add Data Sync Barrier
322 * 5. Rename global veriable
323 * 6. LMAC locker API implement
324 * 7. EL1D Backup functions relocated
325 *
326 * 03 11 2016 james.pan
327 * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
328 * Rollback CL2258329 CL2158833 CL2159108
329 *
330 * 03 07 2016 james.pan
331 * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
332 * md_sm sleep_drv MSBB violation
333 *
334 * 02 23 2016 kevin-kh.liu
335 * [MOLY00163589] [6292][sleep mode] code merge from LR11 to UMOLY
336 *
337 * Sleep Mode Debug Shared Memory Mechanism
338 *
339 * 02 18 2016 leon.yeh
340 * [MOLY00165273] [6292][sleep mode] code merge from LR11 to UMOLY (fixAFC & 32K-less) - fix build error: INVALID_FREQ_OFF define changed to sleepdrv_interface.h
341 *
342 * 02 16 2016 dennis.chueh
343 * [MOLY00141188] [ELBRUS][FPGA] Add new features.
344 * Share memory debug functions:
345 * void SleepDrv_UpdatePSSlpDbgShmFixBuf(SLP_DBG_SHM_FIX_REG_INDEX index, kal_uint32 value);
346 * void SleepDrv_UpdateL1SlpDbgShmFixBuf(SLP_DBG_SHM_FIX_REG_INDEX index, kal_uint32 value);
347 * void SleepDrv_SlpDbgShmRingBufAdd(SLP_DBG_SHM_RING_BUFFER_INDEX index, kal_uint32 status, kal_uint32 dbg_info);
348 *
349 * 01 29 2016 jack.tung
350 * [MOLY00163331] MD-TOPSM API Atomicity Access Implementation
351 * Atomicity Operation Test and Implementation for TOPSM Software Force-On Control
352 *
353 * 01 20 2016 shengfu.tsai
354 * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus
355 *
356 * .fixed xl1sm build issue
357 *
358 * 01 19 2016 shengfu.tsai
359 * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus
360 *
361 * . modify l1sm\ul1sm include file to meet MSBB rule
362 *
363 * 11 03 2015 dennis.chueh
364 * [MOLY00141188] [ELBRUS][FPGA] Add new features.
365 *
366 * Add ENUM define for drvtest.
367 * Add Power down API.
368 *
369 * 11 02 2015 dennis.chueh
370 * [MOLY00141188] [ELBRUS][FPGA] Add new features.
371 *
372 * add MIPS_CPC_PowerOn to sleepdrv_interface.h.
373 *
374 * 10 30 2015 shengfu.tsai
375 * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus
376 *
377 * .merge some change from XL1SM branch
378 *
379 * 08 17 2015 dennis.chueh
380 * [MOLY00070771] [6291][FPGA]solve build error
381 * Solve build error after applying ELBRUS_FPGA.
382 *
383 * 08 16 2015 dennis.chueh
384 * [MOLY00070771] [6291][FPGA]solve build error
385 * Solve build error after applying ELBRUS make file.
386 *
387 * 08 13 2015 dennis.chueh
388 * [MOLY00070771] [6291][FPGA]solve build error
389 * Solve build error after merging back to UMOLY trunk.
390 *
391 * 08 13 2015 dennis.chueh
392 * [MOLY00070771] [6291][FPGA]solve build error
393 * Solve build error after merging back.
394 *
395 * 08 12 2015 shengfu.tsai
396 * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus
397 * .add SleepDrv_LockPcoreSleepMode and SleepDrv_LockLMACPower
398 * but these function need to modify in the future
399 *
400 * 08 04 2015 dennis.chueh
401 * [MOLY00070771] [6291][FPGA]solve build error
402 * SleepDrv_GetHandle() --> SleepDrv_GetHandle(SMP).
403 *
404 * 07 23 2015 guo-huei.chang
405 * [MOLY00131103] Sleep Mode Debug Shared Memory Mechanism Improvement
406 * 1. add CCIRQ CMD for L1core querying shared memory address
407 * 2. add fix pat API for PScore and L1core and ring buffer API for L1core
408 * 3. add fix pat in CheckSleep function
409 * 4. add declarion for DBM and PTPOD shared memory
410 *
411 * 06 11 2015 che-wei.chang
412 * [MOLY00089700] [TK6291][UMOLY]
413 * 1.add MT6755 flag for Jade
414 * 2.update ostd elt log
415 * 3.update SleepDrv_GetHandle return value for assert
416 *
417 * 05 05 2015 che-wei.chang
418 * [MOLY00089700] [TK6291][UMOLY] add enum PS_PLL_FORCEON_USER_SIB to PS_PLL_FORCEON_USER for SIB
419 *
420 * 04 29 2015 che-wei.chang
421 * [MOLY00089700] [TK6291][UMOLY] add a new API MD_TOPSM_PLL_SW_Control for force on PS side PLLs
422 *
423 * 04 29 2015 che-wei.chang
424 * [MOLY00089700] [TK6291][UMOLY] Sync vmick Cbr (Ccirq)
425 *
426 * 02 26 2015 che-wei.chang
427 * [MOLY00089700] [TK6291][UMOLY] Sync MT6291_DEV branch
428 *
429 * 02 10 2015 yu-hung.huang
430 * [MOLY00095165] [TK6291] Check in LITE GPT Driver and New Sleep API
431 * [UMOLY] 2-leve GPT solution: refine SRCLK (26M) force on/off API interface for multiple user
432 *
433 * 09 05 2014 yu-hung.huang
434 * [MOLY00078094] [UMOLY] Sleep Codes Sync from MOLY TRUNK to UMOLY TK6291_DEV
435 * [TK6291_DEV] Sync SD3 Sleep Driver Codes from MOLY TRUNK to UMOLY (Changelists before 2014/9/4 in MOLY TRUNK)
436 *
437 * 08 27 2014 vmick.lin
438 * [MOLY00075930] [MT6582LTE][CSFB DSDS][HQ][Ericsson][lwg bin] [ASSERT] file:rf_conflict_check.c line:97
439 * .
440 *
441 * 08 27 2014 vmick.lin
442 * [MOLY00075930] [MT6582LTE][CSFB DSDS][HQ][Ericsson][lwg bin] [ASSERT] file:rf_conflict_check.c line:97
443 * .
444 *
445 * 08 26 2014 vmick.lin
446 * [MOLY00075930] [MT6582LTE][CSFB DSDS][HQ][Ericsson][lwg bin] [ASSERT] file:rf_conflict_check.c line:97
447 * .
448 * Add 99T 32K period while OST struggle in SETTLE state
449 *
450 * 10 25 2013 alvin.chen
451 * [MOLY00043719] [MT6290][MDTOPSM] Patch for Phone Field trial activity
452 * Integration change.
453 *
454 * 10 03 2013 alvin.chen
455 * [MOLY00040177] [MT6290][MD_TOPSM] Add FRC enable API for Early Stage Debug
456 * <saved by Perforce>
457 *
458 * 07 26 2013 barry.hong
459 * [MOLY00030921] [MT6290]Low Power Feature patch back from CBr
460 * Low Power Feature patch back from CBr
461 *
462 * 02 26 2013 jeff.lee
463 * reorg. header file.
464 *
465 *
466 *
467 *------------------------------------------------------------------------------
468 * Upper this line, this part is controlled by ClearCase. DO NOT MODIFY!!
469 *============================================================================
470 ****************************************************************************/
471
472
473
474#ifndef __SLEEPDRV_INTERFACE_H__
475#define __SLEEPDRV_INTERFACE_H__
476
477#include "kal_public_api.h" //MSBB change #include "kal_release.h"
478#include "sleepdrv_common.h"
479
480
481#if defined(__SMART_PHONE_MODEM__) && defined(__MODEM_CCCI_EXIST__) && defined(__HIF_SDIO_SUPPORT__)
482#define PHONE_TYPE_FOR_HQA
483#endif
484
485#define BIG_DAC_CHANGE_RECALIBRATION /* This compiler option is default defined in Moly branch to enable this feature */
486
487#ifdef BIG_DAC_CHANGE_RECALIBRATION
488#define FREQ_OFF_THR 11700 /* 13ppm freqeuncy offset based on 900MHz */
489#define FREQ_OFF_VALID 65528 /* Valid DAC frequency offset shall be below 8191x8=65528(Hz) */
490#define INVALID_FREQ_OFF 0x7FFFFFFF /* When L1D/UL1D detect the frequency error is unreliable, return 0x7FFFFFFF to sleep mode */
491#endif //BIG_DAC_CHANGE_RECALIBRATION
492
493typedef enum
494{
495 PS_USIP_FORCEON_USER_AUDIO = 0,
496 PS_USIP_FORCEON_USER_LOG,
497 NUM_OF_USIP_FORCEON_USER
498} PS_USIP_FORCEON_USER;
499
500typedef enum
501{
502 SRCLK_FORCEON_USER_SIM = 0,
503 SRCLK_FORCEON_USER_USB,
504#if defined(__MD97__) && defined(__MTK_TARGET__) && defined(MT6297)
505 SRCLK_FORCEON_USER_DRAM,
506#endif
507 NUM_OF_SRCLK_FORCEON_USER
508} SRCLK_FORCEON_USER;
509
510typedef enum
511{
512 PS_PLL_FORCEON_USER_CTI = 0,
513 PS_PLL_FORCEON_USER_SIB,
514 NUM_OF_PLL_FORCEON_USER
515} PS_PLL_FORCEON_USER;
516
517typedef enum
518{
519#if defined(__MD93__)
520 PS_TOPSM_MDCORE_PLL = 0,
521 PS_TOPSM_BUS2X_PLL,
522 PS_TOPSM_F208M_PLL,
523 PS_TOPSM_DBG_PLL,
524 PS_TOPSM_LOG_PLL,
525 PS_TOPSM_SDF_ATB_PLL,
526 NUM_OF_PS_TOPSM_PLL,
527#elif defined(__MD95__)
528 PS_TOPSM_MDCORE_PLL = 0,
529 PS_TOPSM_BUS2X_PLL = 1,
530 PS_TOPSM_F208M_PLL = 2,
531 PS_TOPSM_DBG_PLL = 3,
532 PS_TOPSM_LOG_PLL = 4,
533 PS_TOPSM_SDF_ATB_PLL = 5,
534 PS_TOPSM_MML2_PLL = 6,
535 NUM_OF_PS_TOPSM_PLL = 7,
536#elif defined(__MD97__) || defined(__MD97P__)
537 PS_TOPSM_MDCORE_PLL = 0,
538 PS_TOPSM_BUS4X_PLL = 1,
539 PS_TOPSM_F208M_PLL = 2,
540 PS_TOPSM_DBG_PLL = 3,
541 PS_TOPSM_LOG_PLL = 4,
542 PS_TOPSM_SDF_ATB_PLL = 5,
543 PS_TOPSM_MML2_PLL = 6,
544 PS_TOPSM_SHAOLIN_PLL = 7,
545 PS_TOPSM_IA_PLL = 8,
546 NUM_OF_PS_TOPSM_PLL = 9,
547#else
548 #error "no chip match"
549#endif
550} PS_TOPSM_PLL;
551
552typedef enum
553{
554#if defined(__MD93__)
555 SLEEP_CTL_SLEEP_DRV = 0, // 0x00, Allow AT cmd to control cores' sleep function
556 SLEEP_CTL_SCC = 1, // 0x01, Disable sleep for PHY capture debug usage
557 SLEEP_CTL_MML2 = 2, // 0x02, For MML2 force on period, IA cannot sleep
558 SLEEP_CTL_LHIF = 3, // 0x03, For CLDMA uplink scenario
559 SLEEP_CTL_DVFS = 4, // 0x04, Keep MD awake while debugging gear changing and PLL ready interrupt
560 SLEEP_CTL_3G_FDD_UL1D = 5, // 0x05, L1 lock CORE1 sleep before sending L2P CCIRQ to core1
561 SLEEP_CTL_USB = 6, // 0x06, To lock sleep when driver get rx gpd done event
562 SLEEP_CTL_ADT = 7, // 0x07, DL data by GDMA to ISPRAM0, we need to avoid power down core0
563 SLEEP_CTL_L4 = 8, // 0x08, AT+ESLP to control sleep mode
564 SLEEP_CTL_3G_TDD_TL1 = 9, // 0x09, TL1 lock core0 sleep in TL1C/TL1D wake up state and unlock core0 sleep in TL1C/TL1D sleep state
565 SLEEP_CTL_USIM0 = 10, // 0x0A,
566 SLEEP_CTL_USIM1 = 11, // 0x0B,
567 SLEEP_CTL_USIM2 = 12, // 0x0C,
568 SLEEP_CTL_USIM3 = 13, // 0x0D,
569 SLEEP_CTL_C2K_1X = 14, // 0x0E,
570 SLEEP_CTL_C2K_DO = 15, // 0x0F,
571 SLEEP_CTL_C2K_SS = 16, // 0x10,
572 SLEEP_CTL_2G_TDD_MPAL = 17, // 0x11, GAS lock CORE1 sleep before sending msg to core1
573 SLEEP_CTL_FM = 18, // 0x12, Lock sleep while do calibration
574 SLEEP_CTL_EL1SM = 19, // 0x13, To lock core0/core1 sleep when LTE timer wakeup
575 SLEEP_CTL_EL1SM_DEBUG = 20, // 0x14, Debug for LTE sleep mode verify
576 SLEEP_CTL_UL1SM = 21, // 0x15, To lock core0 sleep when 3G FDD timer wakeup
577 SLEEP_CTL_L1SM = 22, // 0x16, To lock core0 sleep when 2G timer wakeup
578 SLEEP_CTL_GCU = 23, // 0x17,
579 SLEEP_CTL_IDC = 24, // 0x18, Lock core until idc_uart tx confirms last two bytes of data was sent
580 SLEEP_CTL_SPEECH = 25, // 0x19, Lock core while MD speech is working
581 SLEEP_CTL_MTD_NAND = 26, // 0x1A, Not used in 93, but owner request to perserve for future use
582 SLEEP_CTL_RR_FDD = 27, // 0x1B, To Lock/Unlock MPAL sleep
583 SLEEP_CTL_2G_SMM_DPS = 28, // 0x1C, To Lock/Unlock 2G SMM in Dummy PS TASK
584 SLEEP_CTL_3G_SMM_DPS = 29, // 0x1D, To Lock/Unlock 3G SMM in Dummy PS TASK
585 SLEEP_CTL_3G_FDD_SLCE = 30, // 0x1E, To Lock CORE1 sleep when in 3G connected mode for stack 1
586 SLEEP_CTL_3G_FDD_SLCE2 = 31, // 0x1F, To Lock CORE1 sleep when in 3G connected mode for stack 2
587 SLEEP_CTL_3G_FDD_SLCE3 = 32, // 0x20, To Lock CORE1 sleep when in 3G connected mode for stack 3
588 SLEEP_CTL_EL2 = 33, // 0x21, To ensure mcu awake until EL2 polling complete
589 SLEEP_CTL_ERRC = 34, // 0x22, Lock current core for avoiding delay when lower layer control
590 SLEEP_CTL_ERRC2 = 35, // 0x23, Because in the L+L architecture, ERRC1 and ERRC2 are in the same task, both has sleep mode control requirement
591 SLEEP_CTL_PLS = 36, // 0x24, Lock sleep to make sure the user's tag will succeed in the PLS logging mode.
592 SLEEP_CTL_SIM1 = 37, // 0x25, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
593 SLEEP_CTL_SIM2 = 38, // 0x26, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
594 SLEEP_CTL_SIM3 = 39, // 0x27, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
595 SLEEP_CTL_SIM4 = 40, // 0x28, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
596 MAX_SLEEP_HANDLE = 46
597#elif defined(__MD95__)
598 SLEEP_CTL_SLEEP_DRV = 0, // 0x00, Allow AT cmd to control cores' sleep function
599 SLEEP_CTL_SCC = 1, // 0x01, Disable sleep for PHY capture debug usage
600 SLEEP_CTL_MML2 = 2, // 0x02, For MML2 force on period, IA cannot sleep
601 SLEEP_CTL_LHIF = 3, // 0x03, For CLDMA uplink scenario
602 SLEEP_CTL_DVFS = 4, // 0x04, Keep MD awake while debugging gear changing and PLL ready interrupt
603 SLEEP_CTL_USB = 5, // 0x05, To lock sleep when driver get rx gpd done event
604 SLEEP_CTL_L4 = 6, // 0x06, AT+ESLP to control sleep mode
605 SLEEP_CTL_3G_TDD_TL1 = 7, // 0x07, TL1 lock core0 sleep in TL1C/TL1D wake up state and unlock core0 sleep in TL1C/TL1D sleep state
606 SLEEP_CTL_USIM0 = 8, // 0x08,
607 SLEEP_CTL_USIM1 = 9, // 0x09,
608 SLEEP_CTL_USIM2 = 10, // 0x0A,
609 SLEEP_CTL_USIM3 = 11, // 0x0B,
610 SLEEP_CTL_C2K_1X = 12, // 0x0C,
611 SLEEP_CTL_C2K_DO = 13, // 0x0D,
612 SLEEP_CTL_C2K_SS = 14, // 0x0E,
613 SLEEP_CTL_2G_TDD_MPAL = 15, // 0x0F, GAS lock CORE1 sleep before sending msg to core1
614 SLEEP_CTL_FM = 16, // 0x10, Lock sleep while do calibration
615 SLEEP_CTL_EL1SM = 17, // 0x11, To lock core0/core1 sleep when LTE timer wakeup
616 SLEEP_CTL_EL1SM_DEBUG = 18, // 0x12, Debug for LTE sleep mode verify
617 SLEEP_CTL_UL1SM = 19, // 0x13, To lock core0 sleep when 3G FDD timer wakeup
618 SLEEP_CTL_L1SM = 20, // 0x14, To lock core0 sleep when 2G timer wakeup
619 SLEEP_CTL_IDC = 21, // 0x15, Lock core until idc_uart tx confirms last two bytes of data was sent
620 SLEEP_CTL_MTD_NAND = 22, // 0x16, Not used in 93, but owner request to perserve for future use
621 SLEEP_CTL_RR_FDD = 23, // 0x17, To Lock/Unlock MPAL sleep
622 SLEEP_CTL_2G_SMM_DPS = 24, // 0x18, To Lock/Unlock 2G SMM in Dummy PS TASK
623 SLEEP_CTL_3G_SMM_DPS = 25, // 0x19, To Lock/Unlock 3G SMM in Dummy PS TASK
624 SLEEP_CTL_3G_FDD_SLCE = 26, // 0x1A, To Lock CORE1 sleep when in 3G connected mode for stack 1
625 SLEEP_CTL_3G_FDD_SLCE2 = 27, // 0x1B, To Lock CORE1 sleep when in 3G connected mode for stack 2
626 SLEEP_CTL_3G_FDD_SLCE3 = 28, // 0x1C, To Lock CORE1 sleep when in 3G connected mode for stack 3
627 SLEEP_CTL_ERRC = 29, // 0x1D, Lock current core for avoiding delay when lower layer control
628 SLEEP_CTL_ERRC2 = 30, // 0x1E, because in the L+L architecture, ERRC1 and ERRC2 are in the same task, both has sleep mode control requirement
629 SLEEP_CTL_PLS = 31, // 0x1F, lock sleep to make sure the user's tag will successd in PLS logging mode
630 SLEEP_CTL_SS = 32, // 0x20, for performance profiling
631 SLEEP_CTL_SOE = 33, // 0x21, lock CPU when using SOE
632 SLEEP_CTL_SPEECH = 34, // 0x22, reserved enum for speech
633 SLEEP_CTL_SIM1 = 35, // 0x23, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
634 SLEEP_CTL_SIM2 = 36, // 0x24, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
635 SLEEP_CTL_SIM3 = 37, // 0x25, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
636 SLEEP_CTL_SIM4 = 38, // 0x26, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
637 SLEEP_CTL_MML1 = 39,
638 MAX_SLEEP_HANDLE = 40
639#elif defined(__MD97__) || defined(__MD97P__)
640 SLEEP_CTL_SLEEP_DRV = 0, // 0x00, Allow AT cmd to control cores' sleep function
641 SLEEP_CTL_SCC = 1, // 0x01, Disable sleep for PHY capture debug usage
642 SLEEP_CTL_MML2 = 2, // 0x02, For MML2 force on period, IA cannot sleep
643 SLEEP_CTL_LHIF = 3, // 0x03, For CLDMA uplink scenario
644 SLEEP_CTL_DVFS = 4, // 0x04, Keep MD awake while debugging gear changing and PLL ready interrupt
645 SLEEP_CTL_USB = 5, // 0x05, To lock sleep when driver get rx gpd done event
646 SLEEP_CTL_L4 = 6, // 0x06, AT+ESLP to control sleep mode
647 SLEEP_CTL_3G_TDD_TL1 = 7, // 0x07, TL1 lock core0 sleep in TL1C/TL1D wake up state and unlock core0 sleep in TL1C/TL1D sleep state
648 SLEEP_CTL_USIM0 = 8, // 0x08
649 SLEEP_CTL_USIM1 = 9, // 0x09
650 SLEEP_CTL_USIM2 = 10, // 0x0A
651 SLEEP_CTL_USIM3 = 11, // 0x0B
652 SLEEP_CTL_C2K_1X = 12, // 0x0C
653 SLEEP_CTL_C2K_DO = 13, // 0x0D
654 SLEEP_CTL_C2K_SS = 14, // 0x0E
655 SLEEP_CTL_2G_TDD_MPAL = 15, // 0x0F, GAS lock CORE1 sleep before sending msg to core1
656 SLEEP_CTL_FM = 16, // 0x10, Lock sleep while do calibration
657 SLEEP_CTL_EL1SM = 17, // 0x11, To lock core0/core1 sleep when LTE timer wakeup
658 SLEEP_CTL_EL1SM_DEBUG = 18, // 0x12, Debug for LTE sleep mode verify
659 SLEEP_CTL_UL1SM = 19, // 0x13, To lock core0 sleep when 3G FDD timer wakeup
660 SLEEP_CTL_L1SM = 20, // 0x14, To lock core0 sleep when 2G timer wakeup
661 SLEEP_CTL_IDC = 21, // 0x15, Lock core until idc_uart tx confirms last two bytes of data was sent
662 SLEEP_CTL_MTD_NAND = 22, // 0x16, Not used in 93, but owner request to perserve for future use
663 SLEEP_CTL_RR_FDD = 23, // 0x17, To Lock/Unlock MPAL sleep
664 SLEEP_CTL_2G_SMM_DPS = 24, // 0x18, To Lock/Unlock 2G SMM in Dummy PS TASK
665 SLEEP_CTL_3G_SMM_DPS = 25, // 0x19, To Lock/Unlock 3G SMM in Dummy PS TASK
666 SLEEP_CTL_3G_FDD_SLCE = 26, // 0x1A, To Lock CORE1 sleep when in 3G connected mode for stack 1
667 SLEEP_CTL_3G_FDD_SLCE2 = 27, // 0x1B, To Lock CORE1 sleep when in 3G connected mode for stack 2
668 SLEEP_CTL_3G_FDD_SLCE3 = 28, // 0x1C, To Lock CORE1 sleep when in 3G connected mode for stack 3
669 SLEEP_CTL_ERRC = 29, // 0x1D, Lock current core for avoiding delay when lower layer control
670 SLEEP_CTL_ERRC2 = 30, // 0x1E, Because in the L+L architecture, ERRC1 and ERRC2 are in the same task, both has sleep mode control requirement
671 SLEEP_CTL_PLS = 31, // 0x1F, lock sleep to make sure the user's tag will successd in PLS logging mode
672 SLEEP_CTL_SS = 32, // 0x20, for performance profiling
673 SLEEP_CTL_SOE = 33, // 0x21, lock CPU when using SOE
674 SLEEP_CTL_SPEECH = 34, // 0x22, reserved enum for speech
675 SLEEP_CTL_SIM1 = 35, // 0x23, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
676 SLEEP_CTL_SIM2 = 36, // 0x24, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
677 SLEEP_CTL_SIM3 = 37, // 0x25, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
678 SLEEP_CTL_SIM4 = 38, // 0x26, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
679 SLEEP_CTL_NL1SM = 39, // 0x27
680 SLEEP_CTL_NL1SM_DEBUG = 40, // 0x28
681 SLEEP_CTL_MML1 = 41, // 0x29
682 SLEEP_CTL_USB_2 = 42, // 0x2A
683 SLEEP_CTL_CLDMA = 43, // 0x2B
684 SLEEP_CTL_LVTS_RESET = 44, // 0x2C
685 SLEEP_CTL_MCF = 45, // 0x2D
686 SLEEP_CTL_USBCORE = 46, // 0x2E
687 MAX_SLEEP_HANDLE = 47
688#else
689 #error "no chip match"
690#endif
691
692} SLEEP_CTL_USER;
693
694
695typedef enum
696{
697 MDLPM_VERSION = 0, //MDLPM_VERSION
698 MDLPM_REC_INDEX = 1, //MD RECORD INDEX
699 MDLPM_UTC_0 = 2, //UTC 0~31 bits
700 MDLPM_UTC_1 = 3, //UTC 32~63 bits
701 MDLPM_FRC = 4, //MD Free RUN Counter
702 MDLPM_TIMESTAMP = 5, //MD UTC Timestamp
703 MDLPM_WALL_CLK_0 = 6, //MD Wall Clock 0~31 bits
704 MDLPM_WALL_CLK_1 = 7, //MD Wall Clock 32~63 bits
705 MDLPM_MD_SLEEP_DUR = 8, //MD 26M Off tick
706 MDLPM_SOC_SLEEP_DUR = 9, //SOC 26M off tick
707 MDLPM_MD_TOPSM_PWR_RDY = 10, //MD_TOPSM PWR READY
708 MDLPM_MD_SW_LOCK_0 = 11, //SW Lock 0~31 bit
709 MDLPM_MD_SW_LOCK_1 = 12, //SW Lock 32~64 bit
710 MDLPM_MD_DATA13 = 13, //unused
711 MDLPM_MD_DATA14 = 14, //unused
712 MDLPM_MD_OST_F32_WAKEUP_0 = 15, //32k wakeup event 0~31 bit
713 MDLPM_MD_OST_F32_WAKEUP_1 = 16, //32k wakeup event 32~63 bit
714 MDLPM_MD_OST_26M_WAKEUP_0 = 17, //26m wakeup event 0~31 bit
715 MDLPM_MD_OST_26M_WAKEUP_1 = 18, //26m wakeup event 32~63 bit
716 MDLPM_MD_TOPSM_SLV_REQ_STA = 19, //MD_TOPSM SLV_REQ
717 MDLPM_MD_TOPSM_DBG_REQ_STA = 20, //MD_TOPSM DBG_REQ
718 MDLPM_MDMCU_IDLE_TIME = 21, //Reserve for MD_TOPSM extend
719 MDLPM_USIP_IDLE_TIME = 22, //Reserve for MD_TOPSM extend
720 MDLPM_DATA23 = 23, //Reserve for MD_TOPSM extend
721
722 // AMIF & MD DVFS
723 MDLPM_AMIF_GROUP_0 = 24, //unused
724 MDLPM_AMIF_GROUP_1 = 25, //unused
725 MDLPM_AMIF_GROUP_2 = 26, //unused
726 MDLPM_AMIF_GROUP_3 = 27, //unused
727 MDLPM_AMIF_GROUP_4 = 28, //unused
728 MDLPM_AMIF_GROUP_5 = 29, //unused
729 MDLPM_AMIF_GROUP_6 = 30, //unused
730 MDLPM_AMIF_GROUP_7 = 31, //unused
731 MDLPM_MD_DVFS_GEAR_0 = 32, //MD DVFS
732 MDLPM_MD_DVFS_GEAR_1 = 33, //MD DVFS
733 MDLPM_MD_DVFS_GEAR_2 = 34, //MD DVFS
734 MDLPM_MD_DVFS_GEAR_3 = 35, //MD DVFS
735 MDLPM_MD_DVFS_GEAR_4 = 36, //MD DVFS
736 MDLPM_MD_DVFS_GEAR_5 = 37, //MD DVFS
737 MDLPM_MD_DVFS_GEAR_6 = 38, //MD DVFS
738 MDLPM_MD_DVFS_GEAR_7 = 39, //MD DVFS
739
740 //Others
741 MDLPM_DATA40 = 40, //unused
742 MDLPM_DATA41 = 41, //unused
743 MDLPM_DATA42 = 42, //unused
744 MDLPM_DATA43 = 43, //unused
745 MDLPM_VOLTE_UL = 44, //VOLTE UL
746 MDLPM_VOLTE_DL = 45, //VOLTE DL
747 MDLPM_VOLTE_CODEC = 46, //VOLTE CODEC
748 MDLPM_DATA47 = 47, //unsued
749
750 /* debug info in 93 adding */
751 MDLPM_GL1_SLEEP_ACTIVE_DUR = 48, //2G acc sleep info.
752 MDLPM_GL1_SLEEP_STATUS = 49, //2G sleep status info.
753 MDLPM_UL1_SLEEP_ACTIVE_DUR = 50, //3G acc sleep info.
754 MDLPM_UL1_SLEEP_STATUS = 51, //2G sleep status info.
755 MDLPM_EL1_SLEEP_ACTIVE_DUR = 52, //3G acc sleep info.
756 MDLPM_EL1_SLEEP_STATUS = 53, //2G sleep status info.
757 MDLPM_MODEM_TOPSM_SM_TOPSM_APP_OUTCR_SET = 54,
758 MDLPM_MODEM_TOPSM_SM_DBG_REQ_STA = 55,
759 MDLPM_MODEM_TOPSM_DEBUG = 56,
760 /* debug info in 93 adding end */
761 /* 2G L1 behavior list */
762 MDLPM_GL1_BCCH = 57,
763 MDLPM_GL1_PAGING = 58,
764 MDLPM_GL1_CBCH = 59,
765 MDLPM_GL1_POWER_SCAN = 60,
766 MDLPM_GL1_BSIC_READ = 61, //FB/SB
767 MDLPM_GL1_STANDBY_GAP = 62,
768 MDLPM_GL1_ACCESS = 63, //Access mode is RACH in UL and listening AGCH/CCCH in DL
769 MDLPM_GL1_CS = 64, //dedicated mode circuit-switch
770 MDLPM_GL1_PS = 65, //dedicated mode packet-switch
771 /* 3G L1 behavior list */
772 MDLPM_UL1_BCH = 66, //BCH channel such as SIB/SFN
773 MDLPM_UL1_PCH = 67, //PCH channel
774 MDLPM_UL1_CTCH = 68, //CTCH channel
775 MDLPM_UL1_FS = 69, //frequency scan or power scan
776 MDLPM_UL1_CS = 70, //cell search
777 MDLPM_UL1_CM = 71, //cell measurement
778 MDLPM_UL1_TAS = 72, //TAS/RAS feature
779 MDLPM_UL1_ACTIVE_GAP = 73, //active gap assignment
780 MDLPM_UL1_STANDBY_GAP = 74, //receive standby gap
781 MDLPM_UL1_FACH = 75, //FACH/RACH channel
782 MDLPM_UL1_DCH = 76, //DCH channel
783 MDLPM_UL1_R5R6 = 77, //R5/R6 channel
784 MDLPM_UL1_R7R8 = 78, //R7/R8 channel
785 MDLPM_UL1_OTHERS = 79,
786 MDLPM_UL1_RESOURCE = 80, //RTB or Inter-SIM resource
787 MDLPM_UL1_CC = 81, //channel/mode change
788 MDLPM_UL1_DDL = 82, //DDL
789 MDLPM_UL1_EM = 83, //EM
790 /* 4G L1 behavior list */
791 MDLPM_EL1_MIB_SIB = 84,
792 MDLPM_EL1_PAGE = 85,
793 MDLPM_EL1_CSR = 86,
794 MDLPM_EL1_INTRA_CS = 87,
795 MDLPM_EL1_INTER_CS = 88,
796 MDLPM_EL1_INTRA_CM = 89,
797 MDLPM_EL1_INTER_CM = 90,
798 MDLPM_EL1_INTRA_POS = 91,
799 MDLPM_EL1_INTER_POS = 92,
800 MDLPM_EL1_MBMS = 93,
801 MDLPM_EL1_ACTIVE_GAP = 94, //active gap assignment
802 MDLPM_EL1_STANDBY_GAP = 95, //receive standby gap
803 MDLPM_EL1_CONNECT_START = 96,
804 MDLPM_EL1_CONNECT_END = 97,
805 MDLPM_EL1_CONNECT_DUR = 98, //accumulated connection duration
806 /* RAT L1 behavior list end */
807 /* MLL1 activate RAT monitor data start*/
808 MDLPM_SIM1_ACTIVATE_RAT = 99, //SIM1 activate RAT
809 MDLPM_SIM1_RAT_DRX = 100, //SIM1 activate RAT drx
810 MDLPM_SIM1_UPDATE_FRC = 101, //SIM1 info. update FRC
811 MDLPM_SIM2_ACTIVATE_RAT = 102, //SIM2 activate RAT
812 MDLPM_SIM2_RAT_DRX = 103, //SIM2 activate RAT drx
813 MDLPM_SIM2_UPDATE_FRC = 104, //SIM2 info. update FRC
814 MDLPM_SIM3_ACTIVATE_RAT = 105, //SIM3 activate RAT
815 MDLPM_SIM3_RAT_DRX = 106, //SIM3 activate RAT drx
816 MDLPM_SIM3_UPDATE_FRC = 107, //SIM3 info. update FRC
817 /* 2G monitor data start*/
818 MDLPM_GL1_RX_WINDOW_DUR = 108, //2G RX window open duration
819 MDLPM_GL1_TX_WINDOW_DUR = 109, //2G TX window open duration
820 MDLPM_GL1_TX_POWER_REG1 = 110, //2G TX power region 1: 0 ~ 5dBm; [0, 5]
821 MDLPM_GL1_TX_POWER_REG2 = 111, //2G TX power region 2: 5 ~ 10dBm; (5, 10]
822 MDLPM_GL1_TX_POWER_REG3 = 112, //2G TX power region 3: 10 ~ 15dBm; (10, 15]
823 MDLPM_GL1_TX_POWER_REG4 = 113, //2G TX power region 4: 15 ~ 20dBm; (15, 20]
824 MDLPM_GL1_TX_POWER_REG5 = 114, //2G TX power region 5: 20 ~ 25dBm; (20, 25]
825 MDLPM_GL1_TX_POWER_REG6 = 115, //2G TX power region 6: 25 ~ 30dBm; (25, 30]
826 MDLPM_GL1_TX_POWER_REG7 = 116, //2G TX power region 7: 30 ~ 33dBm; (30, 33]
827 /* 2G monitor data end */
828 /* 3G monitor data start */
829 MDLPM_UL1_RX_WINDOW_START = 117, //3G RX window open start frc
830 MDLPM_UL1_TX_WINDOW_START = 118, //3G TX window open start frc
831 MDLPM_UL1_RX_PATH_USED = 119, //3G RX path used flag
832 MDLPM_UL1_TX_PATH_USED = 120, //3G TX path used flag
833 MDLPM_UL1_RX_PATH1_CNT = 121, //3G use RX path 1 used cnt
834 MDLPM_UL1_RX_PATH2_CNT = 122, //3G use RX path 2 used cnt
835 MDLPM_UL1_RX_PATH3_CNT = 123, //3G use RX path 3 used cnt
836 MDLPM_UL1_RX_PATH4_CNT = 124, //3G use RX path 4 used cnt
837 MDLPM_UL1_RX_PATH5_CNT = 125, //3G use RX path 5 used cnt
838 MDLPM_UL1_RX_PATH6_CNT = 126, //3G use RX path 6 used cnt
839 MDLPM_UL1_TX_PATH1_CNT = 127, //3G use TX path 1 used cnt
840 MDLPM_UL1_TX_PATH2_CNT = 128, //3G use TX path 2 used cnt
841 MDLPM_UL1_RX_WINDOW_DUR = 129, //3G RX window open duration
842 MDLPM_UL1_TX_WINDOW_DUR = 130, //3G TX window open duration
843 MDLPM_UL1_TX_POWER_REG1 = 131, //3G TX power region 1: <= -5dBm
844 MDLPM_UL1_TX_POWER_REG2 = 132, //3G TX power region 2: -5 ~ 1dBm; (-5, 1]
845 MDLPM_UL1_TX_POWER_REG3 = 133, //3G TX power region 3: 1 ~ 5dBm; (1,5]
846 MDLPM_UL1_TX_POWER_REG4 = 134, //3G TX power region 4: 5 ~ 10dBm; (5,10]
847 MDLPM_UL1_TX_POWER_REG5 = 135, //3G TX power region 5: 10 ~ 15dBm; (10,15]
848 MDLPM_UL1_TX_POWER_REG6 = 136, //3G TX power region 6: 15 ~ 20dBm; (15,20]
849 MDLPM_UL1_TX_POWER_REG7 = 137, //3G TX power region 7: 20 ~ 24dBm; (20,24]
850 MDLPM_UL1_LORX_MODE0 = 138, //3G LoRX mode 0 (LORX_OFF) cnt
851 MDLPM_UL1_LORX_MODE1 = 139, //3G LoRX mode 1 (LORX_ON) cnt
852 MDLPM_UL1_LORX_TRIG_FALSE = 140, //3G LoRX triger is false
853 MDLPM_UL1_LORX_TRIG_TRUE = 141, //3G LoRX triger is true
854 MDLPM_UL1_ARX_HPM = 142, //3G ARX mode 0 (HPM) cnt
855 MDLPM_UL1_ARX_LPM_VOICE = 143, //3G ARX mode 1 (LPM_VOICE) cnt
856 MDLPM_UL1_ARX_LPM_DATA = 144, //3G ARX mode 2 (LPM_DATA) cnt
857 MDLPM_UL1_RAS_1RX_INVALID = 145, //3G RAS mode 0 (1RX_INVALID) cnt
858 MDLPM_UL1_RAS_1RX_PATH_MAIN = 146, //3G RAS mode 1 (1RX_PATH_MAIN) cnt
859 MDLPM_UL1_RAS_2RX_PATH_BOTH = 147, //3G RAS mode 2 (2RX_PATH_BOTH) cnt
860 /* 3G monitor data end */
861 /* 4G monitor data start */
862 MDLPM_EL1_ACTIVE_1CC = 148, //active 1CC (Pcell only) cnt
863 MDLPM_EL1_ACTIVE_2CC = 149, //active 2CC cnt
864 MDLPM_EL1_ACTIVE_3CC = 150, //active 3CC cnt
865 MDLPM_EL1_ACTIVE_4CC = 151, //active 4CC cnt
866 MDLPM_EL1_ACTIVE_5CC = 152, //active 5CC cnt
867 MDLPM_EL1_CC_LAST = 153, //last active CC number
868 MDLPM_EL1_CC_LAST_FRC = 154, //last active CC number
869 MDLPM_EL1_RX_WINDOW_START = 155, //4G RX window open start frc
870 MDLPM_EL1_TX_WINDOW_START = 156, //4G TX window open start frc
871 MDLPM_EL1_RX_PATH_USED = 157, //4G RX path used flag
872 MDLPM_EL1_TX_PATH_USED = 158, //4G TX path used flag
873 MDLPM_EL1_RX_PATH1_CNT = 159, //4G use RX path 1 used cnt
874 MDLPM_EL1_RX_PATH2_CNT = 160, //4G use RX path 2 used cnt
875 MDLPM_EL1_RX_PATH3_CNT = 161, //4G use RX path 3 used cnt
876 MDLPM_EL1_RX_PATH4_CNT = 162, //4G use RX path 4 used cnt
877 MDLPM_EL1_RX_PATH5_CNT = 163, //4G use RX path 5 used cnt
878 MDLPM_EL1_TX_PATH1_CNT = 164, //4G use TX path 1 used cnt
879 MDLPM_EL1_TX_PATH2_CNT = 165, //4G use TX path 2 used cnt
880 MDLPM_EL1_RX_WINDOW_DUR = 166, //4G RX window open duration
881 MDLPM_EL1_TX_WINDOW_DUR = 167, //4G TX window open duration
882 MDLPM_EL1_TX_POWER_CC0_REG1 = 168, //4G CC0 TX power region 1: <= -5dBm
883 MDLPM_EL1_TX_POWER_CC0_REG2 = 169, //4G CC0 TX power region 2: -5 ~ 1dBm; (-5, 1]
884 MDLPM_EL1_TX_POWER_CC0_REG3 = 170, //4G CC0 TX power region 3: 1 ~ 5dBm; (1,5]
885 MDLPM_EL1_TX_POWER_CC0_REG4 = 171, //4G CC0 TX power region 4: 5 ~ 10dBm; (5,10]
886 MDLPM_EL1_TX_POWER_CC0_REG5 = 172, //4G CC0 TX power region 5: 10 ~ 15dBm; (10,15]
887 MDLPM_EL1_TX_POWER_CC0_REG6 = 173, //4G CC0 TX power region 6: 15 ~ 20dBm; (15,20]
888 MDLPM_EL1_TX_POWER_CC0_REG7 = 174, //4G CC0 TX power region 7: 20 ~ 23dBm; (20,23]
889 MDLPM_EL1_TX_POWER_CC0_REG8 = 175, //4G CC0 TX power region 8: 23 ~ 26dBm; (23,26]
890 MDLPM_EL1_TX_POWER_CC1_REG1 = 176, //4G CC1 TX power region 1: <= -5dBm
891 MDLPM_EL1_TX_POWER_CC1_REG2 = 177, //4G CC1 TX power region 2: -5 ~ 1dBm; (-5, 1]
892 MDLPM_EL1_TX_POWER_CC1_REG3 = 178, //4G CC1 TX power region 3: 1 ~ 5dBm; (1,5]
893 MDLPM_EL1_TX_POWER_CC1_REG4 = 179, //4G CC1 TX power region 4: 5 ~ 10dBm; (5,10]
894 MDLPM_EL1_TX_POWER_CC1_REG5 = 180, //4G CC1 TX power region 5: 10 ~ 15dBm; (10,15]
895 MDLPM_EL1_TX_POWER_CC1_REG6 = 181, //4G CC1 TX power region 6: 15 ~ 20dBm; (15,20]
896 MDLPM_EL1_TX_POWER_CC1_REG7 = 182, //4G CC1 TX power region 7: 20 ~ 23dBm; (20,23]
897 MDLPM_EL1_TX_POWER_CC1_REG8 = 183, //4G CC1 TX power region 8: 23 ~ 26dBm; (23,26]
898 MDLPM_EL1_TX_POWER_CC2_REG1 = 184, //4G CC2 TX power region 1: <= -5dBm
899 MDLPM_EL1_TX_POWER_CC2_REG2 = 185, //4G CC2 TX power region 2: -5 ~ 1dBm; (-5, 1]
900 MDLPM_EL1_TX_POWER_CC2_REG3 = 186, //4G CC2 TX power region 3: 1 ~ 5dBm; (1,5]
901 MDLPM_EL1_TX_POWER_CC2_REG4 = 187, //4G CC2 TX power region 4: 5 ~ 10dBm; (5,10]
902 MDLPM_EL1_TX_POWER_CC2_REG5 = 188, //4G CC2 TX power region 5: 10 ~ 15dBm; (10,15]
903 MDLPM_EL1_TX_POWER_CC2_REG6 = 189, //4G CC2 TX power region 6: 15 ~ 20dBm; (15,20]
904 MDLPM_EL1_TX_POWER_CC2_REG7 = 190, //4G CC2 TX power region 7: 20 ~ 23dBm; (20,23]
905 MDLPM_EL1_TX_POWER_CC2_REG8 = 191, //4G CC2 TX power region 8: 23 ~ 26dBm; (23,26]
906 MDLPM_EL1_TX_POWER_ALL_REG1 = 192, //4G total TX power region 1: <= -5dBm
907 MDLPM_EL1_TX_POWER_ALL_REG2 = 193, //4G total TX power region 2: -5 ~ 1dBm; (-5, 1]
908 MDLPM_EL1_TX_POWER_ALL_REG3 = 194, //4G total TX power region 3: 1 ~ 5dBm; (1,5]
909 MDLPM_EL1_TX_POWER_ALL_REG4 = 195, //4G total TX power region 4: 5 ~ 10dBm; (5,10]
910 MDLPM_EL1_TX_POWER_ALL_REG5 = 196, //4G total TX power region 5: 10 ~ 15dBm; (10,15]
911 MDLPM_EL1_TX_POWER_ALL_REG6 = 197, //4G total TX power region 6: 15 ~ 20dBm; (15,20]
912 MDLPM_EL1_TX_POWER_ALL_REG7 = 198, //4G total TX power region 7: 20 ~ 23dBm; (20,23]
913 MDLPM_EL1_TX_POWER_ALL_REG8 = 199, //4G total TX power region 8: 23 ~ 26dBm; (23,26]
914 MDLPM_EL1_LORX_MODE0 = 200, //4G LoRX mode 0 (LORX_OFF) cnt
915 MDLPM_EL1_LORX_MODE1 = 201, //4G LoRX mode 1 (LORX_TYPE1, symobol mode) cnt
916 MDLPM_EL1_LORX_MODE2 = 202, //4G LoRX mode 2 (LORX_TYPE2, PDCCH early stop) cnt
917 MDLPM_EL1_LORX_MODE3 = 203, //4G LoRX mode 3 (LORX_TYPE3, PDCCH early stop with sync) cnt
918 MDLPM_EL1_LOSX_CC0_ENABLE = 204, //4G LoSX CC0 enable cnt
919 MDLPM_EL1_LOSX_CC1_ENABLE = 205, //4G LoSX CC1 enable cnt
920 MDLPM_EL1_LOSX_CC2_ENABLE = 206, //4G LoSX CC2 enable cnt
921 MDLPM_EL1_LOSX_CC3_ENABLE = 207, //4G LoSX CC3 enable cnt
922 MDLPM_EL1_LOSX_CC4_ENABLE = 208, //4G LoSX CC4 enable cnt
923 MDLPM_EL1_LORX_TRIG_FALSE = 209, //4G LoRX triger is false
924 MDLPM_EL1_LORX_TRIG_TRUE = 210, //4G LoRX triger is true
925 MDLPM_EL1_LOSX_CC0_TRIG = 211, //4G LoSX CC0 triger cnt
926 MDLPM_EL1_LOSX_CC1_TRIG = 212, //4G LoSX CC1 triger cnt
927 MDLPM_EL1_LOSX_CC2_TRIG = 213, //4G LoSX CC2 triger cnt
928 MDLPM_EL1_LOSX_CC3_TRIG = 214, //4G LoSX CC3 triger cnt
929 MDLPM_EL1_LOSX_CC4_TRIG = 215, //4G LoSX CC4 triger cnt
930 MDLPM_EL1_CC0_ARX_HPM = 216, //4G ARX CC0 mode 0 (HPM) cnt
931 MDLPM_EL1_CC0_ARX_LPM_DATA = 217, //4G ARX CC0 mode 1 (LPM_DATA) cnt
932 MDLPM_EL1_CC0_ARX_LPM_LMCS = 218, //4G ARX CC0 mode 2 (LPM_LMCS) cnt
933 MDLPM_EL1_CC0_ARX_LPM_VOICE = 219, //4G ARX CC0 mode 3 (LPM_VOICE) cnt
934 MDLPM_EL1_CC0_ARX_LPM_HMCS = 220, //4G ARX CC0 mode 4 (LPM_HMCS) cnt
935 MDLPM_EL1_CC1_ARX_HPM = 221, //4G ARX CC1 mode 0 (HPM) cnt
936 MDLPM_EL1_CC1_ARX_LPM_DATA = 222, //4G ARX CC1 mode 1 (LPM_DATA) cnt
937 MDLPM_EL1_CC1_ARX_LPM_LMCS = 223, //4G ARX CC1 mode 2 (LPM_LMCS) cnt
938 MDLPM_EL1_CC1_ARX_LPM_VOICE = 224, //4G ARX CC1 mode 3 (LPM_VOICE) cnt
939 MDLPM_EL1_CC1_ARX_LPM_HMCS = 225, //4G ARX CC1 mode 4 (LPM_HMCS) cnt
940 MDLPM_EL1_CC2_ARX_HPM = 226, //4G ARX CC2 mode 0 (HPM) cnt
941 MDLPM_EL1_CC2_ARX_LPM_DATA = 227, //4G ARX CC2 mode 1 (LPM_DATA) cnt
942 MDLPM_EL1_CC2_ARX_LPM_LMCS = 228, //4G ARX CC2 mode 2 (LPM_LMCS) cnt
943 MDLPM_EL1_CC2_ARX_LPM_VOICE = 229, //4G ARX CC2 mode 3 (LPM_VOICE) cnt
944 MDLPM_EL1_CC2_ARX_LPM_HMCS = 230, //4G ARX CC2 mode 4 (LPM_HMCS) cnt
945 MDLPM_EL1_CC3_ARX_HPM = 231, //4G ARX CC3 mode 0 (HPM) cnt
946 MDLPM_EL1_CC3_ARX_LPM_DATA = 232, //4G ARX CC3 mode 1 (LPM_DATA) cnt
947 MDLPM_EL1_CC3_ARX_LPM_LMCS = 233, //4G ARX CC3 mode 2 (LPM_LMCS) cnt
948 MDLPM_EL1_CC3_ARX_LPM_VOICE = 234, //4G ARX CC3 mode 3 (LPM_VOICE) cnt
949 MDLPM_EL1_CC3_ARX_LPM_HMCS = 235, //4G ARX CC3 mode 4 (LPM_HMCS) cnt
950 MDLPM_EL1_CC4_ARX_HPM = 236, //4G ARX CC4 mode 0 (HPM) cnt
951 MDLPM_EL1_CC4_ARX_LPM_DATA = 237, //4G ARX CC4 mode 1 (LPM_DATA) cnt
952 MDLPM_EL1_CC4_ARX_LPM_LMCS = 238, //4G ARX CC4 mode 2 (LPM_LMCS) cnt
953 MDLPM_EL1_CC4_ARX_LPM_VOICE = 239, //4G ARX CC4 mode 3 (LPM_VOICE) cnt
954 MDLPM_EL1_CC4_ARX_LPM_HMCS = 240, //4G ARX CC4 mode 4 (LPM_HMCS) cnt
955 MDLPM_EL1_CC0_RAS_1RX = 241, //4G RAS CC0 mode 0 (1RX) cnt
956 MDLPM_EL1_CC0_RAS_2RX = 242, //4G RAS CC0 mode 1 (2RX) cnt
957 MDLPM_EL1_CC0_RAS_4RX = 243, //4G RAS CC0 mode 2 (4RX) cnt
958 MDLPM_EL1_CC1_RAS_1RX = 244, //4G RAS CC1 mode 0 (1RX) cnt
959 MDLPM_EL1_CC1_RAS_2RX = 245, //4G RAS CC1 mode 1 (2RX) cnt
960 MDLPM_EL1_CC1_RAS_4RX = 246, //4G RAS CC1 mode 2 (4RX) cnt
961 MDLPM_EL1_CC2_RAS_1RX = 247, //4G RAS CC2 mode 0 (1RX) cnt
962 MDLPM_EL1_CC2_RAS_2RX = 248, //4G RAS CC2 mode 1 (2RX) cnt
963 MDLPM_EL1_CC2_RAS_4RX = 249, //4G RAS CC2 mode 2 (4RX) cnt
964 MDLPM_EL1_CC3_RAS_1RX = 250, //4G RAS CC3 mode 0 (1RX) cnt
965 MDLPM_EL1_CC3_RAS_2RX = 251, //4G RAS CC3 mode 1 (2RX) cnt
966 MDLPM_EL1_CC3_RAS_4RX = 252, //4G RAS CC3 mode 2 (4RX) cnt
967 MDLPM_EL1_CC4_RAS_1RX = 253, //4G RAS CC4 mode 0 (1RX) cnt
968 MDLPM_EL1_CC4_RAS_2RX = 254, //4G RAS CC4 mode 1 (2RX) cnt
969 MDLPM_EL1_CC4_RAS_4RX = 255, //4G RAS CC4 mode 2 (4RX) cnt
970 /* 4G monitor data end */
971
972 /* 5G monitor data start */
973 MDLPM_NL1_SLEEP_ACTIVE_DUR = 256, //5G acc sleep info.
974 MDLPM_NL1_SLEEP_STATUS = 257, //5G sleep status info.
975 MDLPM_NL1_MMW_SLEEP_ACTIVE_DUR = 258, //5G mmW acc sleep info.
976 MDLPM_NL1_MMW_SLEEP_STATUS = 259, //5G mmW sleep status info.
977 // RX/TX window related
978 MDLPM_NL1_RX_WINDOW_DUR = 260, //5G RX window acc. open duration
979 MDLPM_NL1_TX_WINDOW_DUR = 261, //5G TX window acc. open duration
980 MDLPM_NL1_CONNECT_DUR = 262, //5G connection duration
981 MDLPM_NL1_TX_POWER_TG0_CC0 = 263, //5G TX power info, 0=> below -5 , 1=>-5~1, 2=>1~5, 3=>5~10,4=>10~15,5=>15~20,6=>20~23,7=>23~26
982 MDLPM_NL1_TX_POWER_TG1_CC0 = 264, //5G TX power info, 0=> below -5 , 1=>-5~1, 2=>1~5, 3=>5~10,4=>10~15,5=>15~20,6=>20~23,7=>23~26
983 MDLPM_NL1_TX_POWER_TG2_CC0 = 265, //5G TX power info, 0=> below -5 , 1=>-5~1, 2=>1~5, 3=>5~10,4=>10~15,5=>15~20,6=>20~23,7=>23~26
984 MDLPM_NL1_ARX_TG0_CC0 = 266, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS
985 MDLPM_NL1_ARX_TG1_CC0 = 267, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS
986 MDLPM_NL1_ARX_TG2_CC0 = 268, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS
987 MDLPM_NL1_ARX_TG0_CC1 = 269, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS
988 MDLPM_NL1_ARX_TG1_CC1 = 270, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS
989 MDLPM_NL1_ARX_TG2_CC1 = 271, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS
990 MDLPM_NL1_ARX_TG0_CC0_CNT = 272, //5G ARX change counter info
991 MDLPM_NL1_ARX_TG1_CC0_CNT = 273, //5G ARX change counter info
992 MDLPM_NL1_ARX_TG2_CC0_CNT = 274, //5G ARX change counter info
993 MDLPM_NL1_ARX_TG0_CC1_CNT = 275, //5G ARX change counter info
994 MDLPM_NL1_ARX_TG1_CC1_CNT = 276, //5G ARX change counter info
995 MDLPM_NL1_ARX_TG2_CC1_CNT = 277, //5G ARX change counter info
996 MDLPM_NL1_RAS_TG0_CC0 = 278, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX
997 MDLPM_NL1_RAS_TG1_CC0 = 279, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX
998 MDLPM_NL1_RAS_TG2_CC0 = 280, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX
999 MDLPM_NL1_RAS_TG0_CC1 = 281, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX
1000 MDLPM_NL1_RAS_TG1_CC1 = 282, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX
1001 MDLPM_NL1_RAS_TG2_CC1 = 283, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX
1002 MDLPM_NL1_RAS_TG0_CC0_CNT = 284, //5G RAS change counter info
1003 MDLPM_NL1_RAS_TG1_CC0_CNT = 285, //5G RAS change counter info
1004 MDLPM_NL1_RAS_TG2_CC0_CNT = 286, //5G RAS change counter info
1005 MDLPM_NL1_RAS_TG0_CC1_CNT = 287, //5G RAS change counter info
1006 MDLPM_NL1_RAS_TG1_CC1_CNT = 288, //5G RAS change counter info
1007 MDLPM_NL1_RAS_TG2_CC1_CNT = 289, //5G RAS change counter info
1008 MDLPM_NL1_SLEEP_ACTIVE_DUR_TG0 = 290, //5G acc sleep info.
1009 MDLPM_NL1_SLEEP_STATUS_TG0 = 291, //5G sleep status info.
1010 MDLPM_NL1_SLEEP_ACTIVE_DUR_TG1 = 292, //5G acc sleep info.
1011 MDLPM_NL1_SLEEP_STATUS_TG1 = 293, //5G sleep status info.
1012 /* 5G monitor data end */
1013 MDLPM_MAX_ITEMS = 512
1014} MDLPM_INDEX;
1015
1016#ifdef SMP
1017#undef SMP
1018#endif
1019
1020typedef enum
1021{
1022 SMP = 0,
1023 CORE0 = 0,
1024 CORE1,
1025 CORE2,
1026 CORE3
1027} SLPDRV_CORE_e;
1028
1029//#ifdef BIG_DAC_CHANGE_RECALIBRATION
1030
1031typedef enum
1032{
1033 MODEM_TOPSM_INPUT_2G = 0, /* Input module is 2G */
1034 MODEM_TOPSM_INPUT_3G /* Input module is 3G */
1035} MODEM_TOPSM_INPUT_MODULE;
1036
1037typedef enum
1038{
1039 MODEM_TOPSM_RF1 = 0,
1040 MODEM_TOPSM_RF2,
1041 NUM_OF_CLOCK_SOURCE
1042} CLOCK_INPUT_SOURCE;
1043
1044//#endif
1045typedef enum{
1046#if defined(__MD93__)
1047 SLP_EMM_CORE0_SLP_SW_LOCK = 0,
1048 SLP_EMM_CORE0_SLP_SW_EXT_LOCK,
1049 SLP_EMM_CORE1_SLP_SW_LOCK,
1050 SLP_EMM_CORE1_SLP_SW_EXT_LOCK,
1051 SLP_EMM_CORE0_SLP_SW_LOCK_TIME,
1052 SLP_EMM_CORE1_SLP_SW_LOCK_TIME,
1053 SLP_EMM_CORE0_SLP_SW_UNLOCK_TIME,
1054 SLP_EMM_CORE1_SLP_SW_UNLOCK_TIME,
1055 SLP_EMM_SLP_INIFINITE_ENTER,
1056#elif defined(__MD95__)
1057 SLP_EMM_CORE0_SLP_SW_LOCK = 0,
1058 SLP_EMM_CORE0_SLP_SW_EXT_LOCK,
1059 SLP_EMM_CORE1_SLP_SW_LOCK,
1060 SLP_EMM_CORE1_SLP_SW_EXT_LOCK,
1061 SLP_EMM_CORE2_SLP_SW_LOCK,
1062 SLP_EMM_CORE2_SLP_SW_EXT_LOCK,
1063 SLP_EMM_CORE0_SLP_SW_LOCK_TIME,
1064 SLP_EMM_CORE1_SLP_SW_LOCK_TIME,
1065 SLP_EMM_CORE2_SLP_SW_LOCK_TIME,
1066 SLP_EMM_CORE0_SLP_SW_UNLOCK_TIME,
1067 SLP_EMM_CORE1_SLP_SW_UNLOCK_TIME,
1068 SLP_EMM_CORE2_SLP_SW_UNLOCK_TIME,
1069 SLP_EMM_SLP_INIFINITE_ENTER,
1070#elif defined(__MD97__) || defined(__MD97P__)
1071 SLP_EMM_CORE0_SLP_SW_LOCK = 0,
1072 SLP_EMM_CORE0_SLP_SW_EXT_LOCK,
1073 SLP_EMM_CORE1_SLP_SW_LOCK,
1074 SLP_EMM_CORE1_SLP_SW_EXT_LOCK,
1075 SLP_EMM_CORE2_SLP_SW_LOCK,
1076 SLP_EMM_CORE2_SLP_SW_EXT_LOCK,
1077 SLP_EMM_CORE3_SLP_SW_LOCK,
1078 SLP_EMM_CORE3_SLP_SW_EXT_LOCK,
1079 SLP_EMM_CORE0_SLP_SW_LOCK_TIME,
1080 SLP_EMM_CORE1_SLP_SW_LOCK_TIME,
1081 SLP_EMM_CORE2_SLP_SW_LOCK_TIME,
1082 SLP_EMM_CORE3_SLP_SW_LOCK_TIME,
1083 SLP_EMM_CORE0_SLP_SW_UNLOCK_TIME,
1084 SLP_EMM_CORE1_SLP_SW_UNLOCK_TIME,
1085 SLP_EMM_CORE2_SLP_SW_UNLOCK_TIME,
1086 SLP_EMM_CORE3_SLP_SW_UNLOCK_TIME,
1087 SLP_EMM_SLP_INIFINITE_ENTER,
1088#else
1089 #error "no chip match"
1090#endif
1091}SLP_EMM_LOG_INDEX;
1092
1093void SleepDrv_LockSleep( SLEEP_CTL_USER user, kal_uint8 target_core);
1094void SleepDrv_UnlockSleep( SLEEP_CTL_USER user, kal_uint8 target_core);
1095
1096void Sleep_DrvLowPowerMonitorInit(void);
1097
1098void SleepDrv_LowPowerMonitorFlushCheck( void );
1099void SleepDrv_LowPowerMonitorDelete(void);
1100void SleepDrv_LowPowerMonitorCreate(void);
1101void SleepDrv_LowPowerMonitorStart(void);
1102void SleepDrv_LowPowerMonitorStop(void);
1103kal_bool SleepDrv_LowPowerMonitorSetParameter(kal_uint32 data_len, kal_uint8 *data_str);
1104
1105void SleepDrv_UpdatePSSlpDbgShmFixBuf(SLP_DBG_SHM_FIX_REG_INDEX index, kal_uint32 value);
1106void SleepDrv_UpdateL1SlpDbgShmFixBuf(SLP_DBG_SHM_FIX_REG_INDEX index, kal_uint32 value);
1107void SleepDrv_SlpDbgShmRingBufAdd(SLP_DBG_SHM_RING_BUFFER_INDEX index, kal_uint32 status, kal_uint32 dbg_info);
1108
1109extern kal_bool MD_TOPSM_StartLPM(kal_uint8 data_str0, kal_uint8 data_str1, kal_uint8 data_str2);
1110extern kal_bool MD_TOPSM_DumpLPM(void);
1111
1112
1113/* MDTOPSM Public API */
1114extern kal_uint32 SleepDrv_GetWallClk(void);
1115extern kal_uint32 SleepDrv_GetWallClk_H(void);
1116extern void MD_TOPSM_EnableFRC(void); /* Enable FRC API for exception handling */
1117extern kal_uint8 MD_TOPSM_SRCLK_SW_Control_GetHandle( kal_char* module_name ); /* Register the module as a SRCLK force on user */
1118extern void MD_TOPSM_SRCLK_SW_Control( SRCLK_FORCEON_USER user, kal_bool fOn ); /* SW lock or unlock 26M */
1119extern void MD_TOPSM_PLL_SW_Control(PS_PLL_FORCEON_USER USER,PS_TOPSM_PLL PLL, kal_bool fOn);
1120extern void MD_TOPSM_USIP_SW_Control(PS_USIP_FORCEON_USER USER, kal_bool fOn);
1121
1122#include "reg_base.h"
1123
1124
1125#define GET_TOPSM_FRC_VAL_R() (*(volatile kal_uint32 *)(BASE_ADDR_MDTOPSM+0x830))
1126#define GET_TOPSM_FRC_SYNC_VAL_2G_US()
1127#define GET_TOPSM_FRC_SYNC_VAL_2G_26M()
1128#define GET_TOPSM_FRC_SYNC_VAL_3G_US()
1129#define GET_TOPSM_FRC_SYNC_VAL_3G_26M()
1130#define GET_TOPSM_FRC_SYNC_VAL_TDD_US()
1131#define GET_TOPSM_FRC_SYNC_VAL_TDD_26M()
1132#define SET_GPS_SYNC_TIME(_val)
1133
1134
1135
1136#ifdef BIG_DAC_CHANGE_RECALIBRATION
1137extern void MODEM_TOPSM_SetCurrentFreqOffset( kal_int32 freq_offset, MODEM_TOPSM_INPUT_MODULE module, CLOCK_INPUT_SOURCE clockSource );
1138extern void MODEM_TOPSM_SetFreqOffsetBase( kal_int32 freq_offset, MODEM_TOPSM_INPUT_MODULE module, CLOCK_INPUT_SOURCE clockSource );
1139#endif
1140
1141extern kal_uint32 MODEM_TOPSM_GetSSTA0(void);
1142extern kal_uint32 MODEM_TOPSM_GetSSTA1(void);
1143
1144extern kal_bool OSTD_Is3gEnabled (void);
1145
1146
1147#endif