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192.168.1.100 / T800_MD / 0b80c7188a6089ae59f523c5d460adad05960e1d / . / mcu / interface / driver / sys_drv / boot_comm.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * boot_comm.h
41 *
42 * Project:
43 * --------
44 * UMOLY_Software
45 *
46 * Description:
47 * ------------
48 *
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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135 *
136 * Rev 1.0 Nov 30 2002 19:49:52 admin
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138 *------------------------------------------------------------------------------
139 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
140 *============================================================================
141 ****************************************************************************/
142
143#ifndef _BOOT_COMM_H
144#define _BOOT_COMM_H
145
146#define TEMP_UNCACHE_BOOTSTACK_BANK (0x00000000)
147#define TEMP_UNCACHE_BOOTSTACK_MASK (0xF0000000)
148#define TEMP_CACHE_BOOTSTACK_BANK (0x6)
149
150
151#define BOOT_SYS_STACK_SIZE (1024)
152#define BOOT_CORE0_SYS_STACK_SIZE (BOOT_SYS_STACK_SIZE)
153#if !defined(__SINGLE_CORE__)
154#define BOOT_CORE1_SYS_STACK_SIZE (BOOT_SYS_STACK_SIZE)
155#if (defined(__MD95__) && !defined(__MD95_IS_2CORES__)) || (defined(MT6297_IA))
156#define BOOT_CORE2_SYS_STACK_SIZE (BOOT_SYS_STACK_SIZE)
157#endif
158#if (defined(MT6297_IA))
159#define BOOT_CORE3_SYS_STACK_SIZE (BOOT_SYS_STACK_SIZE)
160#endif
161#endif
162
163// bootup trace
164#define VPE_BOOTUP_TRC_SIZE (256) // bytes
165
166#define BOOTUP_TRC_OFFSET (1024*7)
167#define BOOTUP_TRC_MAGIC (0x746F6200) // ascii : nBOT
168
169#define BOOTUP_TRC_ID_LEN (10)
170#define BOOTUP_TRC_ID_MASK ((1<<BOOTUP_TRC_ID_LEN) - 1)
171#define BOOTUP_TRC_FRC_MASK (0xFFFFFFFF ^ BOOTUP_TRC_ID_MASK)
172
173#define BASE_MD_FMA_ADDR (GCR_CUSTOM_ADDR)
174#define MD_USCNTI_VAL_ADDR (BASE_MD_FMA_ADDR + 0x40)
175#if defined(__MD97__) || defined(__MD97P__)
176#if defined(MT6297)
177#define BOOTTRC_CCIF0_OLD_MAGIC_ADDR (MDCCIF_BOOTTRC_DATA)
178#define BOOTTRC_CCIF0_OLD_VPE0_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*1)
179#define BOOTTRC_CCIF0_OLD_VPE1_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*2)
180#define BOOTTRC_CCIF0_OLD_VPE2_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*3)
181#define BOOTTRC_CCIF0_OLD_VPE3_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*4)
182#define BOOTTRC_CCIF0_OLD_VPE4_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*5)
183#define BOOTTRC_CCIF0_OLD_VPE5_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*6)
184#define BOOTTRC_CCIF0_OLD_VPE6_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*7)
185#define BOOTTRC_CCIF0_OLD_VPE7_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*8)
186#define BOOTTRC_CCIF0_OLD_VPE8_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*9)
187#define BOOTTRC_CCIF0_OLD_VPE9_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*10)
188#define BOOTTRC_CCIF0_OLD_VPE10_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*11)
189#define BOOTTRC_CCIF0_OLD_VPE11_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*12)
190#else
191#define BOOTTRC_CCIF0_NEW_MAGIC_ADDR (MDCCIF_BOOTTRC_DATA)
192#define BOOTTRC_CCIF0_NEW_VPE0_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*1)
193#define BOOTTRC_CCIF0_NEW_VPE1_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*2)
194#define BOOTTRC_CCIF0_NEW_VPE2_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*3)
195#define BOOTTRC_CCIF0_NEW_VPE3_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*4)
196#define BOOTTRC_CCIF0_NEW_VPE4_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*5)
197#define BOOTTRC_CCIF0_NEW_VPE5_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*6)
198#define BOOTTRC_CCIF0_NEW_VPE6_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*7)
199#define BOOTTRC_CCIF0_NEW_VPE7_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*8)
200#define BOOTTRC_CCIF0_NEW_VPE8_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*9)
201#define BOOTTRC_CCIF0_NEW_VPE9_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*10)
202#define BOOTTRC_CCIF0_NEW_VPE10_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*11)
203#define BOOTTRC_CCIF0_NEW_VPE11_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*12)
204#endif
205#else //__MD97__
206#define BOOTTRC_CCIF0_NEW_MAGIC_ADDR (MDCCIF_BOOTTRC_DATA)
207#define BOOTTRC_CCIF0_NEW_VPE0_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*1)
208#define BOOTTRC_CCIF0_NEW_VPE1_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*3)
209#define BOOTTRC_CCIF0_NEW_VPE2_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*5)
210#define BOOTTRC_CCIF0_NEW_VPE3_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*7)
211#define BOOTTRC_CCIF0_NEW_VPE4_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*9)
212#define BOOTTRC_CCIF0_NEW_VPE5_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*11)
213
214#define BOOTTRC_CCIF0_OLD_MAGIC_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*9)
215#define BOOTTRC_CCIF0_OLD_VPE0_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*10)
216#define BOOTTRC_CCIF0_OLD_VPE1_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*11)
217#define BOOTTRC_CCIF0_OLD_VPE2_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*12)
218#define BOOTTRC_CCIF0_OLD_VPE3_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*13)
219#define BOOTTRC_CCIF0_OLD_VPE4_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*14)
220#define BOOTTRC_CCIF0_OLD_VPE5_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*15)
221#endif
222#if defined(__PROFILE_INIT__)
223#define PROFILE_INIT_ENTRY_COUNT 128
224#define PROFILE_INIT_VPE_SIZE (PROFILE_INIT_ENTRY_COUNT * 0x8)
225#endif
226
227#endif /* !_BOOT_COMM_H */
228