| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2001 |
| 8 | * |
| 9 | *****************************************************************************/ |
| 10 | |
| 11 | /***************************************************************************** |
| 12 | * |
| 13 | * Filename: |
| 14 | * --------- |
| 15 | * cache_sw.h |
| 16 | * |
| 17 | * Project: |
| 18 | * -------- |
| 19 | * Maui_Software |
| 20 | * |
| 21 | * Description: |
| 22 | * ------------ |
| 23 | * This Module defines the functionality of code and data cache. |
| 24 | * |
| 25 | * Author: |
| 26 | * ------- |
| 27 | * ------- |
| 28 | * |
| 29 | *============================================================================ |
| 30 | * HISTORY |
| 31 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 32 | *------------------------------------------------------------------------------ |
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| 454 | *------------------------------------------------------------------------------ |
| 455 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 456 | *============================================================================ |
| 457 | ****************************************************************************/ |
| 458 | |
| 459 | #ifndef _CACHE_SW_H |
| 460 | #define _CACHE_SW_H |
| 461 | |
| 462 | #include "kal_general_types.h" |
| 463 | |
| 464 | |
| 465 | #define L2_Only_Sync() do {\ |
| 466 | register kal_uint32 __tmp__;\ |
| 467 | __asm__ volatile (\ |
| 468 | "li %0, 0x1\n"\ |
| 469 | "sw %0, 0(%1)\n"\ |
| 470 | :"=&r"(__tmp__)\ |
| 471 | :"r"(l2_sync_base):\ |
| 472 | );\ |
| 473 | } while (0) |
| 474 | |
| 475 | /******************************************************************************* |
| 476 | * constants & macros |
| 477 | *******************************************************************************/ |
| 478 | |
| 479 | /* cacheable and non-cacheable */ |
| 480 | #if defined(__DYNAMIC_SWITCH_CACHEABILITY__) |
| 481 | enum |
| 482 | { |
| 483 | DYNAMIC_SWITCH_CACHEABILITY_NON_CACHEABLE = 0x0, |
| 484 | DYNAMIC_SWITCH_CACHEABILITY_CACHEABLE = 0x1 |
| 485 | }; |
| 486 | #endif |
| 487 | |
| 488 | #define CPU_CACHE_LINE_SIZE 32 |
| 489 | #define CPU_L2CACHE_LINE_SIZE 64 |
| 490 | #define CPU_CACHE_LINE_BIT_OFFSET 5 |
| 491 | #define CPU_CACHE_LINE_SIZE_MASK 0x0000001F |
| 492 | #define L2CACHE_LINE_SIZE_MASK 0x0000003F |
| 493 | |
| 494 | #define CPU_CACHE_LINE_ALIGN_ADDR(_addr) \ |
| 495 | ((_addr) & ~CPU_CACHE_LINE_SIZE_MASK) |
| 496 | #define CPU_CACHE_LINE_ALIGN_LEN(_addr, _len) \ |
| 497 | ((CPU_CACHE_LINE_ALIGN_ADDR((_addr) + (_len) -1) - CPU_CACHE_LINE_ALIGN_ADDR((_addr))) + CPU_CACHE_LINE_SIZE) |
| 498 | |
| 499 | #define IS_CACHE_LINE_SIZE_ALIGNED(value) ((value&CPU_CACHE_LINE_SIZE_MASK)==0? 1: 0) |
| 500 | |
| 501 | #define L2CACHE_LINE_ALIGN_ADDR(_addr) \ |
| 502 | ((_addr) & ~L2CACHE_LINE_SIZE_MASK) |
| 503 | #define L2CACHE_LINE_ALIGN_LEN(_addr, _len) \ |
| 504 | ((L2CACHE_LINE_ALIGN_ADDR((_addr) + (_len) -1) - L2CACHE_LINE_ALIGN_ADDR((_addr))) + CPU_L2CACHE_LINE_SIZE) |
| 505 | |
| 506 | #define IS_L2CACHE_LINE_SIZE_ALIGNED(value) ((value&L2CACHE_LINE_SIZE_MASK)==0? 1: 0) |
| 507 | |
| 508 | /******************************************************************************* |
| 509 | * function prototypes |
| 510 | *******************************************************************************/ |
| 511 | |
| 512 | #if defined(__ARM9_MMU__) || defined(__ARM11_MMU__) || defined(__MTK_MMU__) || defined(__CR4__) || defined(__MIPS_IA__) || defined(__MIPS_I7200__) |
| 513 | |
| 514 | kal_uint32 is_predef_dyna_c_region(kal_uint32 vaddr, kal_uint32 len); |
| 515 | kal_uint32 dynamic_switch_cacheable_region(void *vaddr, kal_uint32 len, kal_uint32 cacheable); |
| 516 | kal_uint32 dynamic_switch_cacheable_region_nonblocking(void *vaddr, kal_uint32 len, kal_uint32 cacheable); |
| 517 | |
| 518 | #endif /* __ARM9_MMU__ || __ARM11_MMU__ || __MTK_MMU__ || __CR4__ || __MIPS_IA__ || __MIPS_I7200__*/ |
| 519 | |
| 520 | kal_int32 query_is_dram(kal_uint32 addr, kal_uint32 len); |
| 521 | #define INT_QueryIsDRAM(addr, len) \ |
| 522 | query_is_dram((kal_uint32)addr, (kal_uint32)len) |
| 523 | |
| 524 | kal_int32 query_is_noncached_ram(kal_uint32 addr, kal_uint32 len); |
| 525 | #define INT_QueryIsNonCachedRAM(addr, len) \ |
| 526 | query_is_noncached_ram((kal_uint32)addr, (kal_uint32)len) |
| 527 | |
| 528 | kal_int32 query_is_cached_ram(kal_uint32 addr, kal_uint32 len); |
| 529 | #define INT_QueryIsCachedRAM(addr, len) \ |
| 530 | query_is_cached_ram((kal_uint32)addr, (kal_uint32)len) |
| 531 | |
| 532 | #if defined(__DYNAMIC_SWITCH_CACHEABILITY__) || defined(__WRITE_THROUGH_CACHEABLE__) |
| 533 | kal_int32 invalidate_dcache(kal_uint32 addr, kal_uint32 len) DECLARE_MIPS16; |
| 534 | kal_int32 invalidate_dcache_L2WB(kal_uint32 addr, kal_uint32 len) DECLARE_MIPS16; |
| 535 | // kal_int32 invalidate_icache(kal_uint32 addr, kal_uint32 len); // Not released to user due to HRT concern about L2$ lock. |
| 536 | kal_int32 invalidate_dcache_nonblocking(kal_uint32 addr, kal_uint32 len); |
| 537 | // kal_int32 invalidate_icache_nonblocking(kal_uint32 addr, kal_uint32 len); // Not released to user due to HRT concern about L2$ lock. |
| 538 | |
| 539 | #endif /* __DYNAMIC_SWITCH_CACHEABILITY__ || __WRITE_THROUGH_CACHEABLE__ */ |
| 540 | |
| 541 | #if defined(__DYNAMIC_SWITCH_CACHEABILITY__) |
| 542 | /******************************************************************************* |
| 543 | * <GROUP Functions> |
| 544 | * |
| 545 | * FUNCTION |
| 546 | * clean_dcache |
| 547 | * DESCRIPTION |
| 548 | * This function is used to clean cache |
| 549 | * PARAMETERS |
| 550 | * addr: [IN] the start address. it must be cache line size aligned (usually 32byte) |
| 551 | * len: [IN] the length. it must be the multiple of cache line size |
| 552 | * RETURNS |
| 553 | * always return 0 |
| 554 | ******************************************************************************/ |
| 555 | kal_int32 clean_dcache(kal_uint32 addr, kal_uint32 len) DECLARE_MIPS16; |
| 556 | kal_int32 clean_dcache_L2WB(kal_uint32 addr, kal_uint32 len); |
| 557 | kal_int32 clean_dcache_nonblocking(kal_uint32 addr, kal_uint32 len); |
| 558 | /******************************************************************************* |
| 559 | * <GROUP Functions> |
| 560 | * |
| 561 | * FUNCTION |
| 562 | * clean_and_invalidate_dcache |
| 563 | * DESCRIPTION |
| 564 | * This function is used to clean and invalidate cache. |
| 565 | * PARAMETERS |
| 566 | * addr: [IN] the start address. it must be cache line size aligned (usually 32byte) |
| 567 | * len: [IN] the length. it must be the multiple of cache line size |
| 568 | * RETURNS |
| 569 | * always return 0 |
| 570 | ******************************************************************************/ |
| 571 | kal_int32 clean_and_invalidate_dcache(kal_uint32 addr, kal_uint32 len) DECLARE_MIPS16; |
| 572 | kal_int32 clean_and_invalidate_dcache_L2WB(kal_uint32 addr, kal_uint32 len); |
| 573 | kal_int32 clean_and_invalidate_dcache_nonblocking(kal_uint32 addr, kal_uint32 len); |
| 574 | #ifdef __DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__ |
| 575 | kal_int32 clean_and_invalidate_dcache_unlockL2(kal_uint32 addr, kal_uint32 len) DECLARE_MIPS16; |
| 576 | #endif |
| 577 | kal_uint32 virt_to_phys(void * address); |
| 578 | kal_uint32 phys_to_virt(void * address); |
| 579 | kal_uint32 remap_to_physRam(void * address); |
| 580 | #endif /* __DYNAMIC_SWITCH_CACHEABILITY__ */ |
| 581 | |
| 582 | kal_int32 lock_l2cache(kal_uint32 addr, kal_uint32 len); |
| 583 | kal_int32 invalidate_l2cache(kal_uint32 addr, kal_uint32 len); |
| 584 | #ifdef __DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__ |
| 585 | kal_int32 invalidate_l2cache_unlockL2(kal_uint32 addr, kal_uint32 len); |
| 586 | #endif |
| 587 | #endif /* _CACHE_SW_H */ |