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192.168.1.100 / T800_MD / 1eb8f53f94c145708b5ea2c6b9b96ea3d613f607 / . / mcu / driver / audio / src / v1 / sp_3g.c
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*******************************************************************************
37 *
38 * Filename:
39 * ---------
40 * sp_3g.c
41 *
42 * Project:
43 * --------
44 * Maui
45 *
46 * Description:
47 * ------------
48 * 3G speech interface
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *------------------------------------------------------------------------------
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478
479//#define TK6291_FAKE_COMPILE
480
481
482#include "kal_public_api.h"
483#include "kal_general_types.h"
484#include "sync_data.h"
485//#include "string.h"
486#include "kal_trace.h"
487#include "reg_base.h"
488//MPD
489//#include "l4_ps_api.h"
490#include "ps_em_exported_enum.h"
491//#include "l4_ps_api_public.h"
492extern ps_conf_test_mode_enum query_ps_conf_test_mode(void);
493
494//#include "speech_def.h"
495#include "audio_dsp_d2c_def.h"
496#include "l1aud_common_def.h"
497#include "l1audio.h"
498//#ifndef TK6291_FAKE_COMPILE
499//#include "uas_export_api.h"
500#include "csr_export_api.h"
501//#endif //#ifndef TK6291_FAKE_COMPILE
502#include "am.h"
503#include "l1audio_trace_utmd.h"
504#include "media.h"
505#include "l1sp_trc.h"
506#include "amr_table.h"
507
508#include "sal_exp.h"
509#include "sal_def.h"
510
511#include "sp_enhance.h"
512#include "sp_cc.h"
513
514#if defined(__VOLTE_SUPPORT__)
515#include "sp_ps.h"
516#endif
517#ifdef __VIDEO_CALL_SUPPORT__
518extern void vt_SP3G_Callback( kal_uint8 event, void *data );
519#endif
520
521extern const kal_uint16* tblAMR_WBOrder[9];
522
523#define __DLDCH_DELAY_IMPROVE__
524#if defined(__DLDCH_DELAY_IMPROVE__)
525#define __SP3G_UL_DSP_RESYNC_CSR__
526#define __SP3G_DIRECT_TO_DSP__
527#define ust_get_duration_true(prev, cur) (((cur) >= (prev))? (((cur) - (prev))): ((USCNT_WRAP - (prev) + (cur))))
528#endif
529
530#if defined(__SP3G_UL_DSP_RESYNC_CSR__)
531#include "us_timer.h"
532
533
534
535#define MINIMUM_DELAY_READ_THRESHOLD 14
536#endif
537
538extern kal_enhmutexid sp_handover_mutex;//sp_4g.c
539
540
541#if defined( __UMTS_RAT__ )
542
543#define _EXTRA_LOG_FOR_BIT_TRUE_
544#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
545kal_bool CS_NeedSpeechExtraLog( void );
546kal_bool g_bNeedExtraLog;
547#endif
548
549extern void L1SP_3G_Request(void);
550kal_uint32 SP4G_GetCodecMode(void);
551
552
553
554#define AMR_SID_FRAME 8
555#define AMR_NO_DATA 15
556
557#define AWB_SID_FRAME 9
558#define WB_AMR_SID_FRAME 25
559#define UL_HARD_REAL_TIME_DEMAND
560
561#define UL_MAX_DATA_SIZE 62 // frame_type, UL : len / DL : FQI_flag , DATA(23.85=>60)
562#define DL_MAX_DATA_SIZE 66 // frame_type, UL : len / DL : FQI_flag , CFN(4 bytes), DATA(23.85=>60)
563#define MAX_DSP_FRAME_LEN 30
564
565
566#define MAXIMUM_UL_DELAY 15 // CSR define for debug
567#define START_SHRINK_UL_DELAY 10 // L1Audio shrink UL delay from 40ms to 20ms
568
569
570#define HARD_REAL_TIME_UL_BUFFER_NUM 1 // could not revise
571#define RAT_3G_UL_BUFFER_NUM 2 // could not revise
572#if defined(__SP3G_UL_DSP_RESYNC_CSR__)
573 #define RAT_3G_DL_BUFFER_NUM 1 // do not suggest to revise
574 #define RAT_3G_DL_BUFFER_NUM_BEFORE_RESYNC 2 // do not suggest to revise
575#else
576 #define RAT_3G_DL_BUFFER_NUM 2 // do not suggest to revise
577 #define RAT_3G_DL_BUFFER_NUM_BEFORE_RESYNC 2 // do not suggest to revise
578#endif
579
580#ifdef __VIDEO_CALL_SUPPORT__
581 #define MAX_3G_UL_BUFFER_NUM 5
582 #define MAX_3G_DL_BUFFER_NUM 20
583#elif defined(__CSHSPA_SUPPORT__)
584 #define MAX_3G_UL_BUFFER_NUM 2
585 //In theory, Max CS delay is 200ms at most, which is 10 frames
586 #define MAX_3G_DL_BUFFER_NUM 10
587#else
588 #define MAX_3G_UL_BUFFER_NUM RAT_3G_UL_BUFFER_NUM
589 #define MAX_3G_DL_BUFFER_NUM RAT_3G_DL_BUFFER_NUM_BEFORE_RESYNC
590#endif
591
592#define __SP3G_DL_BUFFER_BEFORE_PLAY__
593/* Enable more buffering before put frame to DSP to keep start of speech smooth.
594 If not defined this compile option, it can reduce delay but maybe can't cover the initial discontinous.
595*/
596
597// here should be careful for this will limit MAX_DL_BUFFER_NUM to 1 << DL_BUF_INDEX_BIT_NUM
598// and MAX_UL_BUFFER_NUM to 1 << UL_BUF_INDEX_BIT_NUM
599#define DL_BUF_INDEX_BIT_NUM 5
600#define UL_BUF_INDEX_BIT_NUM (8 - DL_BUF_INDEX_BIT_NUM)
601
602#define SP3G324M_DL_EXTRA_LEN 5//frameType(1), len(1), l1_frame : recieve(3)
603#define SP3G_DL_EXTRA_LEN 6//frameType(1), FQI_flag(1), CFN(4)(unit:byte)
604
605//AMRWB 23.85 classB 405 bits=>51 bytes
606#define MAX_BYTES_IN_SINGLE_SUBFLOW ((405 + 7)>>3)
607#define _IGNORE_TYPE_ERROR_ // for 3G324M since the CRC is weaker, it's possible wrong pattern.
608 // so ignore it instead of assert.
609
610typedef struct
611{
612 uint16 dsp_buffer[MAX_DSP_FRAME_LEN];
613 uint16 dsp_buffer_dl[MAX_DSP_FRAME_LEN];
614 uint8 dl_buffer[MAX_3G_DL_BUFFER_NUM][DL_MAX_DATA_SIZE];
615#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
616 uint8 dl_buffer2[MAX_3G_DL_BUFFER_NUM][DL_MAX_DATA_SIZE];
617#endif
618 /*0: CFN, 1:RSSI|RSCP|ECIO|HHO_SHO ,2:crc_result ,3:s_value[0], 4:tpc_SIR_lta, 5:dpdch_SIR_lta, 6:TFCI_max_corr */
619 uint32 L1_Info[4][7];
620#if defined(__SP3G_UL_DSP_RESYNC_CSR__)
621 uint32 int_time[5];//0: UL, 1: DL, 2: temp UL, 3: DSP UL time, 4: send DSP resync time
622 bool ul_request_resync;
623 uint8 uDelW;
624#endif
625 uint8 ul_buffer[MAX_3G_UL_BUFFER_NUM][UL_MAX_DATA_SIZE]; // prevent sp3g_hisr , CSR race condition
626 uint8 ul_write_idx;
627 uint8 ul_read_idx;
628 uint8 ul_count;
629 bool is_getting_ul_data;
630 uint8 ul_delay;
631 uint8 dl_count;
632 uint8 dl_write_idx;
633 uint8 dl_read_idx;
634 bool under_interact;
635 uint8 ul_codec_mode;
636 uint8 ul_report;
637 uint8 dl_report;
638 uint8 pre_ul_report;
639 uint8 pre_dl_report;
640 bool waiting; // 1-message-1-get policy
641 bool ul_refresh; // detect change codec_mode
642 uint8 l1_info_idx;
643 uint8 sp3g_mode;
644 uint8 ul_buffer_size;
645 uint8 dl_buffer_size;
646 uint8 dtx_state; //enter dtx mode
647 uint8 dtx_force; //occured that force AMR frame
648#if defined(__CSHSPA_SUPPORT__)
649 uint8 dl_subflow[MAX_BYTES_IN_SINGLE_SUBFLOW];
650#endif
651}SP3G_Struct;
652
653static SP3G_Struct sp3gInfo;
654SP3G_Struct *sp3g;
655kal_spinlockid sp3g_spinlockID;
656static kal_uint32 sp3g_rab_id;
657static kal_bool sp3g_rab_state;
658static kal_bool sp3g_is_csr_ready;
659static kal_uint32 l1AInfo;
660
661static kal_uint8 sp3g_reset_flag; // speech on and InterRAT : set TRUE
662static kal_bool sp3g_dtx_mode;
663#if defined(__CSHSPA_SUPPORT__)
664static kal_uint8 sp3g_max_cs_delay;
665#endif
666
667
668#define INIT_3G_CODEC (0xA) //// 4.75 NB AMR
669
670const uint16 RAB_subflow[][4] = {
671 {42, 53, 0, 13}, // 4.75
672 {49, 54, 0, 14}, // 5.15
673 {55, 63, 0, 15}, // 5.9
674 {58, 76, 0, 18}, // 6.7
675 {61, 87, 0, 19}, // 7.4
676 {75, 84, 0, 21}, // 7.95
677 {65, 99, 40, 27}, // 10.2
678 {81, 103,60, 32}, // 12.2
679 {39, 0, 0, 5}, // SID
680 {39, 0, 0, 5}, // dummy
681 {39, 0, 0, 5}, // dummy
682 {39, 0, 0, 5}, // dummy
683 {39, 0, 0, 5}, // dummy
684 {39, 0, 0, 5}, // dummy
685 {39, 0, 0, 5}, // For Future use
686 {8, 0, 0, 0}, // AMR NoData
687
688/* TS26.201, Table 7 */
689 {54, 78, 0, 17},/* WB type 0, AMR-WB 6.60 */
690 {64, 113, 0, 23},/* WB type 1, AMR-WB 8.85 */
691 {72, 181, 0, 32},/* WB type 2, AMR-WB 12.65 */
692 {72, 213, 0, 36},/* WB type 3, AMR-WB 14.25 */
693 {72, 245, 0, 40},/* WB type 4, AMR-WB 15.85 */
694 {72, 293, 0, 46},/* WB type 5, AMR-WB 18.25 */
695 {72, 325, 0, 50},/* WB type 6, AMR-WB 19.85 */
696 {72, 389, 0, 58},/* WB type 7, AMR-WB 23.05 */
697 {72, 405, 0, 60},/* WB type 8, AMR-WB 23.85 */
698 {40, 0, 0, 5}/* WB type 9, AMR-WB SID */
699/* WB type 10-13, Not Used */
700
701};
702
703const uint8 RAB_Order[8] = {
704 0x80,0x40,0x20,0x10,0x08,0x04,0x02,0x01 /* bits order of AMR frame */
705};
706
707const uint16 DSP_Order[16] = {
708 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080, /* bits order of SHERIF */
709 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000
710};
711#ifdef __VIDEO_CALL_SUPPORT__
712const uint8 AMR_IF2_Order[8] = {
713 0x10,0x20,0x40,0x80,0x01,0x02,0x04,0x08 /* bits order of AMR IF2 frame */
714};
715
716const uint8 AMR_IF2_FRAME_LENGTH[16] = {/* byte length of AMR IF2 frame */
717 13, 14, 16, 18, 19, 21, 26, 31, 6,
718 0 , 0, 0, 0, 0, 0, 1
719};
720#endif
721
722const uint8 AmrFrameType2DspMode[25] = {0x0A, 0x09, 0x08, 0x07, 0x06,
723 0x05, 0x04, 0x03, 0x00, 0x00,
724 0x00, 0x00, 0x00, 0x00, 0x00,
725 0x00, 0x20, 0x21, 0x22, 0x23,
726 0x24, 0x25, 0x26, 0x27, 0x28};
727
728 //** From {0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x00};
729 //** mapping to
730const uint8 NB_DspMode2AmrFrameType[17] = {0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00};
731
732 //** From {0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28};
733 //** mapping to
734const uint8 WB_DspMode2AmrFrameType[17] = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18};
735
736 //** From {0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x00};
737 //** mapping to
738const uint8 NB_DspModeLen[17] = {0x10, 0x0D, 0x0A, 0x0A, 0x09, 0x08, 0x07, 0x06};
739
740 //** From {0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28};
741 //** mapping to
742const uint8 WB_DspModeLen[17] = {0x09, 0x0C, 0x10, 0x12, 0x14, 0x17, 0x19, 0x1D, 0x1E};
743
744
745#define GetFrameType2DspMode(ftype) (AmrFrameType2DspMode[(ftype)])
746#define GetDspMode2FrameType(mode) (((0x20 <= (mode)) && ((mode) <= 0x28)) ? (WB_DspMode2AmrFrameType[(mode)-0x20]) : \
747 (((0x03 <= (mode)) && ((mode) <= 0x0A)) ? (NB_DspMode2AmrFrameType[(mode)-0x03]) : (-1)))
748
749#define GetDspModeLen(mode) (((0x20 <= (mode)) && ((mode) <= 0x28)) ? (WB_DspModeLen[(mode)-0x20]) : \
750 (((0x03 <= (mode)) && ((mode) <= 0x0A)) ? (NB_DspModeLen[(mode)-0x03]) : (0x00)))
751
752#define GetRab2DspMapping(ftype) (((0x10 <= (ftype)) && ((ftype) <= 0x18)) ? (tblAMR_WBOrder[(ftype) - 0x10]) : \
753 (((0x00 <= (ftype)) && ((ftype) <= 0x07)) ? (tblAMROrder[(ftype)-0x00]) : (0)))
754
755
756
757extern const uint8* tblAMROrder[8];
758
759#define AMR_DATA_LOG
760#ifdef __FAKE_3G_LOOPBACK__
761void fake_CSR_Speech_Callback(SP3G_Event event, void *data){}
762#endif
763
764#if defined(__L1_STANDALONE__)
765void CSR_SP3G_Callback( SP3G_Event event, void *data){}
766void CSR_SP4G_Callback( SP4G_Event event, void *data ){}
767#else
768fp_CSR_SP3G_Callback CSR_SP3G_Callback;
769extern void CSR_SP4G_Callback( SP4G_Event event, void *data );
770#endif
771
772extern uint32 L1I_GetTimeStamp( void );
773
774#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
775kal_bool CS_NeedSpeechExtraLog( void )
776{
777 return g_bNeedExtraLog;
778}
779#endif
780
781extern void sp3g_vmRecordService( uint32 *l1_info, uint16 crc_result, uint16 buf_status, uint16 *ul_frame_data, uint16* dl_frame_data, kal_bool bBufferOK);
782
783/* SP3G_UpdateL1InFo */
784/* called by L1A to update DCH on/off and TX in/off(DCH UL on/off) */
785/* bit 0: DCH on/off (1: on, 0: off) */
786/* bit 1: DCH UL on/off (1: on, 0: off) */
787/* bit 2: indicate RLF status (1: indicate RLF, 0: reset RLF) */
788/* bit 3: 3 bits to indicate DCH setup type */
789
790void SP3G_UpdateL1AInFo_P( kal_uint8 bitmap, kal_uint8 value )
791{
792 ASSERT( bitmap <= 3 );
793 MD_TRC_SP3G_L1A_UPDATE_INFO(bitmap, value);
794
795 kal_take_enh_mutex( sp_handover_mutex );
796
797 if( bitmap == 3 ){
798 l1AInfo |= (value << 3);
799 } else {
800 if( value > 0 )
801 l1AInfo |= (1 << bitmap);
802 else
803 l1AInfo &= ~(1 << bitmap);
804 }
805 kal_give_enh_mutex( sp_handover_mutex );
806}
807
808
809extern kal_enhmutexid sp_mutex;
810//CSR inform RAB is established, the rab_id should be set as parameter when callback to CSR
811
812void CSR_Codec_Ready(int rab_id)
813{
814 if(!sp3g_is_csr_ready && NULL != CSR_SP3G_Callback){
815 MD_TRC_SP3G_CODEC_READY_OK(rab_id);
816 CSR_SP3G_Callback(SP3G_CODEC_READY, (void*)rab_id ); // It means that l1sp_speechon is not invoked and callback will be replied until l1sp_speechon is triggered.
817 sp3g_is_csr_ready = true;
818 }else{
819 MD_TRC_SP3G_CODEC_READY_SKIP(rab_id, sp3g_is_csr_ready, (NULL==CSR_SP3G_Callback));
820 }
821}
822
823void CSR_Codec_Close(int rab_id)
824{
825 if(sp3g_is_csr_ready && NULL != CSR_SP3G_Callback){
826 MD_TRC_SP3G_CODEC_CLOSE_OK(rab_id);
827 CSR_SP3G_Callback(SP3G_CODEC_CLOSED, (void*)rab_id );
828 sp3g_is_csr_ready = false;
829 }else{
830 MD_TRC_SP3G_CODEC_CLOSE_SKIP(rab_id, sp3g_is_csr_ready, (NULL==CSR_SP3G_Callback));
831 }
832}
833
834void SP3G_Rab_Est_sub()
835{
836 CSR_Codec_Ready(sp3g_rab_id);
837 SP3G_Reset();
838 AM_InterRAT_2G_to_3G(sp3g->ul_codec_mode);
839 L1SP_SetState( L1SP_STATE_3G_SPEECH_ON );
840}
841#ifdef __FAKE_3G_LOOPBACK__
842extern kal_uint32 get_is_fake_3g(void);
843#endif
844void SP3G_Rab_Est( uint32 rab_id, kal_uint8 default_speech_codec )
845{
846#ifdef __FAKE_3G_LOOPBACK__
847 if(get_is_fake_3g()){
848 uint32 codec;
849 kal_prompt_trace(MOD_L1SP, "[SP3G]SP3G_Rab_Est %d %d", rab_id, default_speech_codec);
850 codec = AmrFrameType2DspMode[default_speech_codec];
851 sp3g->ul_codec_mode = codec;
852 }
853#endif
854 sp3g_rab_id = rab_id;
855 sp3g_rab_state = KAL_TRUE;
856
857 //sp3g_codec_mode = default_speech_codec;
858 MD_TRC_SP3G_RAB_EST_0(L1SP_GetState());
859
860#if defined(_MODEM_RESYNC_3G_)
861 MD_TRC_L1Audio_Msg_AM_3G_Reset_Time_Drift();
862#if defined( __UMTS_RAT__ )
863 switch(L1SP_GetSIMStatus()){
864 case SP_3G_SIM_FDD_ACTIVE:
865#if defined(__UMTS_FDD_MODE__)
866 UL1D_Speech_Resync_Reset_Time_Offset();
867#endif
868 break;
869 case SP_3G_SIM_TDD_ACTIVE:
870#if defined( __UMTS_TDD128_MODE__ )
871 TL1C_Reset_Time_Drift();
872#endif
873 break;
874 default:
875 ASSERT(0);
876 }
877#endif
878#endif
879
880#if defined( __UMTS_RAT__ ) && !defined(__L1_STANDALONE__)
881 switch(L1SP_GetSIMStatus()){
882 case SP_3G_SIM_FDD_ACTIVE:
883 if(query_ps_conf_test_mode()==PS_CONF_TEST_FTA)
884 SP3G_SetDTX(false);
885 else
886 SP3G_SetDTX(true);
887 break;
888 case SP_3G_SIM_TDD_ACTIVE:
889 break;
890 default:
891 ASSERT(0);
892 }
893#endif
894
895 kal_take_enh_mutex( sp_handover_mutex );
896 MD_TRC_SP3G_RAB_EST();
897
898 //CSR_SP3G_Callback(SP3G_CODEC_READY, (void*)sp3g_rab_id );
899 SAL_Set_LinkStatus(SAL_LINKSTATUS_3G , true);
900 CSR_Codec_Ready(sp3g_rab_id);
901#if defined(__C2K_SPEECH_SUPPORT__)
902 if( L1SP_GetState() == L1SP_STATE_C2K_SPEECH_ON ){//
903 //PSR_C2K_Callback(C2K_CODEC_READY, (void*)0 );
904 //C2k_Reset();
905 AM_InterRAT_C2K_to_3G(sp3g->ul_codec_mode);
906 L1SP_SetState( L1SP_STATE_3G_SPEECH_ON );
907 }else
908#endif
909#if defined(__VOLTE_SUPPORT__)
910 if( L1SP_GetState() == L1SP_STATE_4G_SPEECH_ON ){//
911 PSR_SP4G_Callback(SP4G_CODEC_CLOSED, (void*)0 );
912 SP3G_Reset();
913 AM_InterRAT_4G_to_3G(sp3g->ul_codec_mode);
914 L1SP_SetState( L1SP_STATE_3G_SPEECH_ON );
915 }else
916#endif
917 if( L1SP_GetState() == L1SP_STATE_2G_SPEECH_ON ){//prepare InterRAT HO
918 SP3G_Reset();
919 AM_InterRAT_2G_to_3G(sp3g->ul_codec_mode);
920 L1SP_SetState( L1SP_STATE_3G_SPEECH_ON );
921 }
922
923 kal_give_enh_mutex( sp_handover_mutex );
924}
925
926void SP3G_Rab_Deest( void )
927{
928 sp3g_rab_state = KAL_FALSE;
929 MD_TRC_SP3G_RAB_DEEST_0(L1SP_GetState());
930 kal_take_enh_mutex( sp_handover_mutex );
931
932 MD_TRC_SP3G_RAB_DEEST();
933
934 //CSR_SP3G_Callback(SP3G_CODEC_CLOSED, (void*)sp3g_rab_id );
935 SAL_Set_LinkStatus(SAL_LINKSTATUS_3G , false);
936 CSR_Codec_Close(sp3g_rab_id);
937#if defined(__C2K_SPEECH_SUPPORT__)
938 if( L1SP_isC2KSO_Connected() && L1SP_GetState() != L1SP_STATE_C2K_SPEECH_ON && L1SP_GetState() != L1SP_STATE_IDLE ){//3G->4G
939 //PSR_C2K_Callback(C2K_CODEC_READY, (void*)0 );
940 //C2k_Reset();
941 AM_InterRAT_3G_to_C2K(L1SP_GetC2KSO_Codec());
942 L1SP_SetState( L1SP_STATE_C2K_SPEECH_ON );
943 }else
944#endif
945#if defined(__VOLTE_SUPPORT__)
946 if( SP4G_Rab_State() && L1SP_GetState() != L1SP_STATE_4G_SPEECH_ON && L1SP_GetState() != L1SP_STATE_IDLE ){//3G->4G
947 PSR_SP4G_Callback(SP4G_CODEC_READY, (void*)0 );
948 SP4G_Reset();
949 AM_InterRAT_3G_to_4G(SP4G_GetCodecMode());
950 L1SP_SetState( L1SP_STATE_4G_SPEECH_ON );
951 }else
952#endif
953 if( L1SP_TCH_State() && L1SP_GetState() != L1SP_STATE_2G_SPEECH_ON && L1SP_GetState() != L1SP_STATE_IDLE ){//2G->3G fail case
954 AM_InterRAT_3G_to_2G();
955 L1SP_SetState( L1SP_STATE_2G_SPEECH_ON );
956 }
957 kal_give_enh_mutex( sp_handover_mutex );
958}
959
960kal_bool SP3G_Rab_State( void )
961{
962 return sp3g_rab_state;
963}
964
965kal_uint32 SP3G_Rab_Id( void )
966{
967 return sp3g_rab_id;
968}
969
970
971
972void SP3G_GetSyncDelayRW( kal_uint16 *u16DelayR, kal_uint16 *u16DelayW, kal_uint16 *u16DelayM, kal_uint32 *u32CurTime64us)
973{
974 kal_uint16 msDelayR, msDelayW;
975 kal_uint32 cur_time, delay, idx;
976 kal_uint32 MODE_3G;
977
978#if defined( __UMTS_RAT__ )
979 if(!SP3G_Rab_State()){
980 MODE_3G = SAL_DEALY_3G_FDD;
981 } else {
982 switch(L1SP_GetSIMStatus()){
983 case SP_3G_SIM_FDD_ACTIVE:
984#if defined(__UMTS_FDD_MODE__)
985 MODE_3G = SAL_DEALY_3G_FDD;
986#endif
987 break;
988 case SP_3G_SIM_TDD_ACTIVE:
989#if defined( __UMTS_TDD128_MODE__ )
990 MODE_3G = SAL_DEALY_3G_TDD;
991#endif
992 break;
993 default:
994 ASSERT(0);
995 }
996 }
997#endif
998
999 *u32CurTime64us = fma_get_glb_ts();
1000 cur_time = ust_get_current_time();
1001 sp3g->int_time[4] = cur_time;
1002
1003 MD_TRC_L1Audio_Msg_SP3G_GetSyncDelayRW( sp3g->ul_codec_mode );
1004
1005 if( sp3g_reset_flag == 2 ){
1006 idx = ( ( ust_us_duration( sp3g->int_time[0], sp3g->int_time[1] ) ) / 1000 ) % 20;
1007 SAL_Get_Delay(MODE_3G, 0, idx, u16DelayR, u16DelayW, u16DelayM);
1008 // ASSERT( 0==((*u16DelayR)&0x7) );
1009 // ASSERT( 0==((*u16DelayW)&0x7) );
1010 // ASSERT( 0==((*u16DelayM)&0x7) );
1011 msDelayR = (*u16DelayR)>>3;
1012 msDelayW = (*u16DelayW)>>3;
1013 MD_TRC_L1Audio_Msg_SP3G_SEND_RESYNC_INFO( idx, msDelayR, sp3g->int_time[0]/1000, sp3g->int_time[1]/1000, cur_time/1000);
1014 delay = ( ust_us_duration( sp3g->int_time[1], cur_time ) ) / 1000 ;
1015 if(delay >= msDelayR || delay >= msDelayW){ //error handling
1016 SAL_Get_Delay(MODE_3G, SAL_DELAY_NA, SAL_DELAY_NA, u16DelayR, u16DelayW, u16DelayM);
1017 // ASSERT( 0==((*u16DelayR)&0x7) );
1018 // ASSERT( 0==((*u16DelayW)&0x7) );
1019 // ASSERT( 0==((*u16DelayM)&0x7) );
1020 msDelayR = (*u16DelayR)>>3;
1021 msDelayW = (*u16DelayW)>>3;
1022 MD_TRC_L1Audio_Msg_SP3G_REYSNC_DELAY_OVERFLOW(msDelayR, msDelayW);
1023 sp3g->uDelW = msDelayW;
1024 } else {
1025 *u16DelayR = (msDelayR - delay) * 8;//samples
1026 sp3g->uDelW = (msDelayW - delay);
1027 *u16DelayW = sp3g->uDelW * 8;
1028 }
1029 } else {
1030 SAL_Get_Delay(MODE_3G, SAL_DELAY_NA, SAL_DELAY_NA, u16DelayR, u16DelayW, u16DelayM);
1031 // ASSERT( 0==((*u16DelayR)&0x7) );
1032 // ASSERT( 0==((*u16DelayW)&0x7) );
1033 // ASSERT( 0==((*u16DelayM)&0x7) );
1034 //msDelayR = (*u16DelayR)>>3;
1035 msDelayW = (*u16DelayW)>>3;
1036 sp3g->uDelW = msDelayW;
1037 }
1038}
1039void sp3g_hisr_ul(void *data)
1040{
1041 int32 I, J = 0, K;
1042 uint16 *ptr16;
1043 uint16 tx_type, sc_mode;
1044 uint8 *ptr8;
1045 uint8 len;
1046 const uint8* RAB_To_DSP_Mapping;
1047 uint16 total_bits, idx, rabBitsCount;
1048 uint8 frame_type = 0,bit8Data;
1049 bool bWrite;
1050
1051 kal_take_spinlock(sp3g_spinlockID, KAL_INFINITE_WAIT);
1052 if(L1SP_GetState() != L1SP_STATE_3G_SPEECH_ON){
1053 MD_TRC_SP3G_UL_HISR_SKIP(L1SP_GetState());
1054 kal_give_spinlock(sp3g_spinlockID);
1055 return;
1056 }
1057
1058 ASSERT(sp3g != (SP3G_Struct*) 0);
1059
1060 sp3g->ul_report = SAL_3G_GetValue(SAL_3G_VALUE_TX_CODEC_MODE);
1061
1062 /*for catcher log codec information*/
1063 if( sp3g->ul_report != sp3g->pre_ul_report ){
1064 MD_TRC_L1Audio_Msg_SPEECH_CODEC( L1SP_Speech_Codec_Mode(sp3g->ul_report), L1SP_Speech_Codec_Mode(sp3g->dl_report) );
1065 sp3g->pre_ul_report = sp3g->ul_report;
1066 }
1067#if defined(__SP3G_UL_DSP_RESYNC_CSR__)
1068 sp3g->int_time[3] = ust_get_current_time();
1069 MD_TRC_SP3G_D2M_UL_TIMING((sp3g->int_time[3])/1000);
1070#endif
1071
1072 // UL side
1073 ptr16 = (uint16*)sp3g->dsp_buffer;
1074 {
1075 // get data from DSP UL buffer
1076 volatile uint16 *addr;
1077 tx_type = SAL_3G_GetValue(SAL_3G_VALUE_TX_TYPE);
1078 sc_mode = sp3g->ul_report;
1079 if( sc_mode < 0x03 || sc_mode > 0x28 )
1080 {
1081 MD_TRC_SP3G_INVALID_UL_CODEC_MODE(sc_mode);
1082 tx_type = SAL_3G_TX_NO_DATA;
1083 sc_mode = 3;
1084 }
1085 addr = SAL_3G_GetAddr(SAL_3G_ADDR_TXHB);
1086 for(I = GetDspModeLen(sc_mode); --I >= 0 ; )
1087 *ptr16++ = *addr++;
1088 }
1089
1090 // do bit re-ordering
1091 ptr16 = (uint16*)sp3g->dsp_buffer;
1092#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1093 if (g_bNeedExtraLog == true){
1094 ptr16 = (uint16*)sp3g->dsp_buffer;
1095 //kal_prompt_trace(MOD_L1SPHISR,"SP3GHISR UL DSP len %d, %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x",
1096 // DspModeLen[sc_mode - 3], ptr16[0], ptr16[1], ptr16[2], ptr16[3], ptr16[4], ptr16[5], ptr16[6], ptr16[7],
1097 // ptr16[8], ptr16[9], ptr16[10], ptr16[11], ptr16[12], ptr16[13], ptr16[14], ptr16[15]);
1098 MD_TRC_SP3G_UL_BIT_TRUE_DSP_F8(
1099 GetDspModeLen(sc_mode), ptr16[0], ptr16[1], ptr16[2], ptr16[3], ptr16[4], ptr16[5], ptr16[6], ptr16[7]);
1100 MD_TRC_SP3G_UL_BIT_TRUE_DSP_N8(
1101 ptr16[8], ptr16[9], ptr16[10], ptr16[11], ptr16[12], ptr16[13], ptr16[14], ptr16[15]);
1102
1103 }
1104#endif
1105 ptr8 = (uint8*)sp3g->ul_buffer[sp3g->ul_write_idx];
1106
1107 bWrite = KAL_FALSE;
1108
1109 if(SAL_3G_IsULReady()){//DSP tell MCU the data of DSP is ready
1110 if( sp3g->ul_count < sp3g->ul_buffer_size ){
1111 bWrite = KAL_TRUE;
1112 }
1113 if( sp3g->ul_count == sp3g->ul_buffer_size ){
1114 if( sp3g->is_getting_ul_data ){
1115 bWrite = KAL_FALSE;
1116 }else{
1117 sp3g->ul_read_idx++; //drop oldest frame
1118 sp3g->ul_count--;
1119 bWrite = KAL_TRUE;
1120 if( sp3g->ul_read_idx == sp3g->ul_buffer_size )
1121 sp3g->ul_read_idx = 0;
1122 }
1123 }
1124 SAL_3G_SetULEmpty();
1125 }else{//DSP tell MCU the data of DSP is not ready
1126 sp3g->ul_report = sp3g->ul_codec_mode;
1127 sc_mode = sp3g->ul_report;
1128 AM_FillSilencePatternInBuffer( ptr16, sp3g->ul_report );
1129 tx_type = SAL_3G_TX_SPEECH_GOOD;
1130 bWrite = KAL_TRUE;
1131 MD_TRC_SP3G_UL_DSP_NOT_READY_WARNING_AND_FILL_SILENCE();
1132 }
1133
1134 if(sp3g->under_interact){
1135 MD_TRC_SP3G_SKIP_UL_REFRESH(sp3g->ul_report, sp3g->ul_codec_mode);
1136 kal_give_spinlock(sp3g_spinlockID);
1137 return;
1138 }
1139 if( bWrite ){
1140 frame_type = GetDspMode2FrameType(sc_mode);
1141 switch(tx_type)
1142 {
1143 case SAL_3G_TX_SPEECH_GOOD:
1144 if( sp3g->sp3g_mode == RAT_3G_MODE ){
1145 *ptr8++ = frame_type;
1146 len = RAB_subflow[frame_type][3];
1147 *ptr8++ = len;
1148
1149 if(frame_type >= 0x10) //AMR-WB
1150 RAB_To_DSP_Mapping = (const uint8 *)tblAMR_WBOrder[frame_type-0x10];
1151 else
1152 RAB_To_DSP_Mapping = tblAMROrder[frame_type];
1153
1154 // do bit reorder , move speech information bits to rab_byte_array
1155 total_bits = RAB_subflow[frame_type][0] + RAB_subflow[frame_type][1] + RAB_subflow[frame_type][2];
1156
1157 for(I = len; --I >= 0; *ptr8++ = 0);
1158
1159 for(idx = 0, ptr8 -= len, I = 0; I < 3; I ++){
1160 rabBitsCount = RAB_subflow[frame_type][I];
1161
1162 if( frame_type >= 16 ){
1163 const uint16* WB_RAB_To_DSP_Mapping;
1164 WB_RAB_To_DSP_Mapping = (const uint16*)RAB_To_DSP_Mapping;
1165 for(J = 0; J < rabBitsCount; J++)
1166 {
1167 K = WB_RAB_To_DSP_Mapping[idx++];
1168 bit8Data = (ptr16[K >> 4] & DSP_Order[K & 15])? RAB_Order[J & 0x7] : 0;
1169 ptr8[J >> 3] |= bit8Data;
1170 }
1171 } else {
1172 for(J = 0; J < rabBitsCount; J++)
1173 {
1174 K = RAB_To_DSP_Mapping[idx++];
1175 bit8Data = (ptr16[K >> 4] & DSP_Order[K & 15])? RAB_Order[J & 0x7] : 0;
1176 ptr8[J >> 3] |= bit8Data;
1177 }
1178 }
1179 ptr8 += (rabBitsCount + 7) >> 3;
1180 }
1181
1182 ASSERT(idx == total_bits);
1183 }
1184#ifdef __VIDEO_CALL_SUPPORT__
1185 else{
1186 len = AMR_IF2_FRAME_LENGTH[frame_type]; //frame length
1187 *ptr8++ = len;
1188 RAB_To_DSP_Mapping = tblAMROrder[frame_type];
1189 total_bits = RAB_subflow[frame_type][0] + RAB_subflow[frame_type][1] + RAB_subflow[frame_type][2];
1190
1191 for(I = len; --I >= 0 ; )
1192 *ptr8++ = 0;
1193 idx = 0;
1194 ptr8 -= len;
1195 // do bit reorder , first byte contains frame_type
1196 *ptr8 = frame_type;
1197 I = 4;
1198 for(J = 0; J < total_bits; J++,I++)
1199 {
1200 K = RAB_To_DSP_Mapping[idx++];
1201 bit8Data = (ptr16[K >> 4] & DSP_Order[K & 15])? AMR_IF2_Order[J & 0x7] : 0;
1202 ptr8[I >> 3] |= bit8Data;
1203 }
1204 }
1205#endif
1206#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1207 //kal_prompt_trace(MOD_L1SPHISR,"SP3G_HISR UL is TX_SPEECH_GOOD");
1208 MD_TRC_SP3G_TX_SPEECH_GOOD();
1209#endif
1210 break;
1211 case SAL_3G_TX_SID_FIRST:
1212 if( sp3g->sp3g_mode == RAT_3G_MODE ){
1213 if( sp3g->ul_report >= 0x20 )
1214 *ptr8++ = WB_AMR_SID_FRAME;//WB SID
1215 else
1216 *ptr8++ = AMR_SID_FRAME;
1217 *ptr8++ = 5;
1218 for(I = 4; --I >= 0; )
1219 *ptr8++ = 0;
1220
1221 if( sp3g->ul_report >= 0x20 )
1222 *ptr8 = (uint8)(sp3g->ul_report - 0x20);
1223 else
1224 *ptr8 = (uint8)(frame_type << 1);
1225 #ifdef AMR_DATA_LOG
1226 ptr8 -= 6;
1227 MD_TRC_SP3G_TX_SID_FIRST();
1228 #endif
1229 }
1230#ifdef __VIDEO_CALL_SUPPORT__
1231 else{//3G 324M
1232 *ptr8++ = 6;//frame length
1233 for(I = 5; --I >= 0; )
1234 *ptr8++ = 0;
1235 *ptr8 = (uint8)(frame_type);
1236 ptr8 -= 5;
1237 *ptr8 |= AMR_SID_FRAME;
1238 }
1239#endif
1240 break;
1241 case SAL_3G_TX_SID_UPDATE:
1242 if( sp3g->sp3g_mode == RAT_3G_MODE ){
1243 if( sp3g->ul_report >= 0x20 )
1244 *ptr8++ = WB_AMR_SID_FRAME;//WB SID
1245 else
1246 *ptr8++ = AMR_SID_FRAME;
1247 *ptr8++ = 5;
1248 // do bit reorder , move sid information bits to rab_byte_array
1249 for(I = 5; --I >= 0; )
1250 *ptr8++ = 0;
1251
1252 ptr8 -= 5;
1253 for(I = 0; I < 35; I ++)
1254 {
1255 bit8Data = (ptr16[I >> 4] & DSP_Order[I & 15])? RAB_Order[I & 0x7] : 0;
1256 ptr8[I >> 3] |= bit8Data;
1257 }
1258 frame_type = (frame_type >> 2) | ((frame_type & 0x1) << 2) | (frame_type & 0x2);
1259
1260 if( sp3g->ul_report >= 0x20 )
1261 ptr8[4] |= (uint8)(sp3g->ul_report - 0x20)|0x10;
1262 else
1263 ptr8[4] |= (uint8)(frame_type << 1)|0x10;
1264
1265 #ifdef AMR_DATA_LOG
1266 ptr8 -= 2;
1267 MD_TRC_SP3G_TX_SID_UPDATE();
1268 #endif
1269 }
1270#ifdef __VIDEO_CALL_SUPPORT__
1271 else{//3G 324M
1272 *ptr8++ = 6;//frame length
1273 for(I = 5; --I >= 0; )
1274 *ptr8++ = 0;
1275 *ptr8 = (uint8)(frame_type);
1276 ptr8 -= 5;
1277 *ptr8 |= AMR_SID_FRAME;
1278 J = 4;
1279 for(I = 0; I < 35; J++, I++)
1280 {
1281 bit8Data = (ptr16[I >> 4] & DSP_Order[I & 15])? AMR_IF2_Order[I & 0x7] : 0;
1282 ptr8[J >> 3] |= bit8Data;
1283 }
1284 ptr8[4] |= 0x80;
1285 }
1286#endif
1287 break;
1288 case SAL_3G_TX_NO_DATA:
1289 if( sp3g->sp3g_mode == RAT_3G_MODE ){
1290 *ptr8++ = AMR_NO_DATA;
1291 *ptr8++ = 0;
1292 }
1293#ifdef __VIDEO_CALL_SUPPORT__
1294 else{//3G324M
1295 *ptr8++ = 1;
1296 *ptr8++ = AMR_NO_DATA;
1297 }
1298#endif
1299#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1300 //kal_prompt_trace(MOD_L1SPHISR,"SP3G_HISR UL is NO DATA");
1301 MD_TRC_SP3G_UL_NO_DATA();
1302#endif
1303 break;
1304 default:
1305 ASSERT(false);
1306 break;
1307 }
1308#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1309 if (g_bNeedExtraLog == true){
1310 //kal_prompt_trace(MOD_L1SPHISR,"SP3G_HISR UL Type %d, Frm %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x",
1311 // tx_type, ptr8[0], ptr8[1],ptr8[2],ptr8[3],ptr8[4],
1312 // ptr8[5],ptr8[6],ptr8[7],ptr8[8],ptr8[9],ptr8[10],ptr8[11],ptr8[12],ptr8[13],ptr8[14],ptr8[15], ptr8[16],ptr8[17],ptr8[18],ptr8[19],ptr8[20]);
1313 uint8 *tmp_ = (uint8*)sp3g->ul_buffer[sp3g->ul_write_idx];
1314 MD_TRC_SP3G_DEBUG_UL_BUFF(sp3g->ul_write_idx);
1315 MD_TRC_SP3G_UL_BIT_TRUE_F8(
1316 1, tx_type, tmp_[0], tmp_[1],tmp_[2],tmp_[3],tmp_[4],tmp_[5],tmp_[6],tmp_[7]);
1317 MD_TRC_SP3G_UL_BIT_TRUE_N13(
1318 tmp_[8],tmp_[9],tmp_[10],tmp_[11],tmp_[12],tmp_[13],tmp_[14],tmp_[15],
1319 tmp_[16],tmp_[17],tmp_[18],tmp_[19],tmp_[20]);
1320 }
1321#endif
1322 }
1323
1324 if( sp3g->ul_refresh )
1325 {
1326 if((sp3g->ul_report <= 0x0A && sp3g->ul_codec_mode >= 0x20) || //WB, NB handover
1327 (sp3g->ul_report >= 0x20 && sp3g->ul_codec_mode <= 0xA)){
1328 ASSERT(0);
1329 }else if(sp3g->ul_report != sp3g->ul_codec_mode ){
1330 SAL_3G_Upd_Enc_Cod(sp3g->ul_codec_mode);
1331 }
1332 sp3g->ul_refresh = KAL_FALSE;
1333 }
1334
1335 if( bWrite ){
1336 sp3g->ul_write_idx++;
1337 if( sp3g->ul_write_idx == sp3g->ul_buffer_size )
1338 sp3g->ul_write_idx = 0;
1339 sp3g->ul_count++;
1340#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1341 if (g_bNeedExtraLog == true) {
1342 //kal_prompt_trace(MOD_L1SPHISR,"SP3GVT UL cnt=%d,r=%d,w=%d",sp3g->ul_count,sp3g->ul_read_idx,sp3g->ul_write_idx);
1343 MD_TRC_SP3G_UL_BUFFER(sp3g->ul_count,sp3g->ul_read_idx,sp3g->ul_write_idx);
1344 }
1345#endif
1346 if( sp3g->sp3g_mode == RAT_3G_MODE && sp3g->ul_delay > START_SHRINK_UL_DELAY && !sp3g->is_getting_ul_data){
1347 sp3g->ul_read_idx++;
1348 if( sp3g->ul_read_idx == sp3g->ul_buffer_size )
1349 sp3g->ul_read_idx = 0;
1350 if(sp3g->ul_count > 1)
1351 sp3g->ul_count--;
1352 }//when ul write updated, check ul_delay. keep newest one
1353 }
1354
1355 if( sp3g->waiting == KAL_FALSE )
1356 {
1357 sp3g->waiting = KAL_TRUE;
1358 if( sp3g->sp3g_mode == RAT_3G_MODE ){
1359 ASSERT( NULL != CSR_SP3G_Callback );
1360 CSR_SP3G_Callback( SP3G_UL_DATA_NOTIFY, (void*)0 );
1361 }
1362 }
1363 else
1364 {
1365 sp3g->ul_delay ++;
1366 if( sp3g->sp3g_mode == RAT_3G_MODE ){
1367 ASSERT( NULL != CSR_SP3G_Callback );
1368 CSR_SP3G_Callback(SP3G_UL_DATA_DEALY_TICK, (void *)(kal_uint32)sp3g->ul_delay);
1369 }
1370 MD_TRC_SP3G_UL_DELAY(sp3g->ul_delay);
1371#if 0
1372/* under construction !*/
1373#endif
1374 }
1375 kal_give_spinlock(sp3g_spinlockID);
1376#ifdef __FAKE_3G_LOOPBACK__
1377 if(get_is_fake_3g()){
1378 msg_send6(MOD_L1SP, MOD_MED, AUDIO_SAP, MSG_ID_AUDIO_M2M_SP3G_UL_EVENT, NULL, NULL);
1379 }
1380#endif
1381}
1382
1383void sp3g_updateL1DSync(void)
1384{
1385#if defined(_MODEM_RESYNC_3G_)
1386 int16 time_drift;
1387#if defined( __UMTS_RAT__ )
1388 if(!SP3G_Rab_State()){
1389 MD_TRC_SP3G_L1D_Resync_Skip();
1390 return;
1391 }
1392 switch(L1SP_GetSIMStatus()){
1393 case SP_3G_SIM_FDD_ACTIVE:
1394#if defined(__UMTS_FDD_MODE__)
1395 time_drift = UL1D_Speech_Resync_Get_Time_Offset(); //us
1396 MD_TRC_SP3G_L1D_Resync(1, time_drift);
1397 if(time_drift > 1000){
1398 MD_TRC_L1D_RESYNC_UPDATE(1);
1399 UL1D_Speech_Resync_Update_Time_Offset(true);
1400 SAL_8K_Resync(true, 8, true, 8);
1401 }else if(time_drift < -1000){
1402 MD_TRC_L1D_RESYNC_UPDATE(0);
1403 UL1D_Speech_Resync_Update_Time_Offset(false);
1404 SAL_8K_Resync(true, -8, true, -8);
1405 }
1406#endif
1407 break;
1408 case SP_3G_SIM_TDD_ACTIVE:
1409#if defined( __UMTS_TDD128_MODE__ )
1410 time_drift = TL1C_Get_Time_Drift(); //us
1411 MD_TRC_SP3G_L1D_Resync(2, time_drift);
1412 if(time_drift > 1000){
1413 MD_TRC_L1D_RESYNC_UPDATE(1);
1414 TL1C_Update_Time_Drift(true);
1415 SAL_8K_Resync(true, 8, true, 8);
1416 }else if(time_drift < -1000){
1417 MD_TRC_L1D_RESYNC_UPDATE(0);
1418 TL1C_Update_Time_Drift(false);
1419 SAL_8K_Resync(true, -8, true, -8);
1420 }
1421#endif
1422 break;
1423 default:
1424 ASSERT(0);
1425 }
1426#endif
1427#endif
1428}
1429
1430extern void vmSet3GNetworkInfo( uint32 *l1_info, uint16 crc_result, uint16 buf_status, uint8 dl_count );
1431void sp3g_hisr_dl(void *data)
1432{
1433 int32 I, J = 0, K;
1434 uint16 *ptr16;
1435 uint16 rx_type = 0, sd_mode = 0, rx_len = 0;
1436 uint8 *ptr8;
1437#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1438 uint8 *ptr8_bak;
1439#endif
1440 const uint8* RAB_To_DSP_Mapping, *Order = NULL;
1441 uint16 total_bits, idx, rabBitsCount;
1442 uint8 frame_type = 0;
1443 uint16 bit16Data;
1444 uint8 sidData;
1445 bool FQI_flag = false;
1446
1447#if defined(__SP3G_UL_DSP_RESYNC_CSR__)
1448 MD_TRC_SP3G_D2M_DL_TIMING((ust_get_current_time())/1000);
1449#endif
1450 if(L1SP_GetState() != L1SP_STATE_3G_SPEECH_ON)
1451 return;
1452 ASSERT(sp3g != (SP3G_Struct*) 0);
1453
1454 sp3g->dl_report = SAL_3G_GetValue(SAL_3G_VALUE_RX_CODEC_MODE);
1455
1456
1457 /*for catcher log codec information*/
1458 if( sp3g->dl_report != sp3g->pre_dl_report ){
1459 MD_TRC_L1Audio_Msg_SPEECH_CODEC( L1SP_Speech_Codec_Mode(sp3g->ul_report), L1SP_Speech_Codec_Mode(sp3g->dl_report) );
1460 sp3g->pre_dl_report = sp3g->dl_report;
1461 }
1462
1463
1464 {
1465 uint32 *l1_info = NULL;
1466 //uint16 crc_result = 0;
1467 uint16 buf_status, crc_result = 0;
1468
1469 if( sp3g->dl_count == 0 ){
1470 crc_result = (l1AInfo << 8);
1471 }
1472 else
1473 {
1474 uint32 CFN = 0;
1475 if( sp3g->sp3g_mode == RAT_3G324M_MODE ){
1476 l1_info = NULL;
1477 }
1478 else{
1479 ptr8 = (uint8*) sp3g->dl_buffer[sp3g->dl_read_idx];
1480 ptr8 += 2;
1481 CFN = ptr8[0] + (ptr8[1] << 8) + (ptr8[2] << 16) + (ptr8[3] << 24);
1482
1483 for(I = 0 ; I < 4 ; I ++)
1484 if( CFN == sp3g->L1_Info[I][0] )
1485 break;
1486 if( I == 4 ){
1487 crc_result = (l1AInfo << 8);
1488 l1_info = NULL;
1489 }else{
1490 l1_info = sp3g->L1_Info[I];
1491 crc_result = (uint16)(l1AInfo << 8) | (uint16)(sp3g->L1_Info[I][2] & 0xF); //[0:7]:CRC, [8:15]:l1AInfo
1492 }
1493 /*SID BAD False alarm work around, log in VM first*/
1494 {
1495 uint8 * ptrDL;
1496 ptrDL = (uint8*) sp3g->dl_buffer[sp3g->dl_read_idx];
1497 if( sp3g->dtx_state == 0 && ptrDL[0] == 8 /*AMR_SID*/ && ptrDL[1] == KAL_FALSE/*CRC fail*/)
1498 crc_result |= 0x8000;// The flag indicate working around
1499 if( ptrDL[0] == AMR_NO_DATA && sp3g->dtx_force == KAL_TRUE )
1500 //crc_result |= 0x4000;
1501 crc_result |= 0x0080;//move from bit14 to bit7. 20100821
1502 }
1503 }
1504 }
1505 buf_status = ( ( (sp3g->ul_read_idx << DL_BUF_INDEX_BIT_NUM) + sp3g->dl_read_idx ) << 8 ) +
1506 (sp3g->ul_write_idx << DL_BUF_INDEX_BIT_NUM) + sp3g->dl_write_idx;
1507 vmSet3GNetworkInfo(l1_info, crc_result, buf_status, sp3g->dl_count);
1508
1509 }
1510
1511 l1AInfo &= ~0xFFFC;
1512 // DL side
1513 if( sp3g->dl_count == 0 || sp3g_reset_flag != 2 ){ // buffer under flow
1514 SAL_3G_Set_RxType(SAL_3G_RX_NO_DATA);
1515 rx_type = SAL_3G_RX_NO_DATA;
1516 sp3g->dtx_state = 1;
1517 MD_TRC_SP3G_DTX_NO_DATA();
1518 }
1519 else
1520 {
1521 MD_TRC_SP3G_BUFFER_STATUS(sp3g->dl_read_idx, sp3g->dl_write_idx,sp3g->dl_count, sp3g->dl_buffer[sp3g->dl_read_idx][0]);
1522
1523 ptr8 = (uint8*) sp3g->dl_buffer[sp3g->dl_read_idx];
1524#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1525 ptr8_bak = (uint8*) sp3g->dl_buffer2[sp3g->dl_read_idx];
1526#endif
1527 ptr16 = (uint16*) sp3g->dsp_buffer_dl;
1528 if( sp3g->sp3g_mode == RAT_3G_MODE ){
1529 frame_type = *ptr8++; // here 0 ~ 7 and includes SID and NO_DATA
1530 FQI_flag = (bool)*ptr8++;
1531 ptr8 += 4; // skip CFN
1532#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1533 ptr8_bak += 6;
1534#endif
1535 }
1536#ifdef __VIDEO_CALL_SUPPORT__
1537 else{//3G 324M
1538 FQI_flag = KAL_TRUE;
1539 frame_type = *ptr8++; // here 0 ~ 7 and includes SID and NO_DATA
1540 ptr8++; // skip frame length
1541 }
1542#endif
1543#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1544 if (g_bNeedExtraLog == true){
1545 //kal_prompt_trace(MOD_L1SPHISR,"SP3G_HISR DL Type %d, Frm %x %x %x %x %x", frame_type, ptr8[0], ptr8[1],ptr8[2],ptr8[3],ptr8[4]);
1546 MD_TRC_SP3G_DL_BIT_TRUE(frame_type, ptr8[0], ptr8[1],ptr8[2],ptr8[3],ptr8[4]);
1547 }
1548#endif
1549 if( frame_type == AMR_NO_DATA && sp3g->dtx_force == KAL_TRUE ){
1550 frame_type = AMR_SID_FRAME;
1551 FQI_flag = KAL_FALSE; // force enter SID_BAD;
1552 sp3g->dtx_state = 1;
1553 }
1554 sp3g->dtx_force = KAL_FALSE;
1555 if( sp3g->dtx_state == 0 && frame_type == AMR_SID_FRAME && FQI_flag == KAL_FALSE ){//previous dtx_state is false, but suddenly SID_BAD, regard it as false alarm.
1556 frame_type = AMR_NO_DATA;
1557 sp3g->dtx_force = KAL_TRUE;
1558 }
1559 if( data == (void *)2 )
1560 {
1561#if defined(__SP3G_DL_BUFFER_BEFORE_PLAY__)
1562 MD_TRC_SP3G_FORCE_NODATA_WHEN_RESYNC();
1563 frame_type = AMR_NO_DATA;
1564#endif
1565 }
1566 switch(frame_type)
1567 {
1568 case 0: // 4.75 kbps
1569 case 1: // 5.15 kbps
1570 case 2: // 5.9 kbps
1571 case 3: // 6.7 kbps
1572 case 4: // 7.4 kbps
1573 case 5: // 7.95 kbps
1574 case 6: // 10.2 kbps
1575 case 7: // 12.2 kbps
1576 case 16:/* WB type 0, AMR-WB 6.60 */
1577 case 17:/* WB type 1, AMR-WB 8.85 */
1578 case 18:/* WB type 2, AMR-WB 12.65 */
1579 case 19:/* WB type 3, AMR-WB 14.25 */
1580 case 20:/* WB type 4, AMR-WB 15.85 */
1581 case 21:/* WB type 5, AMR-WB 18.25 */
1582 case 22:/* WB type 6, AMR-WB 19.85 */
1583 case 23:/* WB type 7, AMR-WB 23.05 */
1584 case 24:/* WB type 8, AMR-WB 23.85 */
1585 if( frame_type >= 16 )
1586 RAB_To_DSP_Mapping = (const uint8 *) tblAMR_WBOrder[frame_type-16];
1587 else
1588 RAB_To_DSP_Mapping = tblAMROrder[frame_type];
1589 if( FQI_flag == KAL_TRUE )
1590 rx_type = SAL_3G_RX_SPEECH_GOOD;
1591 else
1592 rx_type = SAL_3G_RX_SPEECH_BAD;
1593
1594 sd_mode = GetFrameType2DspMode(frame_type);
1595 rx_len = GetDspModeLen(sd_mode);
1596 // move amr data to dl_buffer
1597
1598 total_bits = RAB_subflow[frame_type][0] + RAB_subflow[frame_type][1] + RAB_subflow[frame_type][2];
1599
1600 for(I = rx_len; --I >= 0; )
1601 *ptr16++ = 0;
1602
1603 ptr16 -= rx_len;
1604 idx = 0;
1605 if( sp3g->sp3g_mode == RAT_3G_MODE ){
1606 for(I = 0; I < 3; I ++)
1607 {
1608 if(RAB_subflow[frame_type][I] == 0)
1609 break;
1610#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1611 if (g_bNeedExtraLog == true){
1612 ASSERT( *ptr8 == *ptr8_bak );
1613 }
1614#endif
1615 rabBitsCount = RAB_subflow[frame_type][I];
1616 if(frame_type >= 16){
1617 const uint16* WB_RAB_To_DSP_Mapping;
1618 WB_RAB_To_DSP_Mapping = (const uint16*)RAB_To_DSP_Mapping;
1619 for(J = 0; J < rabBitsCount; J++)
1620 {
1621 K = WB_RAB_To_DSP_Mapping[idx++];
1622 bit16Data = (ptr8[J >> 3] & RAB_Order[J & 7])? DSP_Order[K & 15] : 0;
1623 ptr16[K >> 4] |= bit16Data;
1624 }
1625 } else {
1626 for(J = 0; J < rabBitsCount; J++)
1627 {
1628 uint32 t1;
1629 uint16 *t2;
1630 K = RAB_To_DSP_Mapping[idx++];
1631 bit16Data = (ptr8[J >> 3] & RAB_Order[J & 7])? DSP_Order[K & 15] : 0;
1632 t1 = K >> 4;
1633 t2 = ptr16 + t1;
1634
1635 //ptr16[K >> 4] |= bit16Data;
1636 *t2 |= bit16Data;
1637 }
1638 }
1639 ptr8 += (rabBitsCount + 7) >> 3;
1640#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1641 ptr8_bak += (rabBitsCount + 7) >> 3;
1642#endif
1643 }
1644 ASSERT(idx == total_bits);
1645 }
1646#ifdef __VIDEO_CALL_SUPPORT__
1647 else{//3G 324M
1648 I = 4;
1649 for(J = 0; J < total_bits; J++, I++)
1650 {
1651 K = RAB_To_DSP_Mapping[idx++];
1652 bit16Data = (ptr8[I >> 3] & AMR_IF2_Order[J & 7])? DSP_Order[K & 15] : 0;
1653 ptr16[K >> 4] |= bit16Data;
1654 }
1655 }
1656#endif
1657 sp3g->dtx_state = 0;
1658 break;
1659
1660 case 8: // AMR SID
1661 case 25:
1662 sidData = ptr8[4];
1663 if( sp3g->sp3g_mode == RAT_3G_MODE ){
1664 if( FQI_flag == KAL_TRUE )
1665 {
1666 if( sidData & 0x10 )
1667 rx_type = SAL_3G_RX_SID_UPDATE;
1668 else
1669 rx_type = SAL_3G_RX_SID_FIRST;
1670 sp3g->dtx_state = 1;
1671 }
1672 else
1673 rx_type = SAL_3G_RX_SID_BAD;
1674
1675 if( frame_type == 25 ){
1676 sd_mode = (sidData & 0xF);
1677
1678 if(sd_mode >= 10)
1679 {
1680 rx_type = SAL_3G_RX_SID_BAD;
1681 sd_mode = sp3g->pre_dl_report;
1682 } else if(9 == sd_mode){
1683 sd_mode = sp3g->pre_dl_report;
1684 } else {
1685 sd_mode = GetFrameType2DspMode(sd_mode+16);
1686 }
1687 } else
1688 {
1689 sd_mode = (sidData & 0xE) >> 1;// should reverse
1690 sd_mode = (sd_mode >> 2) | ((sd_mode & 0x1) << 2) | (sd_mode & 0x2);
1691 sd_mode = GetFrameType2DspMode(sd_mode);
1692 //sd_mode = AmrFrameType2DspMode[sd_mode]; // RX SD Mode
1693 }
1694 }
1695#ifdef __VIDEO_CALL_SUPPORT__
1696 else{//3G 324M
1697 if( sidData & 0x80 )
1698 rx_type = SAL_3G_RX_SID_UPDATE;
1699 else
1700 rx_type = SAL_3G_RX_SID_FIRST;
1701 sd_mode = GetFrameType2DspMode((ptr8[5] & 0x7));
1702 }
1703#endif
1704
1705 rx_len = 3; // 35 information bits
1706 // move sid data to dl_buffer
1707 for(I = 3; --I >= 0; )
1708 *ptr16++ = 0;
1709 ptr16 -= 3;
1710 Order = RAB_Order;
1711 if( sp3g->sp3g_mode == RAT_3G_MODE ){
1712 J = 0;
1713 Order = RAB_Order;
1714 }
1715#ifdef __VIDEO_CALL_SUPPORT__
1716 else{//3G324M
1717 J = 4;
1718 Order = AMR_IF2_Order;
1719 }
1720#endif
1721
1722 for(I = 0; I < 35; I++,J++)
1723 {
1724 bit16Data = (ptr8[J >> 3] & Order[I & 7])? DSP_Order[I & 15] : 0;
1725 ptr16[I >> 4] |= bit16Data;
1726 }
1727 #ifdef AMR_DATA_LOG
1728 if( rx_type == SAL_3G_RX_SID_FIRST )
1729 MD_TRC_SP3G_RX_SID_FIRST();
1730 else if( rx_type == SAL_3G_RX_SID_UPDATE )
1731 MD_TRC_SP3G_RX_SID_UPDATE();
1732 #endif
1733 break;
1734
1735 case 15: // NO DATA
1736 MD_TRC_SP3G_RX_NO_DATA();
1737 rx_type = SAL_3G_RX_NO_DATA;
1738 rx_len = 0;
1739 // no need to record codec mode , inherit from previous
1740 break;
1741
1742 default:
1743 ASSERT(false);
1744 break;
1745 }
1746 // get codec_mode , set RX codec_mode
1747 // get data from dl_read
1748 ptr16 = (uint16*) sp3g->dsp_buffer_dl;
1749
1750 SAL_3G_Set_RxType(rx_type);
1751
1752 //For NB/WB handover, it's decided by network set UL codec.
1753 // If downlink happens, set it as NO data.
1754 if( rx_type != SAL_3G_RX_NO_DATA )
1755 {
1756 if( (sd_mode <= 0x0A && sp3g->dl_report >= 0x20) ||
1757 (sd_mode >= 0x20 && sp3g->dl_report <= 0x0A) )
1758 {
1759 SAL_3G_Set_RxType(SAL_3G_RX_NO_DATA);
1760 SAL_3G_Upd_Dec_Cod(sp3g->dl_report);
1761 rx_type = SAL_3G_RX_NO_DATA;
1762 MD_TRC_SP3G_RX_FORCE_NO_DATA_WHEN_CHANGE_BAND();
1763 }
1764 }
1765 else if (data == (void *)2) {
1766#if defined(__SP3G_DL_BUFFER_BEFORE_PLAY__)
1767 AM_3G_INTRARAT(sp3g->ul_codec_mode);
1768 sp3g->ul_request_resync = KAL_FALSE;
1769#endif
1770 }
1771 if( rx_type != SAL_3G_RX_NO_DATA && rx_type != SAL_3G_RX_SID_BAD ) //if RX_NO_DATA or RX_SID_BAD, codec mode will use the previous one
1772 {
1773 volatile uint16 *addr;
1774 SAL_3G_Upd_Dec_Cod(sd_mode);
1775 addr = SAL_3G_GetAddr(SAL_3G_ADDR_RXHB);
1776 for(I = rx_len ; --I >= 0; )
1777 *addr++ = *ptr16++;
1778 Data_Sync_Barrier();
1779 }
1780
1781#if defined(__SP3G_UL_DSP_RESYNC_CSR__)
1782 if( data == (void *)2 ){
1783 sp3g->dl_count --;
1784 sp3g->dl_read_idx++;
1785 sp3g->dl_buffer_size = RAT_3G_DL_BUFFER_NUM; // 1 or 2
1786 } else
1787#endif
1788 {
1789 // update 3G dl_count
1790 sp3g->dl_count --;
1791 sp3g->dl_read_idx++;
1792 }
1793 if( sp3g->dl_read_idx >= sp3g->dl_buffer_size ){//near end of buffer
1794 sp3g->dl_read_idx = 0;
1795 }
1796 }
1797 MD_TRC_SP3G_SYNC(((uint8)SAL_3G_IsDLEmpty()<<1) + (uint8)SAL_3G_IsULReady());
1798 SAL_3G_SetDLReady(); // MCU tell DSP the data is ready
1799
1800 { /*for catcher log codec information*/
1801 uint8 txType, rxType, ber;
1802 txType = SAL_3G_GetValue(SAL_3G_VALUE_TX_TYPE);
1803 rxType = rx_type >> 1;
1804 ber = 255;//useless both for dsp and driver;
1805 //ber = (*DP_3G_DL_RX_TYPE & 0xFF00);
1806 MD_TRC_L1Audio_Msg_SPEECH_FRAME( L1SP_Speech_TX_Type(txType), L1SP_Speech_RX_Type(rxType), ber );
1807 //L1Audio_Msg_VM_DEBUG( DP2_3G_debug_info0, DP2_3G_debug_info1, DP2_3G_debug_info7 );
1808 }
1809}
1810
1811
1812void SP3G_Reset( void )
1813{
1814 sp3g_reset_flag = 1;
1815}
1816
1817kal_bool SP3G_IsDTXOn()
1818{
1819 return sp3g_dtx_mode;
1820}
1821
1822void SP3G_SetDTX(kal_bool on)
1823{
1824 sp3g_dtx_mode = on;
1825 MD_TRC_SP3G_SET_DTX(on);
1826 if( L1SP_GetState() == L1SP_STATE_3G_SPEECH_ON )
1827 {
1828 kal_take_spinlock(sp3g_spinlockID, KAL_INFINITE_WAIT);
1829 SAL_3G_SetDtx(on);
1830 kal_give_spinlock(sp3g_spinlockID);
1831 }
1832}
1833
1834// Force Rx Type to No data frame, used in speech off
1835void SP3G_SetRxTypeToNoData( void )
1836{
1837 SAL_3G_Set_RxType(SAL_3G_RX_NO_DATA);
1838}
1839
1840void sp3g_reset_internal( void )
1841{
1842 // DL side
1843 sp3g->dl_count = 0;
1844 sp3g->dl_write_idx = 0;
1845 sp3g->dl_read_idx = 0;
1846#if defined(__CSHSPA_SUPPORT__)
1847 sp3g->dl_buffer_size = sp3g_max_cs_delay;
1848#else
1849 sp3g->dl_buffer_size = RAT_3G_DL_BUFFER_NUM_BEFORE_RESYNC;
1850#endif
1851 sp3g_reset_flag = 0; // clear reset flag, wait it to be 2
1852}
1853
1854void sp3g_init( void )
1855{
1856 sp3g_is_csr_ready = false;
1857 sp3g_rab_id = 0;
1858 sp3g_rab_state = KAL_FALSE;
1859 l1AInfo = 0;
1860
1861#if !defined(__L1_STANDALONE__)
1862 CSR_SP3G_Callback = NULL;
1863#endif
1864#if defined(__CSHSPA_SUPPORT__)
1865 sp3g_max_cs_delay = 2;
1866#endif
1867
1868 sp3g_dtx_mode = 0;
1869
1870
1871#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1872 g_bNeedExtraLog = KAL_FALSE;
1873#endif
1874 sp3g_spinlockID = kal_create_spinlock("sp3g_spinlock");
1875 sp3g = &sp3gInfo;
1876}
1877
1878void sp3g_speech_init(uint8 RAT_Mode)
1879{
1880 ASSERT( (RAT_Mode == RAT_3G_MODE) || (RAT_Mode == RAT_3G324M_MODE) );
1881 ASSERT( L1SP_GetState() == L1SP_STATE_IDLE );
1882
1883#if !defined(__L1_STANDALONE__)
1884#ifdef __FAKE_3G_LOOPBACK__
1885 CSR_SP3G_Callback = fake_CSR_Speech_Callback;
1886 g_bNeedExtraLog = KAL_TRUE;
1887#else
1888 CSR_SP3G_Callback = csr_get_fp_CSR_SP3G_Callback();
1889#endif
1890#endif
1891 memset(sp3g, 0, sizeof(SP3G_Struct));
1892 sp3g->sp3g_mode = RAT_Mode;
1893 // UL side
1894 sp3g->waiting = KAL_FALSE;
1895
1896 sp3g->ul_write_idx = 0;
1897 sp3g->ul_read_idx = 0;
1898 sp3g->ul_count = 0;
1899 sp3g->is_getting_ul_data = KAL_FALSE;
1900 sp3g->under_interact = KAL_FALSE;
1901 sp3g->ul_delay = 0;
1902 sp3g->pre_ul_report = sp3g->pre_dl_report = sp3g->ul_report = sp3g->dl_report = INIT_3G_CODEC;
1903
1904 if( sp3g->sp3g_mode == RAT_3G_MODE )
1905 sp3g->ul_buffer_size = RAT_3G_UL_BUFFER_NUM;
1906#ifdef __VIDEO_CALL_SUPPORT__
1907 else //3G324M
1908 sp3g->ul_buffer_size = MAX_3G_UL_BUFFER_NUM;
1909#endif
1910#if defined(UL_HARD_REAL_TIME_DEMAND)
1911 sp3g->ul_buffer_size = HARD_REAL_TIME_UL_BUFFER_NUM;
1912#endif
1913
1914#ifdef __FAKE_3G_LOOPBACK__
1915 if(get_is_fake_3g()){
1916 ;//sp3g->ul_codec_mode = INIT_3G_CODEC; applya the previous codec
1917 }else{
1918 sp3g->ul_codec_mode = INIT_3G_CODEC;
1919 }
1920#else
1921 sp3g->ul_codec_mode = INIT_3G_CODEC;
1922#endif
1923
1924 sp3g->ul_refresh = KAL_FALSE; // detect change codec_mode
1925
1926 // DL side
1927 sp3g->dl_count = 0;
1928 sp3g->dl_write_idx = 0;
1929 sp3g->dl_read_idx = 0;
1930
1931 if( sp3g->sp3g_mode == RAT_3G_MODE ){
1932#if defined(__CSHSPA_SUPPORT__)
1933 sp3g->dl_buffer_size = sp3g_max_cs_delay;
1934#else
1935 sp3g->dl_buffer_size = RAT_3G_DL_BUFFER_NUM_BEFORE_RESYNC;
1936#endif
1937 sp3g_reset_flag = 1;
1938 }
1939 else{ // 3G324M
1940 sp3g->dl_buffer_size = MAX_3G_DL_BUFFER_NUM;
1941 sp3g_reset_flag = 2;
1942 }
1943
1944#if defined(SP3G_UNIT_TEST)
1945 L1Audio_HookHisrHandler(DP_D2C_3G,(L1Audio_EventHandler)sp3g_hisr_2, 0);
1946#else
1947#if 0//!defined(__UNIFIED_ISR_LEVEL__)
1948/* under construction !*/
1949#endif
1950 L1Audio_HookHisrHandler(DP_D2C_3G_DONE_UL,(L1Audio_EventHandler)sp3g_hisr_ul, 0);
1951#endif
1952 SAL_3G_Upd_Enc_Cod(sp3g->ul_codec_mode);
1953 SAL_3G_Upd_Dec_Cod(sp3g->ul_codec_mode);
1954#if defined(__SP3G_UL_DSP_RESYNC_CSR__)
1955 sp3g->int_time[0] = 0;
1956 sp3g->int_time[1] = 0;
1957 sp3g->int_time[2] = 0;
1958 sp3g->int_time[3] = 0;
1959 sp3g->int_time[4] = 0;
1960 sp3g->ul_request_resync = KAL_FALSE;
1961#endif
1962 sp3g->l1_info_idx = 0;
1963 sp3g->dtx_state = 0;
1964}
1965
1966void sp3g_speech_close( bool IsInterRAT )
1967{
1968#if 0//!defined(__UNIFIED_ISR_LEVEL__)
1969/* under construction !*/
1970#endif
1971 L1Audio_UnhookHisrHandler(DP_D2C_3G_DONE_UL);
1972 //kal_take_spinlock(sp3g_spinlockID, KAL_INFINITE_WAIT);
1973 //free_ctrl_buffer(sp3g);
1974 //sp3g = (SP3G_Struct*) 0;
1975 //kal_give_spinlock(sp3g_spinlockID);
1976#if defined(__CSHSPA_SUPPORT__)
1977 sp3g_max_cs_delay = 2;
1978 //reset to 2 frame
1979#if defined(CSHSPA_UNIT_TEST)
1980 L1Audio_FreeAudioID(sp3g_hspa_aud_id);
1981#endif
1982#endif
1983
1984 /* only these cases should wait state, if only 2G happen, then return to idle */
1985 if( L1SP_GetState() == L1SP_STATE_3G_SPEECH_ON || L1SP_GetState() == L1SP_STATE_3G_SPEECH_CLOSING || IsInterRAT
1986#ifdef __VIDEO_CALL_SUPPORT__
1987 || L1SP_GetState() == L1SP_STATE_3G324M_SPEECH_ON
1988#endif
1989 ){
1990 //uint32 waitTime;
1991#ifdef __VIDEO_CALL_SUPPORT__
1992 if( L1SP_GetState() == L1SP_STATE_3G324M_SPEECH_ON )
1993 vt_SP3G_Callback( (kal_uint8)SP3G_CODEC_CLOSED, (void*)0);
1994 else
1995#endif
1996 CSR_Codec_Close(SP3G_Rab_Id());
1997 }
1998#if !defined(__L1_STANDALONE__)
1999 kal_take_spinlock(sp3g_spinlockID, KAL_INFINITE_WAIT);
2000 CSR_SP3G_Callback = NULL;
2001 kal_give_spinlock(sp3g_spinlockID);
2002#endif
2003}
2004
2005void SP3G_Request(void)
2006{
2007 MD_TRC_SP3G_REQUEST();
2008 L1SP_3G_Request();
2009}
2010
2011kal_uint32 SP3G_GetCodecMode(void)
2012{
2013 if(sp3g != NULL)
2014 return sp3g->ul_codec_mode;
2015 else
2016 return INIT_3G_CODEC;
2017}
2018
2019void SP3G_UL_SetFrameType(uint8 amr_frame_type) // function call
2020{
2021 uint8 state;
2022 uint32 codec;
2023 if( (state = L1SP_GetState()) != L1SP_STATE_3G_SPEECH_ON)
2024 {
2025 //if(state == L1SP_STATE_3G_SPEECH_CLOSING)
2026 return;
2027 //else
2028 //ASSERT(false);
2029 }
2030
2031 ASSERT(sp3g != (SP3G_Struct*) 0);
2032
2033 codec = AmrFrameType2DspMode[amr_frame_type];
2034 if((sp3g->ul_codec_mode >= 0x20 && codec <= 0x0A) ||
2035 (sp3g->ul_codec_mode <= 0x0A && codec >= 0x20)){//Intrarat
2036 sp3g->under_interact = KAL_TRUE;
2037 sp3g->ul_codec_mode = codec;
2038 AM_3G_INTRARAT(codec);
2039 sp3g->under_interact = KAL_FALSE;
2040 SP3G_Reset();
2041 MD_TRC_SP3G_DEBUG_UL_SETFRAMETYPE(1, sp3g->ul_codec_mode, codec, amr_frame_type);
2042 //L1SP_SetState( L1SP_STATE_3G_SPEECH_ON );
2043 }else{
2044 MD_TRC_SP3G_DEBUG_UL_SETFRAMETYPE(2, sp3g->ul_codec_mode, codec,amr_frame_type);
2045 sp3g->ul_codec_mode = codec;
2046 sp3g->ul_refresh = KAL_TRUE;
2047 }
2048}
2049
2050// do bit reorder here
2051
2052void sub_SP3G_UL_GetSpeechFrame(kal_uint16*frame_index, kal_uint8 *frame_type, kal_uint8 *rab_byte_array, kal_uint8 *len)
2053{
2054 uint8 *ptr8;
2055 int32 I;
2056 uint16 sc_mode=0;
2057 uint8 state;
2058
2059 if( (state = L1SP_GetState()) != L1SP_STATE_3G_SPEECH_ON){
2060 *frame_index = 0xABCD;
2061 *frame_type = AMR_NO_DATA;
2062 *len = 0;
2063 MD_TRC_SP3G_UL_PUT_SPEECH_FRAME_DEBUG(0);
2064 return;
2065 }
2066
2067 ASSERT(sp3g != (SP3G_Struct*) 0);
2068 MD_TRC_SP3G_UL_GET_SPEECH_FRAME();
2069
2070 //ASSERT(sp3g->waiting == KAL_TRUE); // 1 message 1 get ,
2071 // should take care if CSR doesn't get by DATA_NOTIFY message
2072#if defined(__SP3G_UL_DSP_RESYNC_CSR__)
2073 sp3g->int_time[2] = ust_get_current_time(); // log temp UL time
2074 MD_TRC_SP3G_UL_TIMING(sp3g->int_time[2]/1000);
2075#endif
2076
2077 *frame_index = 0xABCD; // tmp setting , should be apply true value in near future , Adam
2078 kal_take_spinlock(sp3g_spinlockID, KAL_INFINITE_WAIT);
2079 sp3g->is_getting_ul_data = KAL_TRUE;
2080 kal_give_spinlock(sp3g_spinlockID);
2081
2082 if(sp3g->ul_count == 0)// or should repeat last frame
2083 {
2084 *frame_type = AMR_NO_DATA;
2085 *len = 0;
2086 sp3g->is_getting_ul_data = KAL_FALSE;
2087 SAL_3G_SetULUnsync();
2088 MD_TRC_SP3G_UL_PUT_SPEECH_FRAME_DEBUG(1);
2089 return;
2090 }
2091
2092#if defined(__SP3G_UL_DSP_RESYNC_CSR__)
2093 {
2094 kal_uint32 time_diff, time_diff_request_resync;
2095 static kal_uint32 time_request_resync = 0;
2096 time_diff = ust_us_duration( sp3g->int_time[3], sp3g->int_time[2] ) / 1000;
2097 time_diff_request_resync = ust_us_duration( time_request_resync, sp3g->int_time[2] ) / 1000;
2098 if( (time_diff == 0 || time_diff >= 20 ) && sp3g->ul_request_resync == KAL_FALSE && time_diff_request_resync > 200 /*larger than a certain time to wait resync done*/) {
2099 sp3g_reset_flag = 1;
2100 //Do not repeat set sp3g_reset_flag = 1
2101 sp3g->ul_request_resync = KAL_TRUE;
2102 time_request_resync = sp3g->int_time[2];
2103 MD_TRC_SP3G_FOUND_UL_SYNC_TIMING_ERROR();
2104 }
2105 }
2106#endif
2107 //frame_index = 0xABCD; // tmp setting , should be apply true value in near future , Adam
2108 //sp3g->is_getting_ul_data = KAL_TRUE;
2109
2110 ptr8 = (uint8*)sp3g->ul_buffer[sp3g->ul_read_idx];
2111
2112 *frame_type = *ptr8;
2113#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2114 if (g_bNeedExtraLog == true){
2115 uint8 *tmp_ = (uint8*)sp3g->ul_buffer[sp3g->ul_read_idx];
2116 //kal_prompt_trace(MOD_L1SP,"SP3G UL Type %d, Frm %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x",
2117 // *frame_type, ptr8[0], ptr8[1],ptr8[2],ptr8[3],ptr8[4],
2118 // ptr8[5],ptr8[6],ptr8[7],ptr8[8],ptr8[9],ptr8[10],ptr8[11],ptr8[12],ptr8[13],ptr8[14],ptr8[15], ptr8[16],ptr8[17],ptr8[18],ptr8[19],ptr8[20]);
2119 MD_TRC_SP3G_DEBUG_UL_GETSPEECHFRAME(sp3g->ul_read_idx);
2120 MD_TRC_SP3G_UL_BIT_TRUE_F8(
2121 0, *frame_type, tmp_[0], tmp_[1],tmp_[2],tmp_[3],tmp_[4],tmp_[5],tmp_[6],tmp_[7]);
2122 MD_TRC_SP3G_UL_BIT_TRUE_N13(
2123 tmp_[8],tmp_[9],tmp_[10],tmp_[11],tmp_[12],tmp_[13],tmp_[14],tmp_[15],
2124 tmp_[16],tmp_[17],tmp_[18],tmp_[19],tmp_[20]);
2125 }
2126#endif
2127 if(*frame_type < AMR_SID_FRAME)
2128 sc_mode = AmrFrameType2DspMode[*frame_type];
2129 else if(*frame_type >= 16 && *frame_type <= 24){
2130 sc_mode = AmrFrameType2DspMode[*frame_type];
2131 *ptr8 -= 16;//in subflow data, remap to 0~8?????
2132 }else if( *frame_type == 25 ){ //WB AMR SID
2133 *ptr8 = AWB_SID_FRAME; //in subflow data, remap to 9
2134 }
2135 ptr8++;
2136
2137#if defined( __UMTS_RAT__ )
2138 if(!SP3G_Rab_State()){
2139 MD_TRC_SP3G_UL_GET_SPEECH_FRAME_SKIP(0);
2140 *frame_type = AMR_NO_DATA;
2141 *len = 0;
2142 return;
2143 }else{
2144 switch(L1SP_GetSIMStatus()){
2145 case SP_3G_SIM_FDD_ACTIVE:
2146 if((*frame_type < 8) && sc_mode < sp3g->ul_codec_mode) // maximum bit_rate limitation
2147 {
2148 MD_TRC_SP3G_UL_GET_SPEECH_FRAME_SKIP(1);
2149 *frame_type = AMR_NO_DATA;
2150 *len = 0;
2151 }
2152 else
2153 {
2154 *len = *ptr8++;
2155 ASSERT( *len <= 60 );
2156
2157 for( I = *len; --I >= 0 ; )
2158 *rab_byte_array++ = *ptr8++;
2159 }
2160 break;
2161 case SP_3G_SIM_TDD_ACTIVE:
2162 if( sc_mode != sp3g->ul_codec_mode) // maximum bit_rate limitation
2163 {
2164 MD_TRC_SP3G_UL_GET_SPEECH_FRAME_SKIP(2);
2165 *frame_type = AMR_NO_DATA;
2166 *len = 0;
2167 }
2168 else
2169 {
2170 *len = *ptr8++;
2171 ASSERT( *len <= 60 );
2172
2173 for( I = *len; --I >= 0 ; )
2174 *rab_byte_array++ = *ptr8++;
2175 }
2176 break;
2177 default:
2178 ASSERT(0);
2179 }
2180 }
2181#endif
2182
2183
2184// kal_take_spinlock(sp3g_spinlockID, KAL_INFINITE_WAIT);
2185 sp3g->waiting = KAL_FALSE;
2186 sp3g->ul_delay = 0;
2187 sp3g->ul_count--;
2188// kal_give_spinlock(sp3g_spinlockID);
2189 sp3g->ul_read_idx++;
2190 if( sp3g->ul_read_idx == sp3g->ul_buffer_size )
2191 sp3g->ul_read_idx = 0;
2192 sp3g->is_getting_ul_data = KAL_FALSE;
2193}
2194
2195void SP3G_UL_GetSpeechFrame(kal_uint16*frame_index, kal_uint8 *frame_type, kal_uint8 *rab_byte_array, kal_uint8 *len)
2196{
2197 kal_take_enh_mutex( sp_handover_mutex );
2198 sub_SP3G_UL_GetSpeechFrame(frame_index, frame_type, rab_byte_array, len);
2199 kal_give_enh_mutex( sp_handover_mutex );
2200}
2201
2202const uint8 last_sub_flow_id[26] = { 1, 1, 1, 1, 1, 1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0};
2203
2204// do bit reorder here
2205void sub_SP3G_DL_PutSpeechFrame(uint32 CFN, uint8 sub_flow_id, uint8 frame_type, bool crc_status, uint8 *subflow)
2206{
2207 int32 I;
2208 uint8 *ptr8;
2209#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2210 uint8 *ptr8_bak;
2211#endif
2212 uint16 rabBitsCount, state;
2213
2214
2215 if( (state = L1SP_GetState()) != L1SP_STATE_3G_SPEECH_ON)
2216 {
2217 if(state == L1SP_STATE_3G_SPEECH_CLOSING){
2218 MD_TRC_SP3G_DL_PUT_SPEECH_FRAME_DEBUG(0);
2219 }else {
2220 MD_TRC_SP3G_DL_PUT_SPEECH_FRAME_DEBUG(1);
2221 }
2222 return;
2223 }
2224
2225 ASSERT(sp3g != (SP3G_Struct*) 0);
2226
2227 MD_TRC_SP3G_DL_PUT_SPEECH_FRAME(sub_flow_id, frame_type, crc_status);
2228#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2229 if( sub_flow_id == 0 && (frame_type == 8 || frame_type == 25) ) {
2230 //kal_prompt_trace(MOD_L1SP,"SP3G DL Frm %x %x %x %x %x", subflow[0], subflow[1],subflow[2],subflow[3],subflow[4]);
2231 MD_TRC_SP3G_DL_BIT_TRUE_TASK(subflow[0], subflow[1],subflow[2],subflow[3],subflow[4]);
2232 }
2233#endif
2234 //if( frame_type == AMR_NO_DATA )
2235 // return;
2236
2237 ASSERT( frame_type <= 25 );
2238
2239
2240
2241 if( sp3g_reset_flag == 1 ){
2242 sp3g_reset_internal();
2243 }
2244
2245
2246 if( sub_flow_id > last_sub_flow_id[frame_type] ){
2247 return;
2248 }
2249
2250 if( sp3g->dl_count >= sp3g->dl_buffer_size )
2251 {
2252 sp3g->dl_read_idx++;
2253 if( sp3g->dl_read_idx >= sp3g->dl_buffer_size )
2254 sp3g->dl_read_idx = 0;
2255 sp3g->dl_count --;
2256 }//keep only 2 frame
2257
2258
2259 ptr8 = sp3g->dl_buffer[sp3g->dl_write_idx];
2260#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2261 ptr8_bak = sp3g->dl_buffer2[sp3g->dl_write_idx];
2262#endif
2263 if( sub_flow_id == 0 )
2264 {
2265 //frame_len = RAB_subflow[frame_type][3];
2266
2267 // before first RB-subflow write
2268 *ptr8++ = frame_type;
2269#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2270 *ptr8_bak++ = frame_type;
2271#endif
2272 *ptr8++ = (uint8)crc_status;
2273#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2274 *ptr8_bak++ = (uint8)crc_status;
2275#endif
2276 *ptr8++ = CFN & 0xFF;
2277#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2278 *ptr8_bak++ = CFN & 0xFF;
2279#endif
2280 *ptr8++ = (CFN >> 8) & 0xFF;
2281#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2282 *ptr8_bak++ = (CFN >> 8) & 0xFF;
2283#endif
2284 *ptr8++ = (CFN >> 16) & 0xFF;
2285#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2286 *ptr8_bak++ = (CFN >> 16) & 0xFF;
2287#endif
2288 *ptr8++ = (CFN >> 24) & 0xFF;
2289#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2290 *ptr8_bak++ = (CFN >> 24) & 0xFF;
2291#endif
2292 }
2293 else
2294 {
2295 if( frame_type > AMR_NO_DATA && sub_flow_id == 1 ){
2296 //For WB-AMR, the frame type can not be differed in subflow 0,
2297 // so that update it at subflow 1
2298 *ptr8 = frame_type;//Range 16~25
2299 }
2300
2301 //kal_prompt_trace(MOD_L1SP,"SP3G DL r=%d,w=%d,n=%d",sp3g->dl_read,sp3g->dl_write,sp3g->dl_count);
2302 ptr8 += 6;
2303#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2304 ptr8_bak += 6;
2305#endif
2306 for(I = 0 ; I < sub_flow_id ; I ++)
2307 {
2308 rabBitsCount = RAB_subflow[frame_type][I];
2309 ptr8 += (rabBitsCount + 7) >> 3;
2310#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2311 ptr8_bak += (rabBitsCount + 7) >> 3;
2312#endif
2313 }
2314 }
2315
2316 rabBitsCount = RAB_subflow[frame_type][sub_flow_id];
2317
2318 for( I = 0; I < (rabBitsCount + 7) >> 3; I++ ){
2319#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2320 *ptr8++ = *subflow;
2321 *ptr8_bak++ = *subflow++;
2322#else
2323 *ptr8++ = *subflow++;
2324#endif
2325 }
2326
2327 // after last RB-subflow write
2328 if( sub_flow_id == last_sub_flow_id[frame_type] )
2329 {
2330 kal_uint8 u8CheckBufFinish = 0;
2331 sp3g->dl_write_idx++;
2332 if( sp3g->dl_write_idx >= sp3g->dl_buffer_size )
2333 sp3g->dl_write_idx = 0;
2334#if defined(__SP3G_UL_DSP_RESYNC_CSR__)
2335 sp3g->int_time[1] = ust_get_current_time();
2336 if(sp3g->int_time[1] > sp3g->int_time[2]){
2337 sp3g->int_time[0] = sp3g->int_time[2];
2338 }
2339
2340 MD_TRC_SP3G_DL_TIMING(sp3g->int_time[1]/1000);
2341#endif
2342#if defined(__SP3G_DIRECT_TO_DSP__)
2343 if(sp3g_reset_flag == 2 ){// reset done
2344 uint32 time_diff;
2345 time_diff = ust_get_duration_true( sp3g->int_time[4], sp3g->int_time[1] );
2346 time_diff = ( ( time_diff / 1000 ) - sp3g->uDelW ) % 20; //Time difference between sending-resync and SP3G_DL_PUT_SPEECH_FRAME
2347 if(time_diff == 0){ //It's too close, trigger reset
2348 MD_TRC_SP3G_FOUND_DL_SYNC_TIMING_ERROR();
2349 sp3g_reset_flag = 1;
2350 }
2351 }
2352 if(sp3g_reset_flag == 2 ){// reset done
2353 u8CheckBufFinish = 1;
2354 }
2355#endif
2356
2357
2358 sp3g->dl_count ++;
2359 if( sp3g->dl_count == sp3g->dl_buffer_size && sp3g_reset_flag == 0 ){
2360 sp3g_reset_flag = 2;// reset done
2361 u8CheckBufFinish = 2;
2362 }
2363
2364
2365#ifdef __FAKE_3G_LOOPBACK__
2366 if(get_is_fake_3g()){
2367 sp3g_reset_flag = 2;// reset done
2368 u8CheckBufFinish = 1;
2369 }
2370#endif
2371
2372 if( u8CheckBufFinish == 1 ){
2373#if 1//defined(__UNIFIED_ISR_LEVEL__) //Since MT6290, LISR has been depricated, and only HISR and Task are left. Therefore, to avoid affecting the OS scheduling, System Service prohibits any attempt to invoke HISR from a task level
2374 sp3g_hisr_dl((void *)0);
2375#else
2376/* under construction !*/
2377#endif
2378 } else if ( u8CheckBufFinish == 2 ){
2379#if 1//defined(__UNIFIED_ISR_LEVEL__)
2380 sp3g_hisr_dl((void *)2);
2381#else
2382/* under construction !*/
2383#endif
2384 MD_TRC_SP3G_DL_BUFFER_FINISH();
2385 }
2386 }
2387}
2388
2389void SP3G_DL_PutSpeechFrame(uint32 CFN, uint8 sub_flow_id, uint8 frame_type, bool crc_status, uint8 *subflow)
2390{
2391 kal_take_enh_mutex( sp_handover_mutex );
2392 sub_SP3G_DL_PutSpeechFrame(CFN, sub_flow_id, frame_type, crc_status, subflow);
2393 kal_give_enh_mutex( sp_handover_mutex );
2394}
2395
2396
2397typedef struct
2398{
2399 kal_uint8 RSSI;
2400 kal_uint8 RSCP;
2401 kal_uint8 ECIO;
2402 kal_uint8 HHO_SHO;
2403/* Used by UMAC */
2404 /* Modified CRC = CRC |(S value decision)
2405 S value decision=1 => S value < S Threshold. this frame is not reliable
2406 S value decision =0 => S value > S Threshold. This frame is reliable
2407
2408 Modified CRC =0, speech good, CRC=0, S value decision =0
2409 Modified CRC=1, CRC =1 or S value decision=1
2410
2411 crc_result value meaning :
2412 0 : Modified CRC = 0
2413 1 : Modified CRC = 1, CRC = 0
2414 2 : Modified CRC = 1, CRC = 1
2415 */
2416 kal_uint8 crc_result[3]; /* For Class A/B/C */
2417 kal_uint32 s_value[3]; /* For Class A/B/C */
2418
2419 kal_int16 tpc_SIR_lta; // For recording into speech VM
2420 kal_int16 dpdch_SIR_lta; // For recording into speech VM
2421 kal_int16 TFCI_max_corr; // For recording into speech VM
2422}L1_info_struct;
2423
2424void SP3G_Log_L1_Info(uint32 CFN, L1_info_struct *p_L1_Info)
2425{
2426 uint32 *l1_info;
2427 uint32 l1_data, crc_result;
2428
2429 kal_take_enh_mutex( sp_handover_mutex );
2430 if(L1SP_GetState() != L1SP_STATE_3G_SPEECH_ON){
2431 kal_give_enh_mutex( sp_handover_mutex );
2432 return;
2433 }
2434 l1_info = sp3g->L1_Info[sp3g->l1_info_idx++];
2435 sp3g->l1_info_idx &= 0x3;
2436
2437 l1_info[0] = CFN;
2438 l1_data = (uint32)(p_L1_Info->RSSI) + ((uint32)(p_L1_Info->RSCP) << 8) +
2439 ((uint32)(p_L1_Info->ECIO) << 16) + ((uint32)(p_L1_Info->HHO_SHO) << 24);
2440 crc_result = (uint32)(p_L1_Info->crc_result[0]) + ((uint32)(p_L1_Info->crc_result[1]) << 8) +
2441 ((uint32)(p_L1_Info->crc_result[2]) << 16);
2442 l1_info[1] = l1_data;
2443 l1_info[2] = crc_result;
2444 l1_info[3] = p_L1_Info->s_value[0];
2445 l1_info[4] = (uint32)p_L1_Info->tpc_SIR_lta;
2446 l1_info[5] = (uint32)p_L1_Info->dpdch_SIR_lta;
2447 l1_info[6] = (uint32)p_L1_Info->TFCI_max_corr;
2448 MD_TRC_SP3G_LOG_L1_INFO(
2449 l1_info[0], l1_info[1], crc_result, p_L1_Info->s_value[0], p_L1_Info->s_value[1],p_L1_Info->s_value[2]);
2450 kal_give_enh_mutex( sp_handover_mutex );
2451}
2452
2453void SP3G_Closed_Confirm( void )
2454{
2455 //ASSERT( L1SP_GetState() != L1SP_STATE_3G_SPEECH_ON );
2456 //L1SP_SetState(L1SP_STATE_3G_SPEECH_CLOSED);
2457}
2458/*====================== CS over HSPA interface ============================*/
2459#if defined(__CSHSPA_SUPPORT__)
2460void SP3GHSPA_UL_GetSpeechFrame(kal_uint8 *frame_type, kal_uint8 *rab_byte_array, kal_uint8 *len)
2461{
2462 kal_uint16 frame_index, I, J, K, rabBitsCount;
2463 kal_uint8 *ptr8, *ptr8_swap, byte_swap, bit8Data;
2464 kal_take_enh_mutex( sp_handover_mutex );
2465
2466#if 0
2467/* under construction !*/
2468/* under construction !*/
2469/* under construction !*/
2470/* under construction !*/
2471/* under construction !*/
2472/* under construction !*/
2473/* under construction !*/
2474/* under construction !*/
2475/* under construction !*/
2476/* under construction !*/
2477/* under construction !*/
2478/* under construction !*/
2479/* under construction !*/
2480/* under construction !*/
2481/* under construction !*/
2482/* under construction !*/
2483#else
2484//#if 1
2485 sub_SP3G_UL_GetSpeechFrame(&frame_index, frame_type, rab_byte_array, len);
2486 //reorder to AMR IF1
2487 if( *frame_type != AMR_NO_DATA && *frame_type != 25 && *frame_type != AMR_SID_FRAME )
2488 {
2489 ptr8 = rab_byte_array;
2490 ptr8_swap = rab_byte_array;
2491 byte_swap = *ptr8_swap;
2492 *ptr8 = 0;
2493 K = 0;
2494 for( I = 0 ; I < 3 ; I++ ){
2495 rabBitsCount = RAB_subflow[*frame_type][I];
2496 for( J = 0; J < rabBitsCount ; J++, K++ ){
2497 bit8Data = (byte_swap & RAB_Order[J & 7])? RAB_Order[K & 7] : 0;
2498 *ptr8 |= bit8Data;
2499 if( (J&7) == 7 ){
2500 ptr8_swap++;
2501 byte_swap = *ptr8_swap;
2502 }
2503 if( (K&7) == 7 ){
2504 ptr8++;
2505 *ptr8 = 0;
2506 }
2507 }
2508 if( (J&7) != 0 ){ // avoid false advance a byte
2509 ptr8_swap++;
2510 byte_swap = *ptr8_swap;
2511 }
2512 }
2513 //recalculate rab length
2514 rabBitsCount = 0;
2515 for( I = 0 ; I < 3 ; I++ )
2516 rabBitsCount += RAB_subflow[*frame_type][I];
2517 *len = ((rabBitsCount+7)>>3);
2518 }
2519#endif
2520 MD_TRC_SP3G_HSPA_UL_GET_SPEECH_FRAME(*frame_type, *len, rab_byte_array[0], rab_byte_array[1]);
2521 kal_give_enh_mutex( sp_handover_mutex );
2522}
2523
2524kal_uint8 subflow_null[32];
2525void SP3GHSPA_DL_PutSpeechFrame(kal_uint32 CFN, kal_uint8 frame_type, kal_bool crc_status, kal_uint8 *subflow)
2526{
2527 kal_take_enh_mutex( sp_handover_mutex );
2528
2529 if(NULL != subflow) {
2530 MD_TRC_SP3G_HSPA_DL_PUT_SPEECH_FRAME(frame_type, CFN, crc_status, subflow[0], subflow[1]);
2531 }
2532 else {
2533 MD_TRC_SP3G_HSPA_DL_PUT_SPEECH_FRAME(frame_type, CFN, crc_status, 0, 0);
2534 }
2535 if( frame_type != AMR_NO_DATA && frame_type != 25 && frame_type != AMR_SID_FRAME ){
2536 kal_uint16 I, J, K, rabBitsCount;
2537 kal_uint8 *ptr8, *ptr8_swap, byte_swap, bit8Data;
2538
2539 K = 0;
2540 ptr8_swap = subflow;
2541 byte_swap = *ptr8_swap;
2542 for( I = 0 ; I < 3 ; I++ ){
2543 rabBitsCount = RAB_subflow[frame_type][I];
2544 if( rabBitsCount == 0 )
2545 break;
2546 ptr8 = &sp3g->dl_subflow[0];
2547 *ptr8 = 0;//reset
2548 for( J = 0; J < rabBitsCount ; J++, K++ ){
2549 bit8Data = (byte_swap & RAB_Order[K & 7])? RAB_Order[J & 7] : 0;
2550 *ptr8 |= bit8Data;
2551 if( (J&7) == 7 ){
2552 ptr8++;
2553 *ptr8 = 0;
2554 }
2555 if( (K&7) == 7 ){
2556 ptr8_swap++;
2557 byte_swap = *ptr8_swap;
2558 }
2559 }
2560 sub_SP3G_DL_PutSpeechFrame(CFN, I, frame_type, crc_status, sp3g->dl_subflow);
2561 }
2562 } else {
2563 if(NULL != subflow) {
2564 sub_SP3G_DL_PutSpeechFrame(CFN, 0, frame_type, crc_status, subflow);
2565 }
2566 else {
2567 sub_SP3G_DL_PutSpeechFrame(CFN, 0, frame_type, crc_status, subflow_null);
2568 }
2569 }
2570 kal_give_enh_mutex( sp_handover_mutex );
2571}
2572
2573void SP3GHSPA_DL_SetMaxCsDelay(kal_uint8 max_cs_delay)
2574{
2575 MD_TRC_SP3G_HSPA_DL_MAX_CS_DELAY(max_cs_delay);
2576
2577 sp3g_max_cs_delay = (max_cs_delay + 19) / 20;
2578 ASSERT(sp3g_max_cs_delay <= 10);
2579 if( sp3g_max_cs_delay < 2 )
2580 sp3g_max_cs_delay = 2;
2581#if 1
2582 if(L1SP_GetState() != L1SP_STATE_3G_SPEECH_ON || sp3g == NULL )
2583 return;
2584
2585
2586 kal_take_spinlock(sp3g_spinlockID, KAL_INFINITE_WAIT);
2587
2588 //Already in speech, allow extend buffer size
2589 if(sp3g->dl_buffer_size < sp3g_max_cs_delay){
2590 sp3g->dl_buffer_size = sp3g_max_cs_delay;
2591 }
2592
2593 kal_give_spinlock(sp3g_spinlockID);
2594
2595
2596#endif
2597}
2598
2599#endif // if defined(__CSHSPA_SUPPORT__)
2600
2601#endif // __UMTS_RAT__