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192.168.1.100 / T800_MD / 1eb8f53f94c145708b5ea2c6b9b96ea3d613f607 / . / mcu / driver / devdrv / bsi / inc / drv_bsi.h
blob: 4fcddab90954f6ed45d2266fb4b892eccc1573b3 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2013
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*******************************************************************************
37 * Filename:
38 * ---------
39 * drv_bsi.h
40 *
41 * Project:
42 * --------
43 * MOLY
44 *
45 * Description:
46 * ------------
47 * BSI (Baseband Serial Interface) Driver
48 *
49 * Author:
50 * -------
51 * -------
52 *
53 * ==========================================================================
54 * $Log$
55 *
56 * 03 06 2013 yu-hung.huang
57 * [MOLY00011206] BSI-PMIC Driver
58 * [TRUNK] add failWrite BSI-PMIC API for reset test
59 *
60 * 03 06 2013 yu-hung.huang
61 * [MOLY00011206] BSI-PMIC Driver
62 * [TRUNK] BSI-PMIC driver update after testing on MT6339 ES1
63 *
64 * 03 01 2013 yu-hung.huang
65 * [MOLY00011206] BSI-PMIC Driver
66 * [TRUNK] add BSI-PMIC driver design and .mak
67 ****************************************************************************/
68
69#ifndef __DRV_REG_H__
70#define __DRV_REG_H__
71
72#include <bsi_reg.h>
73
74// BSICTRL MAC
75#define BSI_MAC_STOP (1UL << 0)
76#define BSI_MAC_RD_EN (1UL << 4)
77
78#define BSI_MAC_RD_EN_BIT_OFFSET (4)
79#define BSI_MAC_STATUS_BIT_OFFSET (8)
80#define BSI_MAC_CS_SEL_BIT_OFFSET (12)
81#define BSI_MAC_PORT_SEL_BIT_OFFSET (13)
82
83#define BSI_MAC_RD_EN_MASK (0x00000010)
84#define BSI_MAC_CS_SEL_MASK (0x00001000)
85#define BSI_MAC_PORT_SEL_MASK (0x0000E000)
86
87#define BSI_MAC_RDINT_STS_BIT (1UL << 0)
88#define BSI_MAC_RDINT_EN (1UL << 8)
89
90#define BSI_MAC_RDATA_3532_OFFSET (0)
91#define BSI_MAC_RDATA_3532_MASK (0xF << BSI_MAC_RDATA_3532_OFFSET)
92
93#define SET_BSI_MAC_CTRL(_port, _cs, _op) \
94 do{ \
95 kal_uint32 tmp; \
96 tmp = (DRV_Reg32(BSI_MAC_CTRL_REG) & (~(BSI_MAC_RD_EN_MASK | BSI_MAC_CS_SEL_MASK | BSI_MAC_PORT_SEL_MASK))); \
97 DRV_WriteReg32(BSI_MAC_CTRL_REG, (tmp | (_port << BSI_MAC_PORT_SEL_BIT_OFFSET) | (_cs << BSI_MAC_CS_SEL_BIT_OFFSET) | (_op << BSI_MAC_RD_EN_BIT_OFFSET)) ); \
98 } while(0)
99#define SET_BSI_MAC_READ_EVENT do{ \
100 kal_uint32 tmp; \
101 tmp = DRV_Reg32(BSI_MAC_CTRL_REG); \
102 DRV_WriteReg32(BSI_MAC_CTRL_REG, (BSI_MAC_RD_EN | tmp)); \
103 } while(0)
104#define SET_BSI_MAC_WRITE_EVENT do{ \
105 kal_uint32 tmp; \
106 tmp = DRV_Reg32(BSI_MAC_CTRL_REG); \
107 DRV_WriteReg32(BSI_MAC_CTRL_REG, ((~BSI_MAC_RD_EN) & tmp)); \
108 } while(0)
109#define STOP_MAC_MODE_EVENT do{ \
110 kal_uint32 tmp; \
111 tmp = DRV_Reg32(BSI_MAC_CTRL_REG); \
112 DRV_WriteReg32(BSI_MAC_CTRL_REG,(BSI_MAC_STOP | tmp)); \
113 } while(0)
114#define SET_BSI_MAC_CS_SEL(_cs) do{ \
115 kal_uint32 tmp; \
116 tmp = DRV_Reg32(BSI_MAC_CTRL_REG); \
117 if ( _cs == 0 ) \
118 DRV_WriteReg32(BSI_MAC_CTRL_REG, ((~(_cs << BSI_MAC_CS_SEL_BIT_OFFSET)) & tmp)); \
119 else if ( _cs == 1 ) \
120 DRV_WriteReg32(BSI_MAC_CTRL_REG, ((_cs << BSI_MAC_CS_SEL_BIT_OFFSET) | tmp)); \
121 else \
122 ASSERT(0); \
123 } while(0)
124#define SET_BSI_MAC_PORT_SEL(_port) do{ \
125 kal_uint32 tmp; \
126 tmp = DRV_Reg32(BSI_MAC_CTRL_REG); \
127 DRV_WriteReg32(BSI_MAC_CTRL_REG, ((_port << BSI_MAC_PORT_SEL_BIT_OFFSET) | tmp)); \
128 } while(0)
129#define ENABLE_BSI_MAC_RDINT do{ \
130 kal_uint32 tmp; \
131 tmp = DRV_Reg32(BSI_MAC_RDINT_REG); \
132 DRV_WriteReg32(BSI_MAC_RDINT_REG, (BSI_MAC_RDINT_EN | tmp)); \
133 } while(0)
134#define DISABLE_BSI_MAC_RDINT do{ \
135 kal_uint32 tmp; \
136 tmp = DRV_Reg32(BSI_MAC_RDINT_REG); \
137 DRV_WriteReg32(BSI_MAC_RDINT_REG, ((~BSI_MAC_RDINT_EN) & tmp)); \
138 } while(0)
139#define CLEAR_MAC_RDINT_STS do{ \
140 kal_uint32 tmp; \
141 tmp = DRV_Reg32(BSI_MAC_RDINT_REG); \
142 DRV_WriteReg32(BSI_MAC_RDINT_REG, (BSI_MAC_RDINT_STS_BIT | tmp)); \
143 } while(0)
144// BSICTRL IMM
145#define BSI_IMM_STOP (1UL << 0)
146#define BSI_IMM_RD_EN (1UL << 4)
147
148#define BSI_IMM_RD_EN_BIT_OFFSET (4)
149#define BSI_IMM_STATUS_BIT_OFFSET (8)
150#define BSI_IMM_CS_SEL_BIT_OFFSET (12)
151#define BSI_IMM_PORT_SEL_BIT_OFFSET (13)
152
153#define BSI_IMM_RD_EN_MASK (0x00000010)
154#define BSI_IMM_CS_SEL_MASK (0x00001000)
155#define BSI_IMM_PORT_SEL_MASK (0x0000E000)
156
157#define BSI_IMM_RDINT_STS_BIT (1UL << 0)
158#define BSI_IMM_RDINT_EN (1UL << 8)
159
160#define BSI_IMM_RDATA_3532_OFFSET (0)
161#define BSI_IMM_RDATA_3532_MASK (0xF << BSI_IMM_RDATA_3532_OFFSET)
162
163
164#define SET_BSI_IMM_CTRL(_port, _cs, _op) \
165 do{ \
166 kal_uint32 tmp; \
167 tmp = (DRV_Reg32(BSI_APB2CRF_IMM_CTRL_REG) & (~(BSI_IMM_RD_EN_MASK | BSI_IMM_CS_SEL_MASK | BSI_IMM_PORT_SEL_MASK))); \
168 DRV_WriteReg32(BSI_APB2CRF_IMM_CTRL_REG, (tmp | (_port << BSI_IMM_PORT_SEL_BIT_OFFSET) | (_cs << BSI_IMM_CS_SEL_BIT_OFFSET) | (_op << BSI_IMM_RD_EN_BIT_OFFSET)) ); \
169 } while(0)
170#define SET_BSI_IMM_READ_EVENT do{ \
171 kal_uint32 tmp; \
172 tmp = DRV_Reg32(BSI_APB2CRF_IMM_CTRL_REG); \
173 DRV_WriteReg32(BSI_APB2CRF_IMM_CTRL_REG, (BSI_IMM_RD_EN | tmp)); \
174 } while(0)
175#define SET_BSI_IMM_WRITE_EVENT do{ \
176 kal_uint32 tmp; \
177 tmp = DRV_Reg32(BSI_APB2CRF_IMM_CTRL_REG); \
178 DRV_WriteReg32(BSI_APB2CRF_IMM_CTRL_REG, ((~BSI_IMM_RD_EN) & tmp)); \
179 } while(0)
180#define STOP_IMM_MODE_EVENT do{ \
181 kal_uint32 tmp; \
182 tmp = DRV_Reg32(BSI_APB2CRF_IMM_CTRL_REG); \
183 DRV_WriteReg32(BSI_APB2CRF_IMM_CTRL_REG,(BSI_IMM_STOP | tmp)); \
184 } while(0)
185#define SET_BSI_IMM_CS_SEL(_cs) do{ \
186 kal_uint32 tmp; \
187 tmp = DRV_Reg32(BSI_APB2CRF_IMM_CTRL_REG); \
188 if ( _cs == 0 ) \
189 DRV_WriteReg32(BSI_APB2CRF_IMM_CTRL_REG, ((~(_cs << BSI_IMM_CS_SEL_BIT_OFFSET)) & tmp)); \
190 else if ( _cs == 1 ) \
191 DRV_WriteReg32(BSI_APB2CRF_IMM_CTRL_REG, ((_cs << BSI_IMM_CS_SEL_BIT_OFFSET) | tmp)); \
192 else \
193 ASSERT(0); \
194 } while(0)
195#define SET_BSI_IMM_PORT_SEL(_port) do{ \
196 kal_uint32 tmp; \
197 tmp = DRV_Reg32(BSI_APB2CRF_IMM_CTRL_REG); \
198 DRV_WriteReg32(BSI_APB2CRF_IMM_CTRL_REG, ((_port << BSI_IMM_PORT_SEL_BIT_OFFSET) | tmp)); \
199 } while(0)
200#define ENABLE_BSI_IMM_RDINT do{ \
201 kal_uint32 tmp; \
202 tmp = DRV_Reg32(BSI_APB2CRF_IMM_RDINT_REG); \
203 DRV_WriteReg32(BSI_APB2CRF_IMM_RDINT_REG, (BSI_IMM_RDINT_EN | tmp)); \
204 } while(0)
205#define DISABLE_BSI_IMM_RDINT do{ \
206 kal_uint32 tmp; \
207 tmp = DRV_Reg32(BSI_APB2CRF_IMM_RDINT_REG); \
208 DRV_WriteReg32(BSI_APB2CRF_IMM_RDINT_REG, ((~BSI_IMM_RDINT_EN) & tmp)); \
209 } while(0)
210#define CLEAR_IMM_RDINT_STS do{ \
211 kal_uint32 tmp; \
212 tmp = DRV_Reg32(BSI_APB2CRF_IMM_RDINT_REG); \
213 DRV_WriteReg32(BSI_APB2CRF_IMM_RDINT_REG, (BSI_IMM_RDINT_STS_BIT | tmp)); \
214 } while(0)
215
216typedef enum
217{
218 BSI_WRITE_EVENT = 0,
219 BSI_READ_EVENT = 1
220}BSI_EVENT_TYPE;
221
222
223// BSISPI CTRL
224// BSISPI_PORT_PARAM_REG:
225#define BSISPI_MIPI_EN_OFFSET (0)
226#define BSISPI_BSI_MODE_OFFSET (1)
227#define BSISPI_SINGLE_DIR_OFFSET (3)
228#define BSISPI_CLSNINT_EN_OFFSET (4)
229#define BSISPI_DBG_EN_OFFSET (5)
230#define BSISPI_READ_PHASE_OFFSET (6)
231#define BSISPI_RESET_MODE_OFFSET (8)
232#define BSISPI_IO_MODE_OFFSET (16)
233#define BSISPI_SW_CS_SEL_OFFSET (17)
234
235#define BSISPI_MIPI_EN_MASK (0x00000001)
236#define BSISPI_BSI_MODE_MASK (0x00000006)
237#define BSISPI_SINGLE_DIR_MASK (0x00000008)
238#define BSISPI_CLSNINT_EN_MASK (0x00000010)
239#define BSISPI_DBG_EN_MASK (0x00000020)
240#define BSISPI_READ_PHASE_MASK (0x000000C0)
241#define BSISPI_RESET_MODE_MASK (0x00000100)
242#define BSISPI_IO_MODE_MASK (0x00010000)
243#define BSISPI_SW_CS_SEL_MASK (0x00020000)
244
245// BSISPI_ICx_PARAM1_REG:
246#define BSISPI_CLK_POL_OFFSET (0)
247#define BSISPI_CLK_SPD_OFFSET (2)
248#define BSISPI_CS_LEN_OFFSET (5)
249#define BSISPI_CS_POL_OFFSET (7)
250#define BSISPI_RD_CLK_SPD_OFFSET (8)
251#define BSISPI_RD_TRANS_CLKON_OFFSET (11)
252#define BSISPI_RD_TRANS_LEN_OFFSET (12)
253#define BSISPI_IDLE_CNT_OFFSET (16)
254#define BSISPI_WLEN_OFFSET (24)
255
256#define BSISPI_CLK_POL_MASK (0x00000003)
257#define BSISPI_CLK_SPD_MASK (0x0000001C)
258#define BSISPI_CS_LEN_MASK (0x00000060)
259#define BSISPI_CS_POL_MASK (0x00000080)
260#define BSISPI_RD_CLK_SPD_MASK (0x00000700)
261#define BSISPI_RD_TRANS_CLKON_MASK (0x00000800)
262#define BSISPI_RD_TRANS_LEN_MASK (0x0000F000)
263#define BSISPI_IDLE_CNT_MASK (0x001F0000)
264#define BSISPI_WLEN_MASK (0x1F000000)
265
266// BSISPI_ICx_PARAM2_REG:
267#define BSISPI_RD_TRANS_CS_WAVEFORM_OFFSET (0)
268#define BSISPI_RD_RDATA_CS_POL_OFFSET (15)
269#define BSISPI_RD_WLEN_OFFSET (16)
270#define BSISPI_RD_RLEN_OFFSET (24)
271
272#define BSISPI_RD_TRANS_CS_WAVEFORM_MASK (0x00007FFF)
273#define BSISPI_RD_RDATA_CS_POL_MASK (0x00008000)
274#define BSISPI_RD_WLEN_MASK (0x001F0000)
275#define BSISPI_RD_RLEN_MASK (0x3F000000)
276
277typedef enum
278{
279 BSISPI_READ_PHASE0 = 0,
280 BSISPI_READ_PHASE1 = 1,
281 BSISPI_READ_PHASE2 = 2,
282 BSISPI_READ_PHASE3 = 3
283}BSISPI_READ_PHASE_TYPE;
284
285typedef enum
286{
287 BSISPI_1BIT_PER_CYCLE = 0,
288 BSISPI_2BIT_PER_CYCLE = 1,
289 BSISPI_3BIT_PER_CYCLE = 2,
290 BSISPI_BSI_MODE_RESERVED = 3
291}BSISPI_BSI_MODE_TYPE;
292
293#define BSISPI_RD_TRANS_CLKON (0x1)
294#define BSISPI_CS_POL_INV_EN (0x1)
295
296typedef enum
297{
298 BSISPI_LONG_PULSE = 0,
299 BSISPI_SHORT_PULSE = 1,
300 BSISPI_LONG_PULSE_ALIGN = 2,
301 BSISPI_CS_SHAPE_RESEVED = 3
302}BSISPI_CS_SHAPE_TYPE;
303
304typedef enum
305{
306 BSISPI_CLK_DIV2 = 0,
307 BSISPI_CLK_DIV4 = 1,
308 BSISPI_CLK_DIV6 = 2,
309 BSISPI_CLK_DIV8 = 3,
310 BSISPI_CLK_DIV12 = 4,
311 BSISPI_CLK_DIV16 = 5,
312 BSISPI_CLK_DIV24 = 6,
313 BSISPI_CLK_DIV32 = 7
314}BSISPI_CLK_SPD_TYPE;
315
316typedef enum
317{
318 BSISPI_TRUE_CLK_POL = 0,
319 BSISPI_INV_CLK_POL = 1,
320 BSISPI_TRUE_CLK_POL_PRE_PULSE = 2,
321 BSISPI_INV_CLK_POL_PRE_PULSE = 3
322}BSISPI_CLK_POL_TYPE;
323
324#define BSISPI_RD_RDATA_CS_POL_HIGH (0x1)
325
326// BSICTRL Operations
327#define GET_BSI_MAC_STATUS() ((DRV_Reg32(BSI_MAC_CTRL_REG) >> BSI_MAC_STATUS_BIT_OFFSET) & 0x1)
328#define SET_BSI_MAC_WRITE_DATA(_wdata) DRV_WriteReg32(BSI_MAC_WDATA_REG, _wdata)
329#define GET_BSI_MAC_RD_INT_STATUS() ((DRV_Reg32(BSI_MAC_RDINT_REG) & BSI_MAC_RDINT_STS_BIT) >> 0)
330#define GET_BSI_MAC_READ_DATA_3100() DRV_Reg32(BSI_MAC_RDATA_3100_REG)
331#define GET_BSI_MAC_READ_DATA_3532() DRV_Reg32(BSI_MAC_RDATA_3532_REG)
332#define GET_BSI_MAC_READ_DATA() ((DRV_Reg32(BSI_MAC_RDATA_3532_REG) << 32) | DRV_Reg32(BSI_MAC_RDATA_3100_REG))
333
334#define GET_BSI_IMM_STATUS() ((DRV_Reg32(BSI_APB2CRF_IMM_CTRL_REG) >> BSI_IMM_STATUS_BIT_OFFSET) & 0x1)
335#define SET_BSI_IMM_WRITE_DATA(_wdata) DRV_WriteReg32(BSI_APB2CRF_IMM_WDATA_REG, _wdata)
336#define GET_BSI_IMM_RD_INT_STATUS() ((DRV_Reg32(BSI_APB2CRF_IMM_RDINT_REG) & BSI_IMM_RDINT_STS_BIT) >> 0)
337#define GET_BSI_IMM_READ_DATA_3100() DRV_Reg32(BSI_APB2CRF_IMM_RDATA_3100_REG)
338#define GET_BSI_IMM_READ_DATA_3532() DRV_Reg32(BSI_APB2CRF_IMM_RDATA_3532_REG)
339#define GET_BSI_IMM_READ_DATA() ((DRV_Reg32(BSI_APB2CRF_IMM_RDATA_3532_REG) << 32) | DRV_Reg32(BSI_APB2CRF_IMM_RDATA_3100_REG))
340
341
342/*****************************************************************************
343 * function declaration *
344 *****************************************************************************/
345/*-----------------------------------------------------------------------*
346* FUNCTION
347* drv_bsi_pmic_init
348*
349* DESCRIPTION
350* This function is to initialize BSI SPI controller for PMIC.
351*
352* PARAMETERS
353* None.
354*
355* RETURNS
356* None.
357*
358*------------------------------------------------------------------------*/
359extern void drv_bsi_pmic_init(void);
360
361/*-----------------------------------------------------------------------*
362* FUNCTION
363* drv_bsi_pmic6339_reg_write
364*
365* DESCRIPTION
366* This function is to write MT6339 PMIC register through BSI.
367*
368* PARAMETERS
369* reg - MT6339 PMIC register address. (8 bits)
370* val - data to be written into MT6339 PMIC address. (16 bits)
371*
372* RETURNS
373* None
374*
375*------------------------------------------------------------------------*/
376extern void drv_bsi_pmic6339_reg_write(kal_uint8 reg, kal_uint16 val);
377
378/*-----------------------------------------------------------------------*
379* FUNCTION
380* drv_bsi_pmic6339_reg_failWrite
381* (Only for BSI reset testing, not for normal use)
382*
383* DESCRIPTION
384* This function is to write MT6339 PMIC register through BSI
385* with incorrect number of transfer bits.
386*
387* PARAMETERS
388* reg - MT6339 PMIC register address. (8 bits)
389* val - data to be written into MT6339 PMIC address. (16 bits)
390*
391* RETURNS
392* None
393*
394*------------------------------------------------------------------------*/
395extern void drv_bsi_pmic6339_reg_failWrite(kal_uint8 reg, kal_uint16 val);
396
397/*-----------------------------------------------------------------------*
398* FUNCTION
399* drv_bsi_pmic6339_reg_read
400*
401* DESCRIPTION
402* This function is to read MT6339 PMIC register through BSI.
403*
404* PARAMETERS
405* reg - MT6339 PMIC register address. (8 bits)
406*
407* RETURNS
408* value which from MT6339 PMIC address. (16 bits)
409*
410*------------------------------------------------------------------------*/
411extern kal_uint16 drv_bsi_pmic6339_reg_read(kal_uint8 reg);
412
413/*-----------------------------------------------------------------------*
414* FUNCTION
415* drv_bsi_a60386_reg_write
416*
417* DESCRIPTION
418* This function is to write A60386 register through BSI.
419*
420* PARAMETERS
421* reg - A60386 register address. (12 bits)
422* val - data to be written into A60386 address. (16 bits)
423*
424* RETURNS
425* None
426*
427*------------------------------------------------------------------------*/
428extern void drv_bsi_a60386_reg_write(kal_uint16 reg, kal_uint16 val);
429
430/*-----------------------------------------------------------------------*
431* FUNCTION
432* drv_bsi_a60386_reg_read
433*
434* DESCRIPTION
435* This function is to read A60386 register through BSI.
436*
437* PARAMETERS
438* reg - A60386 register address. (12 bits)
439*
440* RETURNS
441* value which from A60386 address. (16 bits)
442*
443*------------------------------------------------------------------------*/
444extern kal_uint16 drv_bsi_a60386_reg_read(kal_uint16 reg);
445
446
447#endif /* end of __DRV_BSI_H__ */