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192.168.1.100 / T800_MD / 1eb8f53f94c145708b5ea2c6b9b96ea3d613f607 / . / mcu / driver / devdrv / btdma / src / btdma.c
blob: 352738a5d6f0885571f824af35ad08d79d0bdf2f [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1#include <stdio.h>
2#include "drv_comm.h"
3#include "btdma_public.h"
4#include "btdma_private.h"
5//#include "spinlock_hw_public.h"
6#include "intrCtrl.h"
7
8
9#define LSB_DIR_ONE(input,output)\
10 output = __builtin_ctz(input)
11
12#define BTDMA_REG32(addr) (*((volatile btdma_uint32 *)(addr)))
13#define BTDMA_ASSERT()
14
15
16
17#undef BTDMA_CALLBACK_REGISTER
18#define BTDMA_CALLBACK_REGISTER(KEY,CALLBACK) extern void CALLBACK(void);
19#include "btdma_callback_reg.h"
20#undef BTDMA_CALLBACK_REGISTER
21
22
23#define cc_spinlock_hw_take_lock(resource)
24#define cc_spinlock_hw_give_lock(resource)
25typedef void (*btdma_callback_type)(void);
26
27
28
29#if 0
30/* under construction !*/
31/* under construction !*/
32/* under construction !*/
33/* under construction !*/
34/* under construction !*/
35/* under construction !*/
36/* under construction !*/
37/* under construction !*/
38/* under construction !*/
39/* under construction !*/
40/* under construction !*/
41#if defined(__BTDMA_DRIVER_TEST__)
42/* under construction !*/
43#endif
44#endif
45
46
47btdma_callback_type btdma_callback[] = {
48#undef BTDMA_CALLBACK_REGISTER
49#define BTDMA_CALLBACK_REGISTER(KEY,CALLBACK) CALLBACK,
50#include "btdma_callback_reg.h"
51#undef BTDMA_CALLBACK_REGISTER
52 0
53};
54
55
56void BTDMA_Interrupt_Handler(kal_uint32 irq_id);
57void BTDMA_Exception_Handler(kal_uint32 irq_id){
58EXT_ASSERT(0, 0, 0, 0);
59}
60
61
62static inline void BTDMA_MPU_AXI_Set(btdma_uint32 channel,
63 btdma_uint32 start_address,
64 btdma_uint32 end_address)
65{
66 DRV_WriteReg32(BTDMA_MPU_REGION_AXI_START_ADDR + channel * 4 ,start_address);
67 DRV_WriteReg32(BTDMA_MPU_REGION_AXI_END_ADDR + channel * 4 ,end_address);
68 DRV_WriteReg32(BTDMA_MPU_ENABLE_ADDR ,(DRV_Reg32(BTDMA_MPU_ENABLE_ADDR)) |(1 << channel));
69
70}
71
72
73static inline void BTDMA_MPU_DBUS_Set(btdma_uint32 channel,
74 btdma_uint32 start_address,
75 btdma_uint32 end_address)
76{
77 DRV_WriteReg32(BTDMA_MPU_REGION_DBUS_START_ADDR + channel * 4 ,start_address);
78 DRV_WriteReg32(BTDMA_MPU_REGION_DBUS_END_ADDR + channel * 4 ,end_address);
79
80#if !defined(MT6297)//defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833)
81 DRV_WriteReg32(BTDMA_MPU_TYPE_ADDR ,(DRV_Reg32(BTDMA_MPU_TYPE_ADDR)) |(1 << (channel+BTDMA_MPU_AXI_CHANNEL_NUM)));
82#endif
83
84 DRV_WriteReg32(BTDMA_MPU_ENABLE_ADDR ,(DRV_Reg32(BTDMA_MPU_ENABLE_ADDR)) |(1 << (channel+BTDMA_MPU_AXI_CHANNEL_NUM)));
85
86
87}
88
89void BTDMA_MPU_EMI_Region_Set(btdma_uint32 start_address,btdma_uint32 end_address)
90{
91 BTDMA_MPU_AXI_Set(0,start_address,end_address);
92}
93
94
95void BTDMA_interrupt_register()
96{
97 //IRQ_Register_LISR(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE, BTDMA_Interrupt_Handler, "btdma");
98 //IRQSensitivity(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE, LEVEL_SENSITIVE);
99 IRQUnmask(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE);
100}
101
102void BTDMA_exception_register()
103{
104 //IRQ_Register_LISR(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE, BTDMA_Exception_Handler, "btdma_exception");
105 //IRQSensitivity(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE, LEVEL_SENSITIVE);
106 IRQUnmask(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE);
107}
108
109void BTDMA_Init()
110{
111
112 BTDMA_interrupt_register();
113 BTDMA_exception_register();
114
115#if defined(__MD97P__)
116 BTDMA_MPU_AXI_Set(1,BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM,BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM+0X600000);
117 BTDMA_MPU_DBUS_Set(0,BASE_MADDR_VCORE_THREAD0_ICM,BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM);
118 BTDMA_MPU_DBUS_Set(1,BASE_MADDR_MCORE_MSYS_DSPCBSCHEDULER,BASE_MADDR_VCORE_THREAD0_ICM);
119#else
120 BTDMA_MPU_AXI_Set(1,BASE_MADDR_HRAM_MML1_HRAM_BRICK,BASE_MADDR_HRAM_MML1_HRAM_BRICK+0X600000);
121 BTDMA_MPU_DBUS_Set(0,BASE_MADDR_VCORE_THREAD0_LOCAL_ICM,BASE_MADDR_HRAM_MML1_HRAM_BRICK);
122 BTDMA_MPU_DBUS_Set(1,BASE_MADDR_MCORE0_CBSCHEDULER,BASE_MADDR_VCORE_TH0_L1MC__CR);
123#endif
124}
125
126
127#if 0
128/* under construction !*/
129/* under construction !*/
130/* under construction !*/
131/* under construction !*/
132/* under construction !*/
133/* under construction !*/
134/* under construction !*/
135/* under construction !*/
136/* under construction !*/
137/* under construction !*/
138/* under construction !*/
139/* under construction !*/
140/* under construction !*/
141/* under construction !*/
142/* under construction !*/
143/* under construction !*/
144/* under construction !*/
145/* under construction !*/
146/* under construction !*/
147/* under construction !*/
148/* under construction !*/
149/* under construction !*/
150/* under construction !*/
151/* under construction !*/
152/* under construction !*/
153/* under construction !*/
154/* under construction !*/
155#endif
156
157void SS_BTDMA_Trigger(btdma_description* desc,
158 btdma_priority_chain priority,
159 btdma_callback_index callback_key)
160{
161 desc[0].callback_key = callback_key;
162 DRV_WriteReg32(BTDMA_DESC_CTRL_0_PRI0_START_ADDR + priority * 4, (btdma_uint32)desc);
163 DRV_WriteReg32(BTDMA_DESC_CTRL_0_PRI0_TRIG_ADDR + priority * 4, 0x1);
164}
165
166
167void BTDMA_Polling_Priority_idle(btdma_uint32 priority)
168{
169 kal_uint32 volatile status = DRV_Reg32(BTDMA_BASE_ADDR + BTDMA_DESC_STS_4_OFFSET+ priority * 4);
170 status = status >> BTDMA_DESC_STS_4_CMD_STS_POS;
171
172 while(status !=0){
173 status = (DRV_Reg32(BTDMA_BASE_ADDR + BTDMA_DESC_STS_4_OFFSET+ priority * 4))>> BTDMA_DESC_STS_4_CMD_STS_POS;
174 }
175}
176
177#if 0
178/* under construction !*/
179/* under construction !*/
180/* under construction !*/
181/* under construction !*/
182/* under construction !*/
183/* under construction !*/
184/* under construction !*/
185/* under construction !*/
186/* under construction !*/
187/* under construction !*/
188/* under construction !*/
189/* under construction !*/
190/* under construction !*/
191/* under construction !*/
192/* under construction !*/
193/* under construction !*/
194/* under construction !*/
195/* under construction !*/
196/* under construction !*/
197/* under construction !*/
198/* under construction !*/
199/* under construction !*/
200/* under construction !*/
201/* under construction !*/
202/* under construction !*/
203/* under construction !*/
204/* under construction !*/
205/* under construction !*/
206/* under construction !*/
207/* under construction !*/
208/* under construction !*/
209/* under construction !*/
210/* under construction !*/
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212/* under construction !*/
213/* under construction !*/
214/* under construction !*/
215/* under construction !*/
216/* under construction !*/
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218/* under construction !*/
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220/* under construction !*/
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223/* under construction !*/
224/* under construction !*/
225/* under construction !*/
226/* under construction !*/
227/* under construction !*/
228/* under construction !*/
229/* under construction !*/
230/* under construction !*/
231/* under construction !*/
232/* under construction !*/
233#endif
234
235void BTDMA_Interrupt_Handler(kal_uint32 irq_id)
236{
237 btdma_uint32 signal_status = BTDMA_REG32(BTDMA_INTERRUPT_STS_ADDR);
238 btdma_uint32 trigger_priority = 0;
239 //LSB_DIR_ONE(signal_status,trigger_priority);
240
241 trigger_priority = __builtin_ctz(signal_status);
242
243
244 while(trigger_priority < BTDMA_PRIO_CHAIN_NUM && signal_status != 0){
245
246 btdma_description* desc = (btdma_description*)DRV_Reg32(DRV_Reg32(BTDMA_DESC_CTRL_0_PRI0_START_ADDR + trigger_priority * 4));
247 btdma_uint32 callback_key = (btdma_uint32)(*desc).callback_key;
248
249 DRV_WriteReg32(BTDMA_INTERRUPT_STS_ADDR,1 <<trigger_priority);
250
251
252 //call user callback
253 (*btdma_callback[callback_key])();
254
255 signal_status = BTDMA_REG32(BTDMA_INTERRUPT_STS_ADDR);
256
257 //LSB_DIR_ONE(signal_status,trigger_priority);
258 trigger_priority = __builtin_ctz(signal_status);
259
260 }
261}
262
263
264#if 0
265/* under construction !*/
266/* under construction !*/
267/* under construction !*/
268/* under construction !*/
269/* under construction !*/
270/* under construction !*/
271/* under construction !*/
272/* under construction !*/
273/* under construction !*/
274/* under construction !*/
275/* under construction !*/
276/* under construction !*/
277/* under construction !*/
278/* under construction !*/
279/* under construction !*/
280/* under construction !*/
281/* under construction !*/
282/* under construction !*/
283/* under construction !*/
284/* under construction !*/
285/* under construction !*/
286/* under construction !*/
287/* under construction !*/
288/* under construction !*/
289/* under construction !*/
290/* under construction !*/
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292/* under construction !*/
293/* under construction !*/
294/* under construction !*/
295/* under construction !*/
296/* under construction !*/
297/* under construction !*/
298/* under construction !*/
299/* under construction !*/
300/* under construction !*/
301/* under construction !*/
302/* under construction !*/
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304/* under construction !*/
305/* under construction !*/
306/* under construction !*/
307/* under construction !*/
308/* under construction !*/
309/* under construction !*/
310/* under construction !*/
311/* under construction !*/
312/* under construction !*/
313/* under construction !*/
314/* under construction !*/
315/* under construction !*/
316/* under construction !*/
317/* under construction !*/
318/* under construction !*/
319/* under construction !*/
320/* under construction !*/
321/* under construction !*/
322/* under construction !*/
323/* under construction !*/
324/* under construction !*/
325/* under construction !*/
326/* under construction !*/
327/* under construction !*/
328/* under construction !*/
329/* under construction !*/
330/* under construction !*/
331/* under construction !*/
332/* under construction !*/
333/* under construction !*/
334/* under construction !*/
335/* under construction !*/
336/* under construction !*/
337/* under construction !*/
338/* under construction !*/
339/* under construction !*/
340/* under construction !*/
341/* under construction !*/
342/* under construction !*/
343/* under construction !*/
344/* under construction !*/
345/* under construction !*/
346#endif
347
348
349void BTDMA_SW_Enable_Ungate_Signal(btdma_core core)
350{
351 btdma_uint32 temp;
352
353 temp = BTDMA_REG32(BTDMA_SIGNAL_CTRL0_ADDR);
354 DRV_WriteReg32(BTDMA_SIGNAL_CTRL0_ADDR,temp | (1 << core));
355 MO_Sync();
356
357}
358
359void BTDMA_SW_Disable_Ungate_Signal(btdma_core core)
360{
361 btdma_uint32 temp;
362
363 temp = BTDMA_REG32(BTDMA_SIGNAL_CTRL0_ADDR);
364 DRV_WriteReg32(BTDMA_SIGNAL_CTRL0_ADDR,temp & ~(1 << core));
365 MO_Sync();
366}
367
368void BTDMA_Debug_Dump()
369{
370
371}