mcu/driver/devdrv/pcie/src/pcie.c

/*****************************************************************************
*  Copyright Statement:
*  --------------------
*  This software is protected by Copyright and the information contained
*  herein is confidential. The software may not be copied and the information
*  contained herein may not be used or disclosed except with the written
*  permission of MediaTek Inc. (C) 2012
*
*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
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*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
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*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
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*****************************************************************************/

/*******************************************************************************
 * Filename:
 * ---------
 *   pcie.c
 *
 * Project:
 * --------
 *   VMOLY
 *
 * Description:
 * ------------
 *  PCIE device driver
 *
 * Author:
 * -------
 * -------
 *
 * ==========================================================================
 * $Log$
 *
 * 11 11 2020 cindy.tu
 * [MOLY00520457] [PCIE][Colgin] PCIE driver
 *
 * 11 11 2020 cindy.tu
 * [MOLY00520457] [PCIE][Colgin] PCIE driver
 * 	
 * 	Sync to MD700.
 *
 * 11 09 2020 cindy.tu
 * [MOLY00591928] [MT6880][Colgin][PCIE][RDIT]Potential race condition in PERST interrupt handing flow
 *
 * 10 09 2020 cindy.tu
 * [MOLY00579078] [MT6880][Colgin][M.2][Low Power] Colgin Data Card(連 RVP) Flight mode suspend current: 4.3 mA  > target 4.1 mA
 * 	
 * 	.
 *
 * 09 28 2020 cindy.tu
 * [MOLY00573840] [MT6880][Colgin][M.2][Low Power] Colgin Data Card(連 RVP) Flight mode suspend current: 5.6 mA  > target 4.2 mA
 *
 * 09 03 2020 cindy.tu
 * [MOLY00520457] [PCIE][Colgin] PCIE driver
 * 	
 * Update L2 flow
 *
 * 08 19 2020 cody.lee
 * [MOLY00557699] [Colgin] MTCMOS CTRL API - bus protection fix
 * + SRAM chain
 *
 * 08 04 2020 cindy.tu
 * [MOLY00520457] [PCIE][Colgin] PCIE driver
 * 	
 * Merge PCIE driver to T700 branch
 *
 * 07 13 2020 cody.lee
 * [MOLY00545672] [Colgin] PCIE MTCMOS CTRL API
 *
 * 07 06 2020 cindy.tu
 * [MOLY00520457] [PCIE][Colgin] PCIE driver
 * 	
 * 	Sync PCIE to MT6880 MP.
 *
 * 05 27 2020 cindy.tu
 * [MOLY00520457] [PCIE][Colgin] PCIE driver
 * 	
 * Fix build error.
 *
 * 05 05 2020 cindy.tu
 * [MOLY00520457] [PCIE][Colgin] PCIE driver
 *
 * 04 30 2020 cindy.tu
 * [MOLY00518788] [PCIE][Mercury] PCIE link API
 * 	EWSP0000108141
 *
 * 04 16 2020 cindy.tu
 * [MOLY00503259] [PCIE][M70] PCIE link API
 * 
 * [PCIE] Integrate with MHCCIF and add test cases.
 *
 * 03 05 2020 cindy.tu
 * [MOLY00503259] [PCIE][M70] PCIE link API
 * 	
 * 	[SWRD]M70 PCIE.
 *
 *
 ****************************************************************************/

#include "kal_public_api.h"
#include "drv_comm.h"
#include "pcie_if.h"
#include "pcie_mac.h"
#include "pcie_dbg.h"
#include "pcie.h"

#define STA_POWER_ON    1
#define STA_POWER_DOWN  0

/* Define MTCMOS Power Status Mask */
#define PCIE_PWR_STA_MASK                (0x1 << 10)
#define MCUSYS_SPMC_PWR_STA_MASK         (0x1 << 14)

/* Define MTCMOS Bus Protect Mask */
#define PCIE_PROT_STEP1_0_MASK           ((0x1 << 6) \
					  |(0x1 << 17) \
					  |(0x1 << 18))
#define PCIE_PROT_STEP1_0_ACK_MASK       ((0x1 << 6) \
					  |(0x1 << 17) \
					  |(0x1 << 18))
#define PCIE_PROT_STEP2_0_MASK           ((0x1 << 16) \
					  |(0x1 << 19) \
					  |(0x1 << 20) \
					  |(0x1 << 24))
#define PCIE_PROT_STEP2_0_ACK_MASK       ((0x1 << 16) \
					  |(0x1 << 19) \
					  |(0x1 << 20) \
					  |(0x1 << 24))

#define PCIE_SW_CG_1			((0x1 << 15) | (0x1 <<18) | (0x1 << 19))
#define PCIE_SW_CG_3			((0x1 <<15) | (0x1 << 27))
#define PCIE_SW_CG_4			((0x1 << 13) | (0x1 << 22) | (0x1 <<23) | (0x1 << 24))	

/* Define Non-CPU SRAM Mask */
#define MD1_SRAM_PDN                     (0x1 << 8)         //MD1_PWR_CON 0x300   //PCIE_SRAM_PDN
#define MD1_SRAM_PDN_ACK                 (0x0 << 12)        //PCIE_SRAM_PDN_ACK
#define MD1_SRAM_PDN_ACK_BIT0            (0x1 << 12)        //PCIE_SRAM_PDN_ACK_BIT0

#define PEXTP_D_2LX1_PWR_ACK_IDX         12
#define PEXTP_D_2LX1_PHY_PWR_ACK_IDX     3

/* Define MTCMOS power control */
#define PWR_RST_B                        (0x1 << 0)
#define PWR_ISO                          (0x1 << 1)
#define PWR_ON                           (0x1 << 2)
#define PWR_ON_2ND                       (0x1 << 3)
#define PWR_CLK_DIS                      (0x1 << 4)
#define SRAM_PD_OFFSET                   (0x1 << 8)
#define SRAM_PD_ACK_OFFSET               (0x1 << 12)

#ifdef CHIP10992
#define SPM_BASE                       (BASE_INFRA_AO_SLEEP_CTRL)
#else
#define SPM_BASE                       0
#endif
#define POWERON_CONFIG_EN              (SPM_BASE + 0x0000)
#define PWR_STATUS                     (SPM_BASE + 0x016C)
#define PWR_STATUS_2ND                 (SPM_BASE + 0x0170)
#define MCUPM_PWR_CON                  (SPM_BASE + 0x03C0)         //PCIE_PWR_CON

#define PEXTP_D_2LX1_PWR_CON            (SPM_BASE + 0x330)
#define PEXTP_D_2LX1_PHY_PWR_CON        (SPM_BASE + 0x30C)

#define SPM_PROJECT_CODE	0xb16
#define SPM_REGWR_CFG_KEY	(SPM_PROJECT_CODE << 16)

#define INFRA_TOPAXI_PROTECTEN_SET  (BASE_INFRA_AO_CONFIG + 0x02A0)
#define INFRA_TOPAXI_PROTECTEN_CLR  (BASE_INFRA_AO_CONFIG + 0x02A4)
#define INFRA_TOPAXI_PROTECTEN_STA1  (BASE_INFRA_AO_CONFIG + 0x0228)

#define INFRA_TOPAXI_PROTECTEN_1_SET (BASE_INFRA_AO_CONFIG + 0x2A8)
#define INFRA_TOPAXI_PROTECTEN_1_CLR  (BASE_INFRA_AO_CONFIG + 0x2AC)
#define INFRA_TOPAXI_PROTECTEN_STA1_1  (BASE_INFRA_AO_CONFIG + 0x258)

#define INFRA_TOPAXI_PROTECTEN_SET_2  (BASE_INFRA_AO_CONFIG + 0x714)
#define INFRA_TOPAXI_PROTECTEN_CLR_2  (BASE_INFRA_AO_CONFIG + 0x718)
#define INFRA_TOPAXI_PROTECTEN_STA1_2  (BASE_INFRA_AO_CONFIG + 0x724)

#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_SET  (BASE_INFRA_AO_CONFIG + 0xB84)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_CLR   (BASE_INFRA_AO_CONFIG + 0xB88)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA1  (BASE_INFRA_AO_CONFIG + 0xB90)

#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_SET_1  (BASE_INFRA_AO_CONFIG + 0xBA4)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_CLR_1  (BASE_INFRA_AO_CONFIG + 0xBA8)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA1_1  (BASE_INFRA_AO_CONFIG + 0xBB0)

#define INFRA_TOPAXI_PROTECTEN_MM_SET  (BASE_INFRA_AO_CONFIG + 0x2D4)
#define INFRA_TOPAXI_PROTECTEN_MM_CLR  (BASE_INFRA_AO_CONFIG + 0x2D8)
#define INFRA_TOPAXI_PROTECTEN_MM_STA1  (BASE_INFRA_AO_CONFIG + 0x2EC)

#define INFRA_TOPAXI_MODULE_SW_CG_1_SET  (BASE_INFRA_AO_CONFIG + 0x088)
#define INFRA_TOPAXI_MODULE_SW_CG_1_CLR  (BASE_INFRA_AO_CONFIG + 0x08C)
#define INFRA_TOPAXI_MODULE_SW_CG_3_SET  (BASE_INFRA_AO_CONFIG + 0x0C0)
#define INFRA_TOPAXI_MODULE_SW_CG_3_CLR  (BASE_INFRA_AO_CONFIG + 0x0C4)
#define INFRA_TOPAXI_MODULE_SW_CG_4_SET  (BASE_INFRA_AO_CONFIG + 0x0E0)
#define INFRA_TOPAXI_MODULE_SW_CG_4_CLR  (BASE_INFRA_AO_CONFIG + 0x0E4)

#define TOPRGU_WDT_SWSYSRST        (BASE_INFRA_AO_TOPRGU + 0x0018)

PCIE_detect_result_e g_pcie_detect_result = PCIE_LINK_UNKNOWN;

void spm_mtcmos_rsb_on(kal_uint32 reg_addr, int ack_index);
void spm_mtcmos_rsb_off(kal_uint32 reg_addr, int ack_index);

extern kal_uint32 g_ltssm;
extern kal_uint32 Plat_SW_Code(void);

#ifdef CHIP10992
void toprgu_ctrl_pcie_off(void)
{
	/* Set PCIE PHY ip+reset_mode */
	DRV_WriteReg32(TOPRGU_WDT_SWSYSRST, (DRV_Reg32(TOPRGU_WDT_SWSYSRST) & 0x00EFFFFF) | 0x88100000);    
}
#endif

#ifdef MT6298
void phy_ctrl_pcie_off(void) 
{
	DRV_WriteReg32(0xC1F80020, (DRV_Reg32(0xC1F80020) | 0x1) );
}
#endif

void spm_mtcmos_ctrl_pcie(int state)
{
	/* TINFO="enable SPM register control" */
	DRV_WriteReg32(POWERON_CONFIG_EN, (SPM_PROJECT_CODE << 16) | (0x1 << 0));

	if (state == STA_POWER_DOWN) {
		/* TINFO="Start to turn off PCIE" */
		/* TINFO="Set bus protect - step1 : 0" */
		DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_SET, PCIE_PROT_STEP1_0_MASK);
#ifndef IGNORE_MTCMOS_CHECK
		while ((DRV_Reg32(INFRA_TOPAXI_PROTECTEN_STA1) & PCIE_PROT_STEP1_0_ACK_MASK) != PCIE_PROT_STEP1_0_ACK_MASK) {
		}
#endif
		/* TINFO="Set bus protect - step2 : 0" */
		DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_SET, PCIE_PROT_STEP2_0_MASK);
#ifndef IGNORE_MTCMOS_CHECK
		while ((DRV_Reg32(INFRA_TOPAXI_PROTECTEN_STA1) & PCIE_PROT_STEP2_0_ACK_MASK) != PCIE_PROT_STEP2_0_ACK_MASK) {
		}
#endif
		/* TINFO="Set SRAM_PDN = 1" */
		DRV_WriteReg32(MCUPM_PWR_CON, DRV_Reg32(MCUPM_PWR_CON) | MD1_SRAM_PDN);
#ifndef IGNORE_MTCMOS_CHECK
		/* TINFO="Wait until MD1_SRAM_PDN_ACK = 1" */
		while ((DRV_Reg32(MCUPM_PWR_CON) & MD1_SRAM_PDN_ACK) != MD1_SRAM_PDN_ACK) {
				/* Need f_fsmi_ck for SRAM PDN delay IP. */
		}
#endif
		/* TINFO="Set PWR_ISO = 1" */
		DRV_WriteReg32(MCUPM_PWR_CON, DRV_Reg32(MCUPM_PWR_CON) | PWR_ISO);
		/* TINFO="Set PWR_CLK_DIS = 1" */
		DRV_WriteReg32(MCUPM_PWR_CON, DRV_Reg32(MCUPM_PWR_CON) | PWR_CLK_DIS);
		/* TINFO="Set PWR_RST_B = 0" */
		DRV_WriteReg32(MCUPM_PWR_CON, DRV_Reg32(MCUPM_PWR_CON) & ~PWR_RST_B);
		/* TINFO="Set PWR_ON = 0" */
		DRV_WriteReg32(MCUPM_PWR_CON, DRV_Reg32(MCUPM_PWR_CON) & ~PWR_ON);
		/* TINFO="Set PWR_ON_2ND = 0" */
		DRV_WriteReg32(MCUPM_PWR_CON, DRV_Reg32(MCUPM_PWR_CON) & ~PWR_ON_2ND);
#ifndef IGNORE_MTCMOS_CHECK
		/* TINFO="Wait until PWR_STATUS = 0 and PWR_STATUS_2ND = 0" */
		while ((DRV_Reg32(PWR_STATUS) & PCIE_PWR_STA_MASK)
		       || (DRV_Reg32(PWR_STATUS_2ND) & PCIE_PWR_STA_MASK)) {
				/* No logic between pwr_on and pwr_ack. Print SRAM / MTCMOS control and PWR_ACK for debug. */
		}
#endif
		/* TINFO="Finish to turn off PCIE" */
	} else {    /* STA_POWER_ON */
		/* TINFO="Start to turn on PCIE" */
		/* TINFO="Set PWR_ON = 1" */
		DRV_WriteReg32(MCUPM_PWR_CON, DRV_Reg32(MCUPM_PWR_CON) | PWR_ON);
		/* TINFO="Set PWR_ON_2ND = 1" */
		DRV_WriteReg32(MCUPM_PWR_CON, DRV_Reg32(MCUPM_PWR_CON) | PWR_ON_2ND);
#ifndef IGNORE_MTCMOS_CHECK
		/* TINFO="Wait until PWR_STATUS = 1 and PWR_STATUS_2ND = 1" */
		while (((DRV_Reg32(PWR_STATUS) & PCIE_PWR_STA_MASK) != PCIE_PWR_STA_MASK)
		       || ((DRV_Reg32(PWR_STATUS_2ND) & PCIE_PWR_STA_MASK) != PCIE_PWR_STA_MASK)) {
				/* No logic between pwr_on and pwr_ack. Print SRAM / MTCMOS control and PWR_ACK for debug. */
		}
#endif
		/* TINFO="Set PWR_CLK_DIS = 0" */
		DRV_WriteReg32(MCUPM_PWR_CON, DRV_Reg32(MCUPM_PWR_CON) & ~PWR_CLK_DIS);
		/* TINFO="Set PWR_ISO = 0" */
		DRV_WriteReg32(MCUPM_PWR_CON, DRV_Reg32(MCUPM_PWR_CON) & ~PWR_ISO);
		/* TINFO="Set PWR_RST_B = 1" */
		DRV_WriteReg32(MCUPM_PWR_CON, DRV_Reg32(MCUPM_PWR_CON) | PWR_RST_B);
		/* TINFO="Set SRAM_PDN = 0" */
		DRV_WriteReg32(MCUPM_PWR_CON, DRV_Reg32(MCUPM_PWR_CON) & ~(0x1 << 8));
#ifndef IGNORE_MTCMOS_CHECK
		/* TINFO="Wait until MD1_SRAM_PDN_ACK = 0" */
		while (DRV_Reg32(MCUPM_PWR_CON) & MD1_SRAM_PDN_ACK) {
				/* Need f_fsmi_ck for SRAM PDN delay IP. */
		}
#endif
		/* TINFO="Release bus protect - step2 : 0" */
		DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_CLR, PCIE_PROT_STEP2_0_MASK);
#ifndef IGNORE_MTCMOS_CHECK
		/* Note that this protect ack check after releasing protect has been ignored */
#endif
		/* TINFO="Release bus protect - step1 : 0" */
		DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_CLR, PCIE_PROT_STEP1_0_MASK);
#ifndef IGNORE_MTCMOS_CHECK
		/* Note that this protect ack check after releasing protect has been ignored */
#endif
		/* TINFO="Finish to turn on PCIE" */
	}
}

void pcie_cg_enable(void)
{
	DRV_WriteReg32(INFRA_TOPAXI_MODULE_SW_CG_1_SET, PCIE_SW_CG_1);
	DRV_WriteReg32(INFRA_TOPAXI_MODULE_SW_CG_3_SET, PCIE_SW_CG_3);
	DRV_WriteReg32(INFRA_TOPAXI_MODULE_SW_CG_4_SET, PCIE_SW_CG_4);
}

void pcie_cg_disable(void)
{
	DRV_WriteReg32(INFRA_TOPAXI_MODULE_SW_CG_1_CLR, PCIE_SW_CG_1);
	DRV_WriteReg32(INFRA_TOPAXI_MODULE_SW_CG_3_CLR, PCIE_SW_CG_3);
	DRV_WriteReg32(INFRA_TOPAXI_MODULE_SW_CG_4_CLR, PCIE_SW_CG_4);
}

void pcie_power_off(void)
{
	pcie_printf(PCIE_UARTDBG_INFO, "Power off PCIE\r\n");

	/* Power off pcie mtcmos */
	spm_mtcmos_ctrl_pcie(STA_POWER_DOWN);

	/* Set PCIE PHY reset mode */
#ifdef CHIP10992
	toprgu_ctrl_pcie_off();
#endif

#ifdef MT6298
	phy_ctrl_pcie_off();
#endif
}

PCIE_detect_result_e pcie_get_link_state(void)
{
	if(g_pcie_detect_result == PCIE_LINK_UNKNOWN){
		g_pcie_detect_result = pcie_detect();
	}

	dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_NIL, "[PCIE][LINK]Link state %d, LTSSM %x", g_pcie_detect_result, g_ltssm); 	

	return g_pcie_detect_result;
}

void pcie_mac_mtcmos_ctrl(kal_bool enable){

    dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_NIL, "[PCIE][MTCMOS]Plat Code %d", Plat_SW_Code()); 
	
    if (enable) {
				
        if(Plat_SW_Code() == 0)
        {
            spm_mtcmos_rsb_on(PEXTP_D_2LX1_PWR_CON,PEXTP_D_2LX1_PWR_ACK_IDX);		
        }
        else
        {
            spm_mtcmos_on(PEXTP_D_2LX1_PWR_CON,PEXTP_D_2LX1_PWR_ACK_IDX);
        }		
        spm_mtcmos_sram_chain_on(PEXTP_D_2LX1_PWR_CON);
        clr_protect_pextp_d_2lx1();
    }
    else {
        set_protect_pextp_d_2lx1();
        spm_mtcmos_sram_chain_off(PEXTP_D_2LX1_PWR_CON);
		
        if(Plat_SW_Code() == 0)
        {
            spm_mtcmos_rsb_off(PEXTP_D_2LX1_PWR_CON,PEXTP_D_2LX1_PWR_ACK_IDX);
        }
        else
        {
            spm_mtcmos_off(PEXTP_D_2LX1_PWR_CON,PEXTP_D_2LX1_PWR_ACK_IDX);
        }
    }
}

void pcie_phy_mtcmos_ctrl(kal_bool enable){
    if (enable) {
        spm_mtcmos_on(PEXTP_D_2LX1_PHY_PWR_CON,PEXTP_D_2LX1_PHY_PWR_ACK_IDX);  
    }
    else {
        spm_mtcmos_off(PEXTP_D_2LX1_PHY_PWR_CON,PEXTP_D_2LX1_PHY_PWR_ACK_IDX);
    }
}

void spm_mtcmos_rsb_on(kal_uint32 reg_addr, int ack_index)
{
    /* TINFO="Set PWR_RST_B = 1" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) | PWR_RST_B);
}

void spm_mtcmos_rsb_off(kal_uint32 reg_addr, int ack_index)
{
    /* TINFO="Set PWR_RST_B = 0" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) & ~PWR_RST_B);
}

void spm_mtcmos_on(kal_uint32 reg_addr, int ack_index){
    /* TINFO="Set PWR_ON = 1" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) | PWR_ON);
#ifndef IGNORE_MTCMOS_CHECK
    while ((DRV_Reg32(PWR_STATUS) & (0x1<<ack_index)) != (0x1<<ack_index));
#endif
    /* TINFO="Set PWR_ON_2ND = 1" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) | PWR_ON_2ND);
#ifndef IGNORE_MTCMOS_CHECK
    while ((DRV_Reg32(PWR_STATUS_2ND) & (0x1<<ack_index)) != (0x1<<ack_index));
#endif
    /* TINFO="Set PWR_CLK_DIS = 0" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) & ~PWR_CLK_DIS);
    /* TINFO="Set PWR_ISO = 0" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) & ~PWR_ISO);
    /* TINFO="Set PWR_RST_B = 1" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) | PWR_RST_B);
}

void spm_mtcmos_off(kal_uint32 reg_addr, int ack_index){
    /* TINFO="Set PWR_ISO = 1" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) | PWR_ISO);
    /* TINFO="Set PWR_CLK_DIS = 1" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) | PWR_CLK_DIS);
    /* TINFO="Set PWR_RST_B = 0" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) & ~PWR_RST_B);
    /* TINFO="Set PWR_ON = 0" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) & ~PWR_ON);
#ifndef IGNORE_MTCMOS_CHECK
    while ((DRV_Reg32(PWR_STATUS) & (0x1<<ack_index)));
#endif
    /* TINFO="Set PWR_ON_2ND = 0" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) & ~PWR_ON_2ND);
#ifndef IGNORE_MTCMOS_CHECK
    while ((DRV_Reg32(PWR_STATUS_2ND) & (0x1<<ack_index)));
#endif
}

void spm_mtcmos_sram_chain_on(kal_uint32 reg_addr){
    /* TINFO="Start to turn on MTCMOS_SRAM CHAIN" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) & ~SRAM_PD_OFFSET);
    /* TINFO="WAITING MTCMOS_SRAM_ACK" */
    while((DRV_Reg32(reg_addr) & SRAM_PD_ACK_OFFSET) == SRAM_PD_ACK_OFFSET);
}

void spm_mtcmos_sram_chain_off(kal_uint32 reg_addr){
    /* TINFO="Start to turn off MTCMOS_SRAM CHAIN" */
    DRV_WriteReg32(reg_addr, DRV_Reg32(reg_addr) | SRAM_PD_OFFSET);
    /* TINFO="WAITING MTCMOS_SRAM_ACK" */
    while((DRV_Reg32(reg_addr) & SRAM_PD_ACK_OFFSET) != SRAM_PD_ACK_OFFSET);
}

void set_protect_pextp_d_2lx1(void){
    set_prot0(BUS_PROT0_PCIE0);
    set_prot3(BUS_PROT3_PCIE0);
    set_prot4(BUS_PROT4_PCIE0);
}

void clr_protect_pextp_d_2lx1(void){
    clr_prot0(BUS_PROT0_PCIE0);
    clr_prot3(BUS_PROT3_PCIE0);
    clr_prot4(BUS_PROT4_PCIE0);
}

////////////////
void set_prot0(unsigned int prot){
    /*TINFO="SET PROTECT0"*/
    DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_SET,prot);
    /*TINFO="WAIT PROTECT0 ACK"*/
    while((DRV_Reg32(INFRA_TOPAXI_PROTECTEN_STA1)&prot) != prot);
}

void clr_prot0(unsigned int prot){
    /*TINFO="CLR PROTECT0"*/
    DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_CLR,prot);
}

void set_prot1(unsigned int prot){
    /*TINFO="SET PROTECT1"*/
    DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_1_SET,prot);
    /*TINFO="WAIT PROTECT1 ACK"*/
    while((DRV_Reg32(INFRA_TOPAXI_PROTECTEN_STA1_1)&prot) != prot);
}
void clr_prot1(unsigned int prot){
    /*TINFO="CLR PROTECT1"*/
    DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_1_CLR,prot);
}

void set_prot2(unsigned int prot){
    /*TINFO="SET PROTECT2"*/
    DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_SET_2,prot);
    /*TINFO="WAIT PROTECT2 ACK"*/
    while((DRV_Reg32(INFRA_TOPAXI_PROTECTEN_STA1_2)&prot) != prot);
}
void clr_prot2(unsigned int prot){
    /*TINFO="CLR PROTECT2"*/
    DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_CLR_2,prot);
}

void set_prot3(unsigned int prot){
    /*TINFO="SET PROTECT3"*/
    DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_SET,prot);
    /*TINFO="WAIT PROTECT3 ACK"*/
    while((DRV_Reg32(INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA1)&prot) != prot);
}

void clr_prot3(unsigned int prot){
    /*TINFO="CLR PROTECT3"*/
    DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_CLR,prot);
}

void set_prot4(unsigned int prot){
    /*TINFO="SET PROTECT4"*/
    DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_SET_1,prot);
    /*TINFO="WAIT PROTECT4 ACK"*/
    while((DRV_Reg32(INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA1_1)&prot) != prot);
}

void clr_prot4(unsigned int prot){
    /*TINFO="CLR PROTECT4"*/
    DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_CLR_1,prot);
}

void set_prot6(unsigned int prot){
    /*TINFO="SET PROTECT6"*/
    DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_MM_SET,prot);
    /*TINFO="WAIT PROTECT6 ACK"*/
    while((DRV_Reg32(INFRA_TOPAXI_PROTECTEN_MM_STA1)&prot) != prot);
}
void clr_prot6(unsigned int prot){
    /*TINFO="CLR PROTECT6"*/
    DRV_WriteReg32(INFRA_TOPAXI_PROTECTEN_MM_CLR,prot);
}
////////////////