| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | #ifndef __RSTCTL_REG_H__ |
| 2 | #define __RSTCTL_REG_H__ |
| 3 | |
| 4 | #include <reg_base.h> |
| 5 | #include <irqid.h> |
| 6 | |
| 7 | #define BASE_ADDR_MDRSTCTL (BASE_ADDR_MDRGU) |
| 8 | #define BASE_ADDR_APRSTCTL (BASE_ADDR_APRGU) |
| 9 | |
| 10 | #define REG_APRSTCTL_SRBER_APINFRA (BASE_ADDR_APRSTCTL+0x031C) //For Yts's reset CLDMA |
| 11 | #define REG_APRSTCTL_SRBER_APPERI (BASE_ADDR_APRSTCTL+0x0310) //For Yts's reset CLDMA_AO |
| 12 | |
| 13 | #define REG_APRSTCTL_SRSTR_APPERI (BASE_ADDR_APRSTCTL+0x0158) //For Yts's reset CLDMA_AO |
| 14 | #define REG_APRSTCTL_SRSTR_APINFRA (BASE_ADDR_APRSTCTL+0x0160) //For Yts's reset CLDMA |
| 15 | #define REG_APRSTCTL_SRCMR (BASE_ADDR_APRSTCTL+0x0300) //For Yts's reset CLDMA & CLDMA_AO |
| 16 | |
| 17 | #define REG_APRSTCTL_WDTSR (BASE_ADDR_APRSTCTL+0x0130) //For Elbrus FPGA RGU IT |
| 18 | #define REG_APRSTCTL_WDTCR (BASE_ADDR_APRSTCTL+0x0100) //For Elbrus FPGA RGU IT |
| 19 | #define REG_APRSTCTL_WDTIR (BASE_ADDR_APRSTCTL+0x0110) //For Elbrus FPGA RGU IT |
| 20 | #define REG_APRSTCTL_WDTRR (BASE_ADDR_APRSTCTL+0x0114) //For Elbrus FPGA RGU IT |
| 21 | #define REG_APRSTCTL_SRCMR_SWDT (BASE_ADDR_APRSTCTL+0x0304) //For Elbrus FPGA RGU IT |
| 22 | #define REG_APRSTCTL_WDTSR_MD1 (BASE_ADDR_APRSTCTL+0x0134) //For Elbrus FPGA RGU IT |
| 23 | #define REG_APRSTCTL_MDWDTCFG_MD1 (BASE_ADDR_APRSTCTL+0x0330) //For Elbrus FPGA RGU IT |
| 24 | #define REG_APRSTCTL_WDT_DUMMY (BASE_ADDR_APRSTCTL+0x0358) //For Elbrus FPGA RGU IT |
| 25 | #define REG_APRSTCTL_DUMMY (BASE_ADDR_APRSTCTL+0x0190) //For Elbrus FPGA RGU IT |
| 26 | |
| 27 | |
| 28 | #define REG_MDRSTCTL_WDTCR (BASE_ADDR_MDRSTCTL+0x0100) |
| 29 | #define REG_MDRSTCTL_WDTRR (BASE_ADDR_MDRSTCTL+0x0110) |
| 30 | /* |
| 31 | #define REG_MDRSTCTL_WDTER_MDPERI (BASE_ADDR_MDRSTCTL+0x0114) |
| 32 | #define REG_MDRSTCTL_WDTER_MDMCU (BASE_ADDR_MDRSTCTL+0x0118) |
| 33 | #define REG_MDRSTCTL_WDTER_MDINFRA (BASE_ADDR_MDRSTCTL+0x011C) |
| 34 | #define REG_MDRSTCTL_WDTER_LTEL2 (BASE_ADDR_MDRSTCTL+0x0120) |
| 35 | #define REG_MDRSTCTL_WDTER_HSPAL2 (BASE_ADDR_MDRSTCTL+0x0124) |
| 36 | */ |
| 37 | #define REG_MDRSTCTL_WDTER_MDSYS (BASE_ADDR_MDRSTCTL+0x0128) |
| 38 | |
| 39 | #define REG_MDRSTCTL_WDTSR (BASE_ADDR_MDRSTCTL+0x0134) |
| 40 | |
| 41 | /* |
| 42 | #define REG_MDRSTCTL_SRSTR_MDPERI (BASE_ADDR_MDRSTCTL+0x0144) |
| 43 | #define REG_MDRSTCTL_SRSTR_MDMCU (BASE_ADDR_MDRSTCTL+0x0148) |
| 44 | #define REG_MDRSTCTL_SRSTR_MDINFRA (BASE_ADDR_MDRSTCTL+0x014C) |
| 45 | #define REG_MDRSTCTL_SRSTR_LTEL2 (BASE_ADDR_MDRSTCTL+0x0150) |
| 46 | #define REG_MDRSTCTL_SRSTR_HSPAL2 (BASE_ADDR_MDRSTCTL+0x0154) |
| 47 | */ |
| 48 | #define REG_MDRSTCTL_SRSTR_MDSYS (BASE_ADDR_MDRSTCTL+0x0158) |
| 49 | |
| 50 | //#define REG_MDRSTCTL_RESET_UNLOCK (BASE_ADDR_MDRSTCTL+0x0168) |
| 51 | #define REG_MDRSTCTL_DUMMY (BASE_ADDR_MDRSTCTL+0x016C) |
| 52 | |
| 53 | /* |
| 54 | #define REG_MDRSTCTL_APWDTER_MDPERI (BASE_ADDR_MDRSTCTL+0x0170) //AP software reset MD |
| 55 | #define REG_MDRSTCTL_APWDTER_MDMCU (BASE_ADDR_MDRSTCTL+0x0174) //AP software reset MD |
| 56 | #define REG_MDRSTCTL_APWDTER_MDINFRA (BASE_ADDR_MDRSTCTL+0x0178) //AP software reset MD |
| 57 | #define REG_MDRSTCTL_APWDTER_LTEL2 (BASE_ADDR_MDRSTCTL+0x017C) //AP software reset MD |
| 58 | #define REG_MDRSTCTL_APWDTER_HSPAL2 (BASE_ADDR_MDRSTCTL+0x0180) //AP software reset MD |
| 59 | */ |
| 60 | |
| 61 | #define REG_MDRSTCTL_CHECK_BIT_SET (BASE_ADDR_MDRSTCTL+0x0184) |
| 62 | #define REG_MDRSTCTL_CHECK_BIT_CLR (BASE_ADDR_MDRSTCTL+0x0188) |
| 63 | #define REG_MDRSTCTL_KICK_BIT_SET (BASE_ADDR_MDRSTCTL+0x018C) |
| 64 | #define REG_MDRSTCTL_KICK_BIT_CLR (BASE_ADDR_MDRSTCTL+0x0190) |
| 65 | #define REG_MDRSTCTL_CHECK_BIT_STS (BASE_ADDR_MDRSTCTL+0x0194) |
| 66 | #define REG_MDRSTCTL_KICK_BIT_STS (BASE_ADDR_MDRSTCTL+0x0198) |
| 67 | |
| 68 | #define REG_MDRSTCTL_V0_KICK_FRC (BASE_ADDR_MDRSTCTL+0x019C) |
| 69 | #define REG_MDRSTCTL_V1_KICK_FRC (BASE_ADDR_MDRSTCTL+0x01A0) |
| 70 | #define REG_MDRSTCTL_V2_KICK_FRC (BASE_ADDR_MDRSTCTL+0x01A4) |
| 71 | #define REG_MDRSTCTL_V3_KICK_FRC (BASE_ADDR_MDRSTCTL+0x01A8) |
| 72 | |
| 73 | #define REG_MDRSTCTL_RESTART_FRC (BASE_ADDR_MDRSTCTL+0x01BC) |
| 74 | #define REG_MDRSTCTL_WDT_CNT (BASE_ADDR_MDRSTCTL+0x01C0) |
| 75 | #define REG_MDRSTCTL_AUXWDT_CNT (BASE_ADDR_MDRSTCTL+0x01C4) |
| 76 | #define REG_MDRSTCTL_WDT1_STS (BASE_ADDR_MDRSTCTL+0x01C8) |
| 77 | |
| 78 | #define REG_MDRSTCTL_SRCMR (BASE_ADDR_MDRSTCTL+0x0300) |
| 79 | #define REG_MDRSTCTL_SRCMR_SWDT (BASE_ADDR_MDRSTCTL+0x0304) |
| 80 | |
| 81 | /* |
| 82 | #define REG_MDRSTCTL_SRBER_MDPERI (BASE_ADDR_MDRSTCTL+0x0308) |
| 83 | #define REG_MDRSTCTL_SRBER_MDMCU (BASE_ADDR_MDRSTCTL+0x030C) |
| 84 | #define REG_MDRSTCTL_SRBER_MDINFRA (BASE_ADDR_MDRSTCTL+0x0310) |
| 85 | #define REG_MDRSTCTL_SRBER_LTEL2 (BASE_ADDR_MDRSTCTL+0x0314) |
| 86 | #define REG_MDRSTCTL_SRBER_HSPAL2 (BASE_ADDR_MDRSTCTL+0x0318) |
| 87 | */ |
| 88 | #define REG_MDRSTCTL_SRBER_MDSYS (BASE_ADDR_MDRSTCTL+0x0308) |
| 89 | |
| 90 | #define REG_MDRSTCTL_WDTIR (BASE_ADDR_MDRSTCTL+0x033C) |
| 91 | #define REG_MDRSTCTL_WDTIR_AUX (BASE_ADDR_MDRSTCTL+0x0340) |
| 92 | #define REG_MDRSTCTL_WDT_DUMMY (BASE_ADDR_MDRSTCTL+0x0358) |
| 93 | |
| 94 | #define _RST_DURATION_LOOP_DEFAULT_VALUE (10000) /* Just a magic number for reset duration */ |
| 95 | |
| 96 | |
| 97 | /**< REG_MDRGU_CHECK(KICK)_BIT_SET(CLR) */ |
| 98 | #define RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET (16) |
| 99 | #define RSTCTL_MD_CHECK_AND_KICK_KEY (0x87E8) |
| 100 | #define RSTCTL_MD_CHECK_AND_KICK_0 (1 << 0) |
| 101 | #define RSTCTL_MD_CHECK_AND_KICK_1 (1 << 1) |
| 102 | #define RSTCTL_MD_CHECK_AND_KICK_2 (1 << 2) |
| 103 | #define RSTCTL_MD_CHECK_AND_KICK_3 (1 << 3) |
| 104 | #define RSTCTL_MD_CHECK_AND_KICK_4 (1 << 4) |
| 105 | #define RSTCTL_MD_CHECK_AND_KICK_5 (1 << 5) |
| 106 | #define RSTCTL_MD_CHECK_AND_KICK_6 (1 << 6) |
| 107 | #define RSTCTL_MD_CHECK_AND_KICK_7 (1 << 7) |
| 108 | #define RSTCTL_MD_CHECK_AND_KICK_KEY_0 ((0x87E8+0) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) |
| 109 | #define RSTCTL_MD_CHECK_AND_KICK_KEY_1 ((0x87E8+1) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) |
| 110 | #define RSTCTL_MD_CHECK_AND_KICK_KEY_2 ((0x87E8+2) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) |
| 111 | #define RSTCTL_MD_CHECK_AND_KICK_KEY_3 ((0x87E8+3) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) |
| 112 | #define RSTCTL_MD_CHECK_AND_KICK_KEY_4 ((0x87E8+4) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) |
| 113 | #define RSTCTL_MD_CHECK_AND_KICK_KEY_5 ((0x87E8+5) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) |
| 114 | #define RSTCTL_MD_CHECK_AND_KICK_KEY_6 ((0x87E8+6) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) |
| 115 | #define RSTCTL_MD_CHECK_AND_KICK_KEY_7 ((0x87E8+7) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) |
| 116 | |
| 117 | //For Yts's reset CLDMA(< REG_APRSTCTL_SRBER_APINFRA>) |
| 118 | #define RSTCTL_APSRBER_CLDMA_RST (1 << 16) /**< Soft reset of CLDMA */ |
| 119 | #define RSTCTL_APSRBER_CLDMA_AO_RST (1 << 15) /**< Soft reset of CLDMA_AO */ |
| 120 | |
| 121 | |
| 122 | /**< REG_MDRSTCTL_SRBER_MDSYS */ |
| 123 | #define RSTCTL_MDSRBER_IA_LOGGER_RST (1 << 0) /**< Soft reset of USIM1 */ |
| 124 | #define RSTCTL_MDSRBER_MDUART0_RST (1 << 16) /**< Soft reset of MDUART0 */ |
| 125 | #define RSTCTL_MDSRBER_MDUART1_RST (1 << 17) /**< Soft reset of MDUART1 */ |
| 126 | #define RSTCTL_MDSRBER_SOE_RST (1 << 18) /**< Soft reset of SOE (security offload engine) */ |
| 127 | #define RSTCTL_MDSRBER_USIM1_RST (1 << 19) /**< Soft reset of USIM1 */ |
| 128 | #define RSTCTL_MDSRBER_USIM2_RST (1 << 20) /**< Soft reset of USIM2 */ |
| 129 | #define RSTCTL_MDSRBER_MDGPTM_RST (1 << 21) /**< Soft reset of MDGPTM */ |
| 130 | #define RSTCTL_MDSRBER_MDTOPSM_RST (1 << 22) /**< Soft reset of MDTOPSM */ |
| 131 | #define RSTCTL_MDSRBER_MDOST_RST (1 << 23) /**< Soft reset of MDOST */ |
| 132 | #define RSTCTL_MDSRBER_TRACE_RST (1 << 24) /**< Soft reset of TRACE */ |
| 133 | #define RSTCTL_MDSRBER_L1SYS_RST (1 << 25) /**< Soft reset of L1SYS : only valid for MDARM */ |
| 134 | #define RSTCTL_MDSRBER_MML2_RST (1 << 26) /**< Soft reset of L1SYS : only valid for MDARM */ |
| 135 | |
| 136 | /**< REG_MDRGU_WDTCR */ |
| 137 | #define RSTCTL_WDTCR_KEY_CONTROL_OFFSET (24) |
| 138 | #define RSTCTL_WDTCR_KEY (0x55 << RSTCTL_WDTCR_KEY_CONTROL_OFFSET) |
| 139 | #define RSTCTL_WDTCR_WDT_SPD_UP (1 << 15) /* watch dog timer speed up mode (timer will decrease by 256 per cycle if enable)*/ |
| 140 | #define RSTCTL_WDTCR_AUX_WDT_IRQEN (1 << 5) /*watch dog timer interrupt enable for WDT2*/ |
| 141 | #define RSTCTL_WDTCR_WDT_IRQEN (1 << 4) /* watch dog timer interrupt enable (select "intterrupt" or "reset" when watch dog timeout) */ |
| 142 | #define RSTCTL_WDTCR_AUX_WDT_EN (1 << 1) /* watch dog timer enable for WDT2*/ |
| 143 | #define RSTCTL_WDTCR_WDT_EN (1 << 0) /* watch dog timer enable */ |
| 144 | |
| 145 | |
| 146 | /**< REG_MDRSTCTL_WDTIR */ |
| 147 | #define RSTCTL_WDTIR_KEY_INTV_OFFSET (24) |
| 148 | #define RSTCTL_WDTIR_KEY (0x67 << RSTCTL_WDTIR_KEY_INTV_OFFSET) |
| 149 | #define RSTCTL_WDTIR_AUX_KEY (0x68 << RSTCTL_WDTIR_KEY_INTV_OFFSET) |
| 150 | #define RSTCTL_WDTIR_INTERVAL_MASK (0x3FFFFF) /* Watch dog timer down count interval (the real interval is 1/32.768k */ |
| 151 | #define RSTCTL_WDTIR_INTERVAL_OFFSET (0) |
| 152 | |
| 153 | |
| 154 | /**< REG_MDRSTCTL_WDTRR */ |
| 155 | #define RSTCTL_WDTRR_KEY_RESTART_OFFSET (16) |
| 156 | #define RSTCTL_WDTRR_KEY (0x7208 << RSTCTL_WDTRR_KEY_RESTART_OFFSET) |
| 157 | #define RSTCTL_WDTRR_WDT_RESTART (1 << 0) |
| 158 | |
| 159 | /**< REG_MDRSTCTL_RESET_UNLOCK */ |
| 160 | #define RSTCTL_MIPS_RESET_UNLOCK_STS (1 << 16) |
| 161 | #define RSTCTL_MIPS_RESET_UNLOCK_CMD (1 << 0) |
| 162 | |
| 163 | |
| 164 | /**< REG_MDRSTCTL_WDTSR */ |
| 165 | #define RSTCTL_WDTSR_KEY_OFFSET (16) |
| 166 | #define RSTCTL_WDTSR_KEY (0x7662 << RSTCTL_WDTSR_KEY_OFFSET) |
| 167 | #define RSTCTL_WDTSR_STATUS_MASK (0x7) /* Watchdog status */ |
| 168 | #define RSTCTL_WDTSR_AUX_STATUS_MASK (0x7) /* Watchdog status for WDT2*/ |
| 169 | #define RSTCTL_WDTSR_STATUS_OFFSET (0) |
| 170 | #define RSTCTL_WDTSR_AUX_STATUS_OFFSET (8) |
| 171 | #define RSTCTL_WDTSR_STS_CLR_OFFSET (4) |
| 172 | #define RSTCTL_WDTSR_AUX_STS_CLR_OFFSET (12) |
| 173 | #define RSTCTL_WDTSR_MD_HWDT (1 << 0) |
| 174 | #define RSTCTL_WDTSR_MD_SWDT (1 << 1) |
| 175 | #define RSTCTL_WDTSR_OST_TIMEOUT (1 << 2) |
| 176 | #define RSTCTL_WDTSR_AUX_MD_HWDT (1 << 8) |
| 177 | #define RSTCTL_WDTSR_AUX_MD_SWDT (1 << 9) |
| 178 | #define RSTCTL_WDTSR_AUX_OST_TIMEOUT (1 << 10) |
| 179 | |
| 180 | |
| 181 | |
| 182 | |
| 183 | /**< REG_MDRSTCTL_SRCMR_SWDT */ |
| 184 | #define RSTCTL_MDSRCMR_SWDT_KEY_MASK (0xffff) |
| 185 | #define RSTCTL_MDSRCMR_SWDT_KEY_OFFSET (16) |
| 186 | #define RSTCTL_MDSRCMR_SWDT_KEY (0x1688 << RSTCTL_MDSRCMR_SWDT_KEY_OFFSET) |
| 187 | #define RSTCTL_MDSRCMR_SWDT_RST (1 << 0) |
| 188 | #define RSTCTL_MDSRCMR_AUX_SWDT_RST (1 << 7) |
| 189 | #define RSTCTL_SRCMR_KEY_SWDT (RSTCTL_MDSRCMR_SWDT_KEY | 0x1) /* Key to enable software watch dog reset */ |
| 190 | #define RSTCTL_AUX_SRCMR_KEY_SWDT (RSTCTL_MDSRCMR_SWDT_KEY | RSTCTL_MDSRCMR_AUX_SWDT_RST) /* Key to enable WDT2 software watch dog reset */ |
| 191 | |
| 192 | |
| 193 | /**< REG_MDRSTCTL_SRCMR */ |
| 194 | #define RSTCTL_MDSRCMR_KEY_MASK (0xffff) |
| 195 | #define RSTCTL_MDSRCMR_KEY_OFFSET (16) |
| 196 | #define RSTCTL_MDSRCMR_SRCMR_KEY (0x2593 << RSTCTL_MDSRCMR_KEY_OFFSET) |
| 197 | #define RSTCTL_MDSRCMR_SWDT_RST (1 << 0) |
| 198 | #define RSTCTL_SRCMR_KEY_SWRST (RSTCTL_MDSRCMR_SRCMR_KEY | 0x1) /* Key to enable software reset */ |
| 199 | |
| 200 | #endif /* end of __GPT_REG_H__ */ |
| 201 | |