| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2017 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /******************************************************************************* |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * tia_reg.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * VMOLY |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * TIA (Thermal Information Acquisition) hardware register header |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
| 58 | * removed! |
| 59 | * removed! |
| 60 | * removed! |
| 61 | *------------------------------------------------------------------------------ |
| 62 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 63 | *============================================================================ |
| 64 | ****************************************************************************/ |
| 65 | |
| 66 | |
| 67 | #ifndef __TIA_REG_H__ |
| 68 | #define __TIA_REG_H__ |
| 69 | |
| 70 | #include "reg_base.h" |
| 71 | //^^ move to reg_base_MTxxxx_username.h |
| 72 | #ifndef BASE_INFRA_AO_TOPRGU |
| 73 | #define BASE_INFRA_AO_TOPRGU (0xC0007000) |
| 74 | #endif |
| 75 | #ifndef BASE_MADDR_TIA |
| 76 | #define BASE_MADDR_TIA (0xC001C000) |
| 77 | #endif |
| 78 | //&& |
| 79 | |
| 80 | #define TIA_M2N(adr) (((adr) & ~0xF0000000) | 0xD0000000) |
| 81 | |
| 82 | #define TIA_BASE (BASE_MADDR_TIA) |
| 83 | #define TIA_AUXADC_CMD_ADDR (TIA_BASE + 0x0000) |
| 84 | #define TIA_AUXADC_CMD_ADDR_AUXADC_CMD_ADDR0_MSK (0xFFFF << 0) |
| 85 | #define TIA_AUXADC_CMD_ADDR_AUXADC_CMD_ADDR0(n) (((n) << 0) & TIA_AUXADC_CMD_ADDR_AUXADC_CMD_ADDR0_MSK) |
| 86 | #define TIA_AUXADC_CMD_ADDR_AUXADC_CMD_ADDR1_MSK (0xFFFF << 16) |
| 87 | #define TIA_AUXADC_CMD_ADDR_AUXADC_CMD_ADDR1(n) (((n) << 16) & TIA_AUXADC_CMD_ADDR_AUXADC_CMD_ADDR1_MSK) |
| 88 | #define TIA_AUXADC_CMD (TIA_BASE + 0x0004) |
| 89 | #define TIA_AUXADC_CMD_AUXADC_CMD0_MSK (0xFFFF << 0) |
| 90 | #define TIA_AUXADC_CMD_AUXADC_CMD0(n) (((n) << 0) & TIA_AUXADC_CMD_AUXADC_CMD0_MSK) |
| 91 | #define TIA_AUXADC_CMD_AUXADC_CMD1_MSK (0xFFFF << 16) |
| 92 | #define TIA_AUXADC_CMD_AUXADC_CMD1(n) (((n) << 16) & TIA_AUXADC_CMD_AUXADC_CMD1_MSK) |
| 93 | #define TIA_AUXADC_TEMP_ADDR (TIA_BASE + 0x0008) |
| 94 | #define TIA_AUXADC_TEMP_ADDR_AUXADC_RDATA_ADDR0_MSK (0xFFFF << 0) |
| 95 | #define TIA_AUXADC_TEMP_ADDR_AUXADC_RDATA_ADDR0(n) (((n) << 0) & TIA_AUXADC_TEMP_ADDR_AUXADC_RDATA_ADDR0_MSK) |
| 96 | #define TIA_AUXADC_TEMP_ADDR_AUXADC_RDATA_ADDR1_MSK (0xFFFF << 16) |
| 97 | #define TIA_AUXADC_TEMP_ADDR_AUXADC_RDATA_ADDR1(n) (((n) << 16) & TIA_AUXADC_TEMP_ADDR_AUXADC_RDATA_ADDR1_MSK) |
| 98 | #define TIA_AUXADC_DLY (TIA_BASE + 0x000C) |
| 99 | #define TIA_AUXADC_DLY_AUXADC_INIT_DLY_MSK (0xFF << 0) |
| 100 | #define TIA_AUXADC_DLY_AUXADC_INIT_DLY(n) (((n) << 0) & TIA_AUXADC_DLY_AUXADC_INIT_DLY_MSK) |
| 101 | #define TIA_AUXADC_DLY_AUXADC_MEASURE_DLY_MSK (0xFF << 8) |
| 102 | #define TIA_AUXADC_DLY_AUXADC_MEASURE_DLY(n) (((n) << 8) & TIA_AUXADC_DLY_AUXADC_MEASURE_DLY_MSK) |
| 103 | #define TIA_MD_ON (TIA_BASE + 0x0010) |
| 104 | #define TIA_MD_ON_MD_ON (1 << 0) |
| 105 | #define TIA_MD_CTRL (TIA_BASE + 0x0014) |
| 106 | #define TIA_MD_CTRL_MD_PERIOD_MSK (0xFFF << 0) |
| 107 | #define TIA_MD_CTRL_MD_PERIOD(n) (((n) << 0) & TIA_MD_CTRL_MD_PERIOD_MSK) |
| 108 | #define TIA_MD_CTRL_MD_TEMP0_EN (1 << 12) |
| 109 | #define TIA_MD_CTRL_MD_TEMP1_EN (1 << 13) |
| 110 | #define TIA_MD_CTRL_MD_CLR_LATEST (1 << 14) |
| 111 | #define TIA_GPS_ON (TIA_BASE + 0x0018) |
| 112 | #define TIA_GPS_ON_GPS_ON (1 << 0) |
| 113 | #define TIA_GPS_CTRL (TIA_BASE + 0x001C) |
| 114 | #define TIA_GPS_CTRL_GPS_PERIOD_MSK (0xFFF << 0) |
| 115 | #define TIA_GPS_CTRL_GPS_PERIOD(n) (((n) << 0) & TIA_GPS_CTRL_GPS_PERIOD_MSK) |
| 116 | #define TIA_GPS_CTRL_GPS_TEMP0_EN (1 << 12) |
| 117 | #define TIA_GPS_CTRL_GPS_TEMP1_EN (1 << 13) |
| 118 | #define TIA_GPS_CTRL_GPS_CLR_LATEST (1 << 14) |
| 119 | #define TIA_TEMP (TIA_BASE + 0x0020) |
| 120 | #define TIA_TEMP_TEMP0_MSK (0xFFFF << 0) |
| 121 | #define TIA_TEMP_TEMP0(v) (((v) >> 0) & 0xFFFF) |
| 122 | #define TIA_TEMP_TEMP1_MSK (0xFFFF << 16) |
| 123 | #define TIA_TEMP_TEMP1(v) (((v) >> 16) & 0xFFFF) |
| 124 | #define TIA_SECUR (TIA_BASE + 0x0024) |
| 125 | #define TIA_SECUR_SEN (1 << 0) |
| 126 | #define TIA_SECUR_SEN_LOCK (1 << 1) |
| 127 | #define TIA_DEBUG (TIA_BASE + 0x00FC) |
| 128 | #define TIA_DEBUG_CNT_T_MSK (0xFFF << 0) |
| 129 | #define TIA_DEBUG_CNT_T(v) (((v) >> 0) & 0xFFF) |
| 130 | #define TIA_DEBUG_MD_LATEST0 (1 << 12) |
| 131 | #define TIA_DEBUG_MD_LATEST1 (1 << 13) |
| 132 | #define TIA_DEBUG_GPS_LATEST0 (1 << 14) |
| 133 | #define TIA_DEBUG_GPS_LATEST1 (1 << 15) |
| 134 | #define TIA_DEBUG_FSM_MSK (0x7 << 16) |
| 135 | #define TIA_DEBUG_FSM(v) (((v) >> 16) & 0x7) |
| 136 | #define TIA_TIA2_MODE_CTRL (TIA_BASE + 0x0028) |
| 137 | #define TIA_TIA2_MODE_CTRL_TIA_SEL (1 << 0) |
| 138 | #define TIA_TIA2_MODE_CTRL_TIA2_ON (1 << 1) |
| 139 | #define TIA_TIA2_MODE_CTRL_TIA2_MD_ON (1 << 4) |
| 140 | #define TIA_TIA2_MODE_CTRL_TIA2_GPS_ON (1 << 5) |
| 141 | #define TIA_TIA2_MODE_CTRL_TIA2_AP_ON (1 << 6) |
| 142 | #define TIA_TIA2_MODE_CTRL_TIA2_ADC_BIT_SEL (1 << 7) |
| 143 | #define TIA_TIA2_MD_RC_CTRL (TIA_BASE + 0x002C) |
| 144 | #define TIA_TIA2_MD_RC_CTRL_TSX_RC_SEL_MD_MSK (0x3 << 0) |
| 145 | #define TIA_TIA2_MD_RC_CTRL_TSX_RC_SEL_MD(n) (((n) << 0) & TIA_TIA2_MD_RC_CTRL_TSX_RC_SEL_MD_MSK) |
| 146 | #define TIA_TIA2_MD_RC_CTRL_T0_RC_SEL_MD_MSK (0x3 << 4) |
| 147 | #define TIA_TIA2_MD_RC_CTRL_T0_RC_SEL_MD(n) (((n) << 4) & TIA_TIA2_MD_RC_CTRL_T0_RC_SEL_MD_MSK) |
| 148 | #define TIA_TIA2_MD_RC_CTRL_T1_RC_SEL_MD_MSK (0x3 << 8) |
| 149 | #define TIA_TIA2_MD_RC_CTRL_T1_RC_SEL_MD(n) (((n) << 8) & TIA_TIA2_MD_RC_CTRL_T1_RC_SEL_MD_MSK) |
| 150 | #define TIA_TIA2_MD_RC_CTRL_T2_RC_SEL_MD_MSK (0x3 << 12) |
| 151 | #define TIA_TIA2_MD_RC_CTRL_T2_RC_SEL_MD(n) (((n) << 12) & TIA_TIA2_MD_RC_CTRL_T2_RC_SEL_MD_MSK) |
| 152 | #define TIA_TIA2_MD_RC_CTRL_T3_RC_SEL_MD_MSK (0x3 << 16) |
| 153 | #define TIA_TIA2_MD_RC_CTRL_T3_RC_SEL_MD(n) (((n) << 16) & TIA_TIA2_MD_RC_CTRL_T3_RC_SEL_MD_MSK) |
| 154 | #define TIA_TIA2_GPS_RC_CTRL (TIA_BASE + 0x0030) |
| 155 | #define TIA_TIA2_GPS_RC_CTRL_TSX_RC_SEL_GPS_MSK (0x3 << 0) |
| 156 | #define TIA_TIA2_GPS_RC_CTRL_TSX_RC_SEL_GPS(n) (((n) << 0) & TIA_TIA2_GPS_RC_CTRL_TSX_RC_SEL_GPS_MSK) |
| 157 | #define TIA_TIA2_GPS_RC_CTRL_T0_RC_SEL_GPS_MSK (0x3 << 4) |
| 158 | #define TIA_TIA2_GPS_RC_CTRL_T0_RC_SEL_GPS(n) (((n) << 4) & TIA_TIA2_GPS_RC_CTRL_T0_RC_SEL_GPS_MSK) |
| 159 | #define TIA_TIA2_GPS_RC_CTRL_T1_RC_SEL_GPS_MSK (0x3 << 8) |
| 160 | #define TIA_TIA2_GPS_RC_CTRL_T1_RC_SEL_GPS(n) (((n) << 8) & TIA_TIA2_GPS_RC_CTRL_T1_RC_SEL_GPS_MSK) |
| 161 | #define TIA_TIA2_GPS_RC_CTRL_T2_RC_SEL_GPS_MSK (0x3 << 12) |
| 162 | #define TIA_TIA2_GPS_RC_CTRL_T2_RC_SEL_GPS(n) (((n) << 12) & TIA_TIA2_GPS_RC_CTRL_T2_RC_SEL_GPS_MSK) |
| 163 | #define TIA_TIA2_GPS_RC_CTRL_T3_RC_SEL_GPS_MSK (0x3 << 16) |
| 164 | #define TIA_TIA2_GPS_RC_CTRL_T3_RC_SEL_GPS(n) (((n) << 16) & TIA_TIA2_GPS_RC_CTRL_T3_RC_SEL_GPS_MSK) |
| 165 | #define TIA_TIA2_AP_RC_CTRL (TIA_BASE + 0x0034) |
| 166 | #define TIA_TIA2_AP_RC_CTRL_TSX_RC_SEL_AP_MSK (0x3 << 0) |
| 167 | #define TIA_TIA2_AP_RC_CTRL_TSX_RC_SEL_AP(n) (((n) << 0) & TIA_TIA2_AP_RC_CTRL_TSX_RC_SEL_AP_MSK) |
| 168 | #define TIA_TIA2_AP_RC_CTRL_T0_RC_SEL_AP_MSK (0x3 << 4) |
| 169 | #define TIA_TIA2_AP_RC_CTRL_T0_RC_SEL_AP(n) (((n) << 4) & TIA_TIA2_AP_RC_CTRL_T0_RC_SEL_AP_MSK) |
| 170 | #define TIA_TIA2_AP_RC_CTRL_T1_RC_SEL_AP_MSK (0x3 << 8) |
| 171 | #define TIA_TIA2_AP_RC_CTRL_T1_RC_SEL_AP(n) (((n) << 8) & TIA_TIA2_AP_RC_CTRL_T1_RC_SEL_AP_MSK) |
| 172 | #define TIA_TIA2_AP_RC_CTRL_T2_RC_SEL_AP_MSK (0x3 << 12) |
| 173 | #define TIA_TIA2_AP_RC_CTRL_T2_RC_SEL_AP(n) (((n) << 12) & TIA_TIA2_AP_RC_CTRL_T2_RC_SEL_AP_MSK) |
| 174 | #define TIA_TIA2_AP_RC_CTRL_T3_RC_SEL_AP_MSK (0x3 << 16) |
| 175 | #define TIA_TIA2_AP_RC_CTRL_T3_RC_SEL_AP(n) (((n) << 16) & TIA_TIA2_AP_RC_CTRL_T3_RC_SEL_AP_MSK) |
| 176 | #define TIA_TIA2_ADC_INI_DLY (TIA_BASE + 0x0038) |
| 177 | #define TIA_TIA2_RC_30K_DLY (TIA_BASE + 0x003C) |
| 178 | #define TIA_TIA2_RC_100K_DLY (TIA_BASE + 0x0040) |
| 179 | #define TIA_TIA2_RC_400K_DLY (TIA_BASE + 0x0044) |
| 180 | #define TIA_TIA2_ADC15_CON_DLY (TIA_BASE + 0x0048) |
| 181 | #define TIA_TIA2_ADC12_30K_CON_DLY (TIA_BASE + 0x004C) |
| 182 | #define TIA_TIA2_ADC12_100K_CON_DLY (TIA_BASE + 0x0050) |
| 183 | #define TIA_TIA2_ADC12_400K_CON_DLY0 (TIA_BASE + 0x0054) |
| 184 | #define TIA_TIA2_ADC12_400K_CON_DLY1 (TIA_BASE + 0x0058) |
| 185 | #define TIA_TIA2_ADC12_CON_SRCLK (TIA_BASE + 0x005C) |
| 186 | #define TIA_TIA2_ADC_SET_ADDR (TIA_BASE + 0x0060) |
| 187 | #define TIA_TIA2_ADC_SET_ADDR_TIA2_ADC_SET_ADDR_MSK (0xFFFF << 0) |
| 188 | #define TIA_TIA2_ADC_SET_ADDR_TIA2_ADC_SET_ADDR(n) (((n) << 0) & TIA_TIA2_ADC_SET_ADDR_TIA2_ADC_SET_ADDR_MSK) |
| 189 | #define TIA_TIA2_TSX_30K_CMD (TIA_BASE + 0x0064) |
| 190 | #define TIA_TIA2_TSX_30K_CMD_TIA2_TSX_30K_CMD_MSK (0xFFFF << 0) |
| 191 | #define TIA_TIA2_TSX_30K_CMD_TIA2_TSX_30K_CMD(n) (((n) << 0) & TIA_TIA2_TSX_30K_CMD_TIA2_TSX_30K_CMD_MSK) |
| 192 | #define TIA_TIA2_TSX_100K_CMD (TIA_BASE + 0x0068) |
| 193 | #define TIA_TIA2_TSX_100K_CMD_TIA2_TSX_100K_CMD_MSK (0xFFFF << 0) |
| 194 | #define TIA_TIA2_TSX_100K_CMD_TIA2_TSX_100K_CMD(n) (((n) << 0) & TIA_TIA2_TSX_100K_CMD_TIA2_TSX_100K_CMD_MSK) |
| 195 | #define TIA_TIA2_TSX_400K_CMD (TIA_BASE + 0x006C) |
| 196 | #define TIA_TIA2_TSX_400K_CMD_TIA2_TSX_400K_CMD_MSK (0xFFFF << 0) |
| 197 | #define TIA_TIA2_TSX_400K_CMD_TIA2_TSX_400K_CMD(n) (((n) << 0) & TIA_TIA2_TSX_400K_CMD_TIA2_TSX_400K_CMD_MSK) |
| 198 | #define TIA_TIA2_ADC15_DCXO_CMD (TIA_BASE + 0x0070) |
| 199 | #define TIA_TIA2_ADC15_DCXO_CMD_TIA2_ADC15_DCXO_CMD_MSK (0xFFFF << 0) |
| 200 | #define TIA_TIA2_ADC15_DCXO_CMD_TIA2_ADC15_DCXO_CMD(n) (((n) << 0) & TIA_TIA2_ADC15_DCXO_CMD_TIA2_ADC15_DCXO_CMD_MSK) |
| 201 | #define TIA_TIA2_ADC12_DCXO_CMD (TIA_BASE + 0x0074) |
| 202 | #define TIA_TIA2_ADC12_DCXO_CMD_TIA2_ADC12_DCXO_CMD_MSK (0xFFFF << 0) |
| 203 | #define TIA_TIA2_ADC12_DCXO_CMD_TIA2_ADC12_DCXO_CMD(n) (((n) << 0) & TIA_TIA2_ADC12_DCXO_CMD_TIA2_ADC12_DCXO_CMD_MSK) |
| 204 | #define TIA_TIA2_T0_30K_CMD (TIA_BASE + 0x0078) |
| 205 | #define TIA_TIA2_T0_30K_CMD_TIA2_T0_30K_CMD_MSK (0xFFFF << 0) |
| 206 | #define TIA_TIA2_T0_30K_CMD_TIA2_T0_30K_CMD(n) (((n) << 0) & TIA_TIA2_T0_30K_CMD_TIA2_T0_30K_CMD_MSK) |
| 207 | #define TIA_TIA2_T1_30K_CMD (TIA_BASE + 0x007C) |
| 208 | #define TIA_TIA2_T1_30K_CMD_TIA2_T1_30K_CMD_MSK (0xFFFF << 0) |
| 209 | #define TIA_TIA2_T1_30K_CMD_TIA2_T1_30K_CMD(n) (((n) << 0) & TIA_TIA2_T1_30K_CMD_TIA2_T1_30K_CMD_MSK) |
| 210 | #define TIA_TIA2_T2_30K_CMD (TIA_BASE + 0x0080) |
| 211 | #define TIA_TIA2_T2_30K_CMD_TIA2_T2_30K_CMD_MSK (0xFFFF << 0) |
| 212 | #define TIA_TIA2_T2_30K_CMD_TIA2_T2_30K_CMD(n) (((n) << 0) & TIA_TIA2_T2_30K_CMD_TIA2_T2_30K_CMD_MSK) |
| 213 | #define TIA_TIA2_T3_30K_CMD (TIA_BASE + 0x0084) |
| 214 | #define TIA_TIA2_T3_30K_CMD_TIA2_T3_30K_CMD_MSK (0xFFFF << 0) |
| 215 | #define TIA_TIA2_T3_30K_CMD_TIA2_T3_30K_CMD(n) (((n) << 0) & TIA_TIA2_T3_30K_CMD_TIA2_T3_30K_CMD_MSK) |
| 216 | #define TIA_TIA2_T0_100K_CMD (TIA_BASE + 0x0088) |
| 217 | #define TIA_TIA2_T0_100K_CMD_TIA2_T0_100K_CMD_MSK (0xFFFF << 0) |
| 218 | #define TIA_TIA2_T0_100K_CMD_TIA2_T0_100K_CMD(n) (((n) << 0) & TIA_TIA2_T0_100K_CMD_TIA2_T0_100K_CMD_MSK) |
| 219 | #define TIA_TIA2_T1_100K_CMD (TIA_BASE + 0x008C) |
| 220 | #define TIA_TIA2_T1_100K_CMD_TIA2_T1_100K_CMD_MSK (0xFFFF << 0) |
| 221 | #define TIA_TIA2_T1_100K_CMD_TIA2_T1_100K_CMD(n) (((n) << 0) & TIA_TIA2_T1_100K_CMD_TIA2_T1_100K_CMD_MSK) |
| 222 | #define TIA_TIA2_T2_100K_CMD (TIA_BASE + 0x0090) |
| 223 | #define TIA_TIA2_T2_100K_CMD_TIA2_T2_100K_CMD_MSK (0xFFFF << 0) |
| 224 | #define TIA_TIA2_T2_100K_CMD_TIA2_T2_100K_CMD(n) (((n) << 0) & TIA_TIA2_T2_100K_CMD_TIA2_T2_100K_CMD_MSK) |
| 225 | #define TIA_TIA2_T3_100K_CMD (TIA_BASE + 0x0094) |
| 226 | #define TIA_TIA2_T3_100K_CMD_TIA2_T3_100K_CMD_MSK (0xFFFF << 0) |
| 227 | #define TIA_TIA2_T3_100K_CMD_TIA2_T3_100K_CMD(n) (((n) << 0) & TIA_TIA2_T3_100K_CMD_TIA2_T3_100K_CMD_MSK) |
| 228 | #define TIA_TIA2_T0_400K_CMD (TIA_BASE + 0x0098) |
| 229 | #define TIA_TIA2_T0_400K_CMD_TIA2_T0_400K_CMD_MSK (0xFFFF << 0) |
| 230 | #define TIA_TIA2_T0_400K_CMD_TIA2_T0_400K_CMD(n) (((n) << 0) & TIA_TIA2_T0_400K_CMD_TIA2_T0_400K_CMD_MSK) |
| 231 | #define TIA_TIA2_T1_400K_CMD (TIA_BASE + 0x009C) |
| 232 | #define TIA_TIA2_T1_400K_CMD_TIA2_T1_400K_CMD_MSK (0xFFFF << 0) |
| 233 | #define TIA_TIA2_T1_400K_CMD_TIA2_T1_400K_CMD(n) (((n) << 0) & TIA_TIA2_T1_400K_CMD_TIA2_T1_400K_CMD_MSK) |
| 234 | #define TIA_TIA2_T2_400K_CMD (TIA_BASE + 0x00A0) |
| 235 | #define TIA_TIA2_T2_400K_CMD_TIA2_T2_400K_CMD_MSK (0xFFFF << 0) |
| 236 | #define TIA_TIA2_T2_400K_CMD_TIA2_T2_400K_CMD(n) (((n) << 0) & TIA_TIA2_T2_400K_CMD_TIA2_T2_400K_CMD_MSK) |
| 237 | #define TIA_TIA2_T3_400K_CMD (TIA_BASE + 0x00A4) |
| 238 | #define TIA_TIA2_T3_400K_CMD_TIA2_T3_400K_CMD_MSK (0xFFFF << 0) |
| 239 | #define TIA_TIA2_T3_400K_CMD_TIA2_T3_400K_CMD(n) (((n) << 0) & TIA_TIA2_T3_400K_CMD_TIA2_T3_400K_CMD_MSK) |
| 240 | #define TIA_TIA2_ADC15_TRIG_ADDR (TIA_BASE + 0x00A8) |
| 241 | #define TIA_TIA2_ADC15_TRIG_ADDR_TIA2_15ADC_TRIG_ADDR_MSK (0xFFFF << 0) |
| 242 | #define TIA_TIA2_ADC15_TRIG_ADDR_TIA2_15ADC_TRIG_ADDR(n) (((n) << 0) & TIA_TIA2_ADC15_TRIG_ADDR_TIA2_15ADC_TRIG_ADDR_MSK) |
| 243 | #define TIA_TIA2_ADC12_TRIG_ADDR (TIA_BASE + 0x00AC) |
| 244 | #define TIA_TIA2_ADC12_TRIG_ADDR_TIA2_12ADC_TRIG_ADDR_MSK (0xFFFF << 0) |
| 245 | #define TIA_TIA2_ADC12_TRIG_ADDR_TIA2_12ADC_TRIG_ADDR(n) (((n) << 0) & TIA_TIA2_ADC12_TRIG_ADDR_TIA2_12ADC_TRIG_ADDR_MSK) |
| 246 | #define TIA_TIA2_ADC15_TRIG_CMD (TIA_BASE + 0x00B0) |
| 247 | #define TIA_TIA2_ADC15_TRIG_CMD_TIA2_15ADC_TRIG_CMD_MSK (0xFFFF << 0) |
| 248 | #define TIA_TIA2_ADC15_TRIG_CMD_TIA2_15ADC_TRIG_CMD(n) (((n) << 0) & TIA_TIA2_ADC15_TRIG_CMD_TIA2_15ADC_TRIG_CMD_MSK) |
| 249 | #define TIA_TIA2_ADC12_TRIG_CMD0 (TIA_BASE + 0x00B4) |
| 250 | #define TIA_TIA2_ADC12_TRIG_CMD0_TIA2_12ADC_TRIG_CMD0_MSK (0xFFFF << 0) |
| 251 | #define TIA_TIA2_ADC12_TRIG_CMD0_TIA2_12ADC_TRIG_CMD0(n) (((n) << 0) & TIA_TIA2_ADC12_TRIG_CMD0_TIA2_12ADC_TRIG_CMD0_MSK) |
| 252 | #define TIA_TIA2_ADC12_TRIG_CMD1 (TIA_BASE + 0x00B8) |
| 253 | #define TIA_TIA2_ADC12_TRIG_CMD1_TIA2_12ADC_TRIG_CMD1_MSK (0xFFFF << 0) |
| 254 | #define TIA_TIA2_ADC12_TRIG_CMD1_TIA2_12ADC_TRIG_CMD1(n) (((n) << 0) & TIA_TIA2_ADC12_TRIG_CMD1_TIA2_12ADC_TRIG_CMD1_MSK) |
| 255 | #define TIA_TIA2_ADC15_READ_ADDR (TIA_BASE + 0x00BC) |
| 256 | #define TIA_TIA2_ADC15_READ_ADDR_TIA2_15ADC_READ_ADDR_MSK (0xFFFF << 0) |
| 257 | #define TIA_TIA2_ADC15_READ_ADDR_TIA2_15ADC_READ_ADDR(n) (((n) << 0) & TIA_TIA2_ADC15_READ_ADDR_TIA2_15ADC_READ_ADDR_MSK) |
| 258 | #define TIA_TIA2_ADC12_READ_ADDR0 (TIA_BASE + 0x00C0) |
| 259 | #define TIA_TIA2_ADC12_READ_ADDR0_TIA2_12ADC_READ_ADDR0_MSK (0xFFFF << 0) |
| 260 | #define TIA_TIA2_ADC12_READ_ADDR0_TIA2_12ADC_READ_ADDR0(n) (((n) << 0) & TIA_TIA2_ADC12_READ_ADDR0_TIA2_12ADC_READ_ADDR0_MSK) |
| 261 | #define TIA_TIA2_ADC12_READ_ADDR1 (TIA_BASE + 0x00C4) |
| 262 | #define TIA_TIA2_ADC12_READ_ADDR1_TIA2_12ADC_READ_ADDR1_MSK (0xFFFF << 0) |
| 263 | #define TIA_TIA2_ADC12_READ_ADDR1_TIA2_12ADC_READ_ADDR1(n) (((n) << 0) & TIA_TIA2_ADC12_READ_ADDR1_TIA2_12ADC_READ_ADDR1_MSK) |
| 264 | #define TIA_TIA2_READY_CLR (TIA_BASE + 0x00C8) |
| 265 | #define TIA_TIA2_READY_CLR_MD_MD_TSX_READY_CLR (1 << 0) |
| 266 | #define TIA_TIA2_READY_CLR_MD_T0_READY_CLR (1 << 1) |
| 267 | #define TIA_TIA2_READY_CLR_MD_T1_READY_CLR (1 << 2) |
| 268 | #define TIA_TIA2_READY_CLR_MD_T2_READY_CLR (1 << 3) |
| 269 | #define TIA_TIA2_READY_CLR_MD_T3_READY_CLR (1 << 4) |
| 270 | #define TIA_TIA2_READY_CLR_MD_GPS_TSX_READY_CLR (1 << 5) |
| 271 | #define TIA_TIA2_READY_CLR_MD_DCXO_READY_CLR (1 << 6) |
| 272 | #define TIA_TIA2_READY_CLR_GPS_MD_TSX_READY_CLR (1 << 7) |
| 273 | #define TIA_TIA2_READY_CLR_GPS_T0_READY_CLR (1 << 8) |
| 274 | #define TIA_TIA2_READY_CLR_GPS_T1_READY_CLR (1 << 9) |
| 275 | #define TIA_TIA2_READY_CLR_GPS_T2_READY_CLR (1 << 10) |
| 276 | #define TIA_TIA2_READY_CLR_GPS_T3_READY_CLR (1 << 11) |
| 277 | #define TIA_TIA2_READY_CLR_GPS_GPS_TSX_READY_CLR (1 << 12) |
| 278 | #define TIA_TIA2_READY_CLR_GPS_DCXO_READY_CLR (1 << 13) |
| 279 | #define TIA_TIA2_READY_CLR_AP_MD_TSX_READY_CLR (1 << 14) |
| 280 | #define TIA_TIA2_READY_CLR_AP_T0_READY_CLR (1 << 15) |
| 281 | #define TIA_TIA2_READY_CLR_AP_T1_READY_CLR (1 << 16) |
| 282 | #define TIA_TIA2_READY_CLR_AP_T2_READY_CLR (1 << 17) |
| 283 | #define TIA_TIA2_READY_CLR_AP_T3_READY_CLR (1 << 18) |
| 284 | #define TIA_TIA2_READY_CLR_AP_GPS_TSX_READY_CLR (1 << 19) |
| 285 | #define TIA_TIA2_READY_CLR_AP_DCXO_READY_CLR (1 << 20) |
| 286 | #define TIA_TIA2_MD_TSX_DATA (TIA_BASE + 0x00CC) |
| 287 | #define TIA_TIA2_MD_TSX_DATA_MD_MD_TSX_DATA_MSK (0xFFFF << 0) |
| 288 | #define TIA_TIA2_MD_TSX_DATA_MD_MD_TSX_DATA(v) (((v) >> 0) & 0xFFFF) |
| 289 | #define TIA_TIA2_GPS_TSX_DATA (TIA_BASE + 0x00D0) |
| 290 | #define TIA_TIA2_GPS_TSX_DATA_GPS_TSX_RC_MSK (0x3 << 16) |
| 291 | #define TIA_TIA2_GPS_TSX_DATA_GPS_TSX_RC(v) (((v) >> 16) & 0x3) |
| 292 | #define TIA_TIA2_GPS_TSX_DATA_GPS_TSX_DATA_MSK (0xFFFF << 0) |
| 293 | #define TIA_TIA2_GPS_TSX_DATA_GPS_TSX_DATA(v) (((v) >> 0) & 0xFFFF) |
| 294 | #define TIA_TIA2_T0_DATA (TIA_BASE + 0x00D4) |
| 295 | #define TIA_TIA2_T0_DATA_T0_RC_MSK (0x3 << 16) |
| 296 | #define TIA_TIA2_T0_DATA_T0_RC(v) (((v) >> 16) & 0x3) |
| 297 | #define TIA_TIA2_T0_DATA_T0_DATA_MSK (0xFFFF << 0) |
| 298 | #define TIA_TIA2_T0_DATA_T0_DATA(v) (((v) >> 0) & 0xFFFF) |
| 299 | #define TIA_TIA2_T1_DATA (TIA_BASE + 0x00D8) |
| 300 | #define TIA_TIA2_T1_DATA_T1_RC_MSK (0x3 << 16) |
| 301 | #define TIA_TIA2_T1_DATA_T1_RC(v) (((v) >> 16) & 0x3) |
| 302 | #define TIA_TIA2_T1_DATA_T1_DATA_MSK (0xFFFF << 0) |
| 303 | #define TIA_TIA2_T1_DATA_T1_DATA(v) (((v) >> 0) & 0xFFFF) |
| 304 | #define TIA_TIA2_T2_DATA (TIA_BASE + 0x00DC) |
| 305 | #define TIA_TIA2_T2_DATA_T2_RC_MSK (0x3 << 16) |
| 306 | #define TIA_TIA2_T2_DATA_T2_RC(v) (((v) >> 16) & 0x3) |
| 307 | #define TIA_TIA2_T2_DATA_T2_DATA_MSK (0xFFFF << 0) |
| 308 | #define TIA_TIA2_T2_DATA_T2_DATA(v) (((v) >> 0) & 0xFFFF) |
| 309 | #define TIA_TIA2_T3_DATA (TIA_BASE + 0x00E0) |
| 310 | #define TIA_TIA2_T3_DATA_T3_RC_MSK (0x3 << 16) |
| 311 | #define TIA_TIA2_T3_DATA_T3_RC(v) (((v) >> 16) & 0x3) |
| 312 | #define TIA_TIA2_T3_DATA_T3_DATA_MSK (0xFFFF << 0) |
| 313 | #define TIA_TIA2_T3_DATA_T3_DATA(v) (((v) >> 0) & 0xFFFF) |
| 314 | #define TIA_TIA2_DCXO_DATA (TIA_BASE + 0x00E4) |
| 315 | #define TIA_TIA2_DCXO_DATA_DCXO_DATA_MSK (0xFFFF << 0) |
| 316 | #define TIA_TIA2_DCXO_DATA_DCXO_DATA(v) (((v) >> 0) & 0xFFFF) |
| 317 | #define TIA_TIA2_SPMI_CMD (TIA_BASE + 0x00E8) |
| 318 | #define TIA_TIA2_SPMI_CMD_SPMI_CMD_MSK (0x3 << 0) |
| 319 | #define TIA_TIA2_SPMI_CMD_SPMI_CMD(n) (((n) << 0) & TIA_TIA2_SPMI_CMD_SPMI_CMD_MSK) |
| 320 | #define TIA_TIA2_SPMI_CMD_SPMI_PMIFID (1 << 2) |
| 321 | #define TIA_TIA2_SPMI_CMD_SPMI_BYTECNT (1 << 3) |
| 322 | #define TIA_TIA2_SPMI_CMD_SPMI_SLVID_MSK (0xF << 4) |
| 323 | #define TIA_TIA2_SPMI_CMD_SPMI_SLVID(n) (((n) << 4) & TIA_TIA2_SPMI_CMD_SPMI_SLVID_MSK) |
| 324 | #define TIA_TIA2_DEBUG (TIA_BASE + 0x00F0) |
| 325 | #define TIA_TIA2_DEBUG_MD_MD_TSX_DATA_READY (1 << 0) |
| 326 | #define TIA_TIA2_DEBUG_MD_T0_DATA_READY (1 << 1) |
| 327 | #define TIA_TIA2_DEBUG_MD_T1_DATA_READY (1 << 2) |
| 328 | #define TIA_TIA2_DEBUG_MD_T2_DATA_READY (1 << 3) |
| 329 | #define TIA_TIA2_DEBUG_MD_T3_DATA_READY (1 << 4) |
| 330 | #define TIA_TIA2_DEBUG_MD_GPS_TSX_DATA_READY (1 << 5) |
| 331 | #define TIA_TIA2_DEBUG_MD_DCXO_DATA_READY (1 << 6) |
| 332 | #define TIA_TIA2_DEBUG_GPS_MD_TSX_DATA_READY (1 << 7) |
| 333 | #define TIA_TIA2_DEBUG_GPS_T0_DATA_READY (1 << 8) |
| 334 | #define TIA_TIA2_DEBUG_GPS_T1_DATA_READY (1 << 9) |
| 335 | #define TIA_TIA2_DEBUG_GPS_T2_DATA_READY (1 << 10) |
| 336 | #define TIA_TIA2_DEBUG_GPS_T3_DATA_READY (1 << 11) |
| 337 | #define TIA_TIA2_DEBUG_GPS_GPS_TSX_DATA_READY (1 << 12) |
| 338 | #define TIA_TIA2_DEBUG_GPS_DCXO_DATA_READY (1 << 13) |
| 339 | #define TIA_TIA2_DEBUG_AP_MD_TSX_DATA_READY (1 << 14) |
| 340 | #define TIA_TIA2_DEBUG_AP_T0_DATA_READY (1 << 15) |
| 341 | #define TIA_TIA2_DEBUG_AP_T1_DATA_READY (1 << 16) |
| 342 | #define TIA_TIA2_DEBUG_AP_T2_DATA_READY (1 << 17) |
| 343 | #define TIA_TIA2_DEBUG_AP_T3_DATA_READY (1 << 18) |
| 344 | #define TIA_TIA2_DEBUG_AP_DCXO_DATA_READY (1 << 19) |
| 345 | #define TIA_TIA2_DEBUG_AP_GPS_TSX_DATA_READY (1 << 20) |
| 346 | #define TIA_TIA2_DEBUG_ST_FSM_MSK (0xF << 21) |
| 347 | #define TIA_TIA2_DEBUG_ST_FSM(v) (((v) >> 21) & 0xF) |
| 348 | #define TIA_TIA2_DEBUG_TR_FSM_MSK (0x7 << 25) |
| 349 | #define TIA_TIA2_DEBUG_TR_FSM(v) (((v) >> 25) & 0x7) |
| 350 | |
| 351 | //****************************************************************************** |
| 352 | // useful macro |
| 353 | //****************************************************************************** |
| 354 | // TIA ADC value, n = 0 ~ 3 |
| 355 | #define TIA_HW_RC_ADC(n) (TIA_M2N(TIA_TIA2_T0_DATA) + ((n) << 2)) |
| 356 | #define TIA_HW_RC_VAL(v) (((v) >> 16) & 0x3) |
| 357 | #define TIA_HW_ADC_VLD(v) (((v) >> 15) & 0x1) |
| 358 | #define TIA_HW_ADC_VAL(v) (((v) >> 0) & 0x7fff) |
| 359 | |
| 360 | // TOPRGU WDT_NONRST_REG2 for hw reset state record |
| 361 | // 4BIT[20:17]: MD TIA SW Thermal Reset Used |
| 362 | // https://wiki.mediatek.inc/display/ALPSStorage/Colgin+RGU+Usage |
| 363 | #define TOPRGU_WDT_NONRST_REG2 (BASE_INFRA_AO_TOPRGU + 0x24) |
| 364 | #define TOPRGU_TIA_STATUS_MSK (0xF << 17) |
| 365 | #define TOPRGU_TIA_STATUS(n) (((v) << 17) & TOPRGU_TIA_STATUS_MSK) |
| 366 | #define TOPRGU_TID_STATUS(tid) (0x1 << (17 + (tid))) |
| 367 | |
| 368 | #endif |