| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * sim_hw.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Maui_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file is intends for SIM driver. |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
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| 166 | *------------------------------------------------------------------------------ |
| 167 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 168 | *============================================================================ |
| 169 | ****************************************************************************/ |
| 170 | #ifdef __SIM_DRV_MULTI_DRV_ARCH__ |
| 171 | /*when __SIM_DRV_MULTI_DRV_ARCH__ is defined, we reorganize the header file to make all solutions built together*/ |
| 172 | #include "sim_drv_HW_reg_MTK.h" |
| 173 | #else |
| 174 | |
| 175 | /*RHR*/ |
| 176 | #include "reg_base.h" |
| 177 | /*RHR*/ |
| 178 | |
| 179 | #ifndef _SIM_HW_H |
| 180 | #define _SIM_HW_H |
| 181 | |
| 182 | |
| 183 | //#if ( (!defined(MT6208)) && (!defined(FPGA)) && (!defined(MT6205)) && (!defined(MT6205B)) && (!defined(MT6218)) ) |
| 184 | #if !defined(DRV_SIM_REG_6208_SERIES) && !defined(DRV_SIM_REG_6205B_SERIES) |
| 185 | /*MT6218B || MT6219 || MT6217 || MT6226 || MT6227 || MT6228 || MT6229*/ |
| 186 | |
| 187 | #ifdef SIM_NAMING_FROM_0_ADDRESS |
| 188 | |
| 189 | #ifdef SIM_base |
| 190 | #undef SIM_base |
| 191 | #endif |
| 192 | #define SIM_base SIM0_base |
| 193 | |
| 194 | #ifdef SIM2_base |
| 195 | #undef SIM2_base |
| 196 | #endif |
| 197 | #define SIM2_base SIM1_base |
| 198 | |
| 199 | #endif //SIM_NAMING_FROM_0_ADDRESS |
| 200 | |
| 201 | #ifdef SIM_DVT_ON_SIM2 |
| 202 | #undef SIM_base |
| 203 | #define SIM_base SIM2_base |
| 204 | #endif |
| 205 | |
| 206 | #define ACK_NULL_CHAR 0x60 |
| 207 | |
| 208 | #define SIM_CTRL (SIM_base+0x0) |
| 209 | #define SIM_CONF (SIM_base+0x4) |
| 210 | #define SIM_BRR (SIM_base+0x8) |
| 211 | #define SIM_IRQEN (SIM_base+0x10) |
| 212 | #define SIM_STS (SIM_base+0x14) |
| 213 | |
| 214 | #define SIM_RETRY (SIM_base+0x20) |
| 215 | #define SIM_TIDE (SIM_base+0x24) |
| 216 | |
| 217 | #define SIM_DATA (SIM_base+0x30) |
| 218 | #define SIM_COUNT (SIM_base+0x34) |
| 219 | |
| 220 | #define SIM_ATIME (SIM_base+0x40) |
| 221 | #define SIM_DTIME (SIM_base+0x44) |
| 222 | #define SIM_TOUT (SIM_base+0x48) |
| 223 | |
| 224 | #define SIM_INS (SIM_base+0x60) |
| 225 | #define SIM_IMP3 (SIM_base+0x64) |
| 226 | #define SIM_SW1 (SIM_base+0x68) |
| 227 | #define SIM_SW2 (SIM_base+0x6c) |
| 228 | #define SIM_REG_STATUS (SIM_base+0x74) |
| 229 | |
| 230 | //SIM_CTRL |
| 231 | #define SIM_CTRL_SIMON 0x0001 |
| 232 | #define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */ |
| 233 | #define SIM_CTRL_WRST 0x0004 /* Trigger a warm reset */ |
| 234 | |
| 235 | //SIM_CONF |
| 236 | #define SIM_CONF_RXHSK 0x0001 |
| 237 | #define SIM_CONF_TXHSK 0x0002 |
| 238 | #define SIM_CONF_CLKPO 0x0004 |
| 239 | #define SIM_CONF_SINV 0x0008 |
| 240 | #define SIM_CONF_SDIR 0x0010 |
| 241 | #define SIM_CONF_ODDPARITY 0x0020 |
| 242 | #define SIM_CONF_SIMSEL 0x0040 |
| 243 | #define SIM_CONF_TOUTEN 0x0080 |
| 244 | #define SIM_CONF_T0EN 0x0200 |
| 245 | #define SIM_CONF_HFEN 0x0400 |
| 246 | #define SIM_CONF_T1EN 0x0100 |
| 247 | |
| 248 | #define SIM_CONF_Direct 0x0000 |
| 249 | #define SIM_CONF_InDirect 0x0038 |
| 250 | |
| 251 | //SIM_BRR |
| 252 | #define SIM_BRR_CLKMSK 0x0003 |
| 253 | #define SIM_BRR_CLK_Div2 0x0000 |
| 254 | #define SIM_BRR_CLK_Div4 0x0001 |
| 255 | #define SIM_BRR_CLK_Div8 0x0002 |
| 256 | #define SIM_BRR_CLK_Div12 0x0003 |
| 257 | |
| 258 | #define SIM_BRR_ETUMSK 0x07FC |
| 259 | #define SIM_BRR_BAUDMSK 0x000C |
| 260 | //#if ( (defined(MT6218B)) || (defined(MT6219))) |
| 261 | #if defined(DRV_SIM_REG_BAUD_6218B_SERIES) |
| 262 | #define SIM_BRR_BAUD_Div372 (0x16<<2) //F=372, D=1 |
| 263 | #define SIM_BRR_BAUD_Div64 (0x03<<2) //F=512, D=8 |
| 264 | #define SIM_BRR_BAUD_Div32 (0x01<<2) //F=512, D=16 |
| 265 | #else /*!Mt6218B,MT6219*/ |
| 266 | #define SIM_BRR_BAUD_Div372 (372<<2) //F=372, D=1 |
| 267 | #define SIM_BRR_BAUD_Div64 (64<<2) //F=512, D=8 |
| 268 | #define SIM_BRR_BAUD_Div32 (32<<2) //F=512, D=16 |
| 269 | #define SIM_BRR_BAUD_Div16 (16<<2) //F=512,D=32 |
| 270 | #endif /*MT6218B,MT6219*/ |
| 271 | |
| 272 | //SIM_IRQEN |
| 273 | #define SIM_IRQEN_TX 0x0001 |
| 274 | #define SIM_IRQEN_RX 0x0002 |
| 275 | #define SIM_IRQEN_OV 0x0004 |
| 276 | #define SIM_IRQEN_TOUT 0x0008 |
| 277 | #define SIM_IRQEN_TXERR 0x0010 |
| 278 | #define SIM_IRQEN_NATR 0x0020 |
| 279 | #define SIM_IRQEN_SIMOFF 0x0040 |
| 280 | #define SIM_IRQEN_T0END 0x0080 |
| 281 | #define SIM_IRQEN_RXERR 0x0100 |
| 282 | |
| 283 | #define SIM_IRQEN_ALL 0x01bf |
| 284 | #define SIM_IRQEN_ALLOFF 0x0000 |
| 285 | /* SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT,SIM_IRQEN_OV,SIM_IRQEN_RX*/ |
| 286 | #define SIM_IRQEN_Normal 0x013e |
| 287 | /*SIM_IRQEN_T0END,SIM_IRQEN_TXErr,SIM_IRQEN_TOUT*/ |
| 288 | #define SIM_IRQEN_CMDNormal 0x019e |
| 289 | /*#define SIM_IRQEN_CMDNormal 0x019c*/ |
| 290 | #define SIM_IRQEN_CMDDMANormal 0x019c |
| 291 | #define USIM_IRQEN_ATR (SIM_IRQEN_RX|SIM_IRQEN_NATR) |
| 292 | #define USIM_IRQEN_NORMAL (SIM_STS_RX|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_TXERR|SIM_STS_RXERR) |
| 293 | #define USIM_IRQEN_CMD_T1 (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_RXERR| \ |
| 294 | SIM_STS_OV|SIM_STS_TOUT) |
| 295 | #define USIM_IRQEN_CMD_T1_RX (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_RX) |
| 296 | #define USIM_IRQEN_CMD_T1_TX (SIM_STS_T1END) |
| 297 | |
| 298 | //SIM_STS |
| 299 | #define SIM_STS_TX 0x0001 |
| 300 | #define SIM_STS_RX 0x0002 |
| 301 | #define SIM_STS_OV 0x0004 |
| 302 | #define SIM_STS_TOUT 0x0008 |
| 303 | #define SIM_STS_TXERR 0x0010 |
| 304 | #define SIM_STS_NATR 0x0020 |
| 305 | #define SIM_STS_SIMOFF 0x0040 |
| 306 | #define SIM_STS_T0END 0x0080 |
| 307 | #define SIM_STS_RXERR 0x0100 |
| 308 | #define SIM_STS_T1END 0x0200 |
| 309 | #define SIM_STS_EDCERR 0x0400 |
| 310 | |
| 311 | //SIM_TOUT |
| 312 | #define SIM_TOUT_MSK 0x3fff |
| 313 | |
| 314 | //SIM_RETRY |
| 315 | #define SIM_RETRY_RXMASK 0x0007 |
| 316 | #define SIM_RETRY_TXMASK 0x0700 |
| 317 | |
| 318 | //SIM_TIDE |
| 319 | #define SIM_TIDE_RXMASK 0x000f |
| 320 | #define SIM_TIDE_TXMASK 0x0f00 |
| 321 | |
| 322 | //SIM_COUNT |
| 323 | #define SIM_COUNT_MASK 0x000f |
| 324 | |
| 325 | //SIM_INS |
| 326 | #define SIM_INS_MASK 0x00ff |
| 327 | #define SIM_INS_INSD 0x0100 |
| 328 | |
| 329 | //SIM_IMP3 |
| 330 | #define SIM_IMP3_MASK 0x01ff |
| 331 | |
| 332 | // SIM_STATUS |
| 333 | #define SIM_STATUS_EDC 0x40 |
| 334 | #define SIM_STATUS_ACK 0x20 |
| 335 | #define SIM_STATUS_NACK 0x10 |
| 336 | #define SIM_STATUS_IDLE 0x01 |
| 337 | #define SIM_STATUS_INS 0x02 |
| 338 | #define SIM_STATUS_SW1 0x04 |
| 339 | #define SIM_STATUS_SW2 0x08 |
| 340 | |
| 341 | #define SIM_TX_DELAY_LEN 0x4 |
| 342 | #define SIM_TX_DELAY_LOOP 4000 |
| 343 | #endif /*MT6218B*/ |
| 344 | |
| 345 | //#if ( (defined(MT6205)) || (defined(MT6205B)) || (defined(MT6218)) ) |
| 346 | #if defined(DRV_SIM_REG_6205B_SERIES) |
| 347 | #define ACK_NULL_CHAR 0x60 |
| 348 | |
| 349 | #define SIM_CTRL (SIM_base+0x0) |
| 350 | #define SIM_CONF (SIM_base+0x4) |
| 351 | #define SIM_BRR (SIM_base+0x8) |
| 352 | #define SIM_IRQEN (SIM_base+0xc) |
| 353 | #define SIM_STS (SIM_base+0x10) |
| 354 | #define SIM_DATA (SIM_base+0x14) |
| 355 | #define SIM_TOUT (SIM_base+0x18) |
| 356 | #define SIM_RETRY (SIM_base+0x1c) |
| 357 | #define SIM_TIDE (SIM_base+0x20) |
| 358 | #define SIM_COUNT (SIM_base+0x24) |
| 359 | #define SIM_ATIME (SIM_base+0x28) |
| 360 | #define SIM_DTIME (SIM_base+0x2C) |
| 361 | #define SIM_INS (SIM_base+0x30) |
| 362 | #define SIM_IMP3 (SIM_base+0x34) |
| 363 | #define SIM_SW1 (SIM_base+0x38) |
| 364 | #define SIM_SW2 (SIM_base+0x3c) |
| 365 | |
| 366 | |
| 367 | //SIM_CTRL |
| 368 | #define SIM_CTRL_SIMON 0x0001 |
| 369 | #define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */ |
| 370 | #define SIM_CTRL_WRST 0x0004 /* Trigger a warm reset */ |
| 371 | |
| 372 | //SIM_CONF |
| 373 | #define SIM_CONF_RXHSK 0x0001 |
| 374 | #define SIM_CONF_TXHSK 0x0002 |
| 375 | #define SIM_CONF_CLKPO 0x0004 |
| 376 | #define SIM_CONF_SINV 0x0008 |
| 377 | #define SIM_CONF_SDIR 0x0010 |
| 378 | #define SIM_CONF_ODDPARITY 0x0020 |
| 379 | #define SIM_CONF_SIMSEL 0x0040 |
| 380 | #define SIM_CONF_TOUTEN 0x0080 |
| 381 | #define SIM_CONF_HALTEN 0x0100 |
| 382 | #define SIM_CONF_T0EN 0x0200 |
| 383 | #define SIM_CONF_HFEN 0x0400 |
| 384 | |
| 385 | #define SIM_CONF_Direct 0x0000 |
| 386 | #define SIM_CONF_InDirect 0x0038 |
| 387 | |
| 388 | //SIM_BRR |
| 389 | #define SIM_BRR_CLKMSK 0x0003 |
| 390 | #define SIM_BRR_CLK_Div2 0x0000 |
| 391 | #define SIM_BRR_CLK_Div4 0x0001 |
| 392 | #define SIM_BRR_CLK_Div8 0x0002 |
| 393 | #define SIM_BRR_CLK_Div12 0x0003 |
| 394 | |
| 395 | #define SIM_BRR_ETUMSK 0x07FC |
| 396 | #define SIM_BRR_BAUDMSK 0x000C |
| 397 | //#ifdef MT6205B |
| 398 | #if defined(DRV_SIM_REG_BAUD_6205B) |
| 399 | #define SIM_BRR_BAUD_Div372 0x000c //F=372, D=1 |
| 400 | #define SIM_BRR_BAUD_Div368 0x0000 //F=368, D=1 |
| 401 | #else /*!MT6205B*/ |
| 402 | #define SIM_BRR_BAUD_Div372 0x0000 //F=372, D=1 |
| 403 | #endif /*MT6205B*/ |
| 404 | #define SIM_BRR_BAUD_Div64 0x0004 //F=512, D=8 |
| 405 | #define SIM_BRR_BAUD_Div32 0x0008 //F=512, D=16 |
| 406 | |
| 407 | //SIM_IRQEN |
| 408 | #define SIM_IRQEN_TX 0x0001 |
| 409 | #define SIM_IRQEN_RX 0x0002 |
| 410 | #define SIM_IRQEN_OV 0x0004 |
| 411 | #define SIM_IRQEN_TOUT 0x0008 |
| 412 | #define SIM_IRQEN_TXERR 0x0010 |
| 413 | #define SIM_IRQEN_NATR 0x0020 |
| 414 | #define SIM_IRQEN_SIMOFF 0x0040 |
| 415 | #define SIM_IRQEN_T0END 0x0080 |
| 416 | #define SIM_IRQEN_RXERR 0x0100 |
| 417 | |
| 418 | #define SIM_IRQEN_ALL 0x01bf |
| 419 | #define SIM_IRQEN_ALLOFF 0x0000 |
| 420 | /* SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT,SIM_IRQEN_OV,SIM_IRQEN_RX*/ |
| 421 | #define SIM_IRQEN_Normal 0x013e |
| 422 | /*SIM_IRQEN_T0END,SIM_IRQEN_TXErr,SIM_IRQEN_TOUT*/ |
| 423 | #define SIM_IRQEN_CMDNormal 0x019e |
| 424 | /*#define SIM_IRQEN_CMDNormal 0x019c*/ |
| 425 | #define SIM_IRQEN_CMDDMANormal 0x019c |
| 426 | |
| 427 | //SIM_STS |
| 428 | #define SIM_STS_TX 0x0001 |
| 429 | #define SIM_STS_RX 0x0002 |
| 430 | #define SIM_STS_OV 0x0004 |
| 431 | #define SIM_STS_TOUT 0x0008 |
| 432 | #define SIM_STS_TXERR 0x0010 |
| 433 | #define SIM_STS_NATR 0x0020 |
| 434 | #define SIM_STS_SIMOFF 0x0040 |
| 435 | #define SIM_STS_T0END 0x0080 |
| 436 | #define SIM_STS_RXERR 0x0100 |
| 437 | |
| 438 | //SIM_TOUT |
| 439 | #define SIM_TOUT_MSK 0x3fff |
| 440 | |
| 441 | //SIM_RETRY |
| 442 | #define SIM_RETRY_RXMASK 0x0007 |
| 443 | #define SIM_RETRY_TXMASK 0x0700 |
| 444 | |
| 445 | //SIM_TIDE |
| 446 | #define SIM_TIDE_RXMASK 0x000f |
| 447 | #define SIM_TIDE_TXMASK 0x0f00 |
| 448 | |
| 449 | //SIM_COUNT |
| 450 | #define SIM_COUNT_MASK 0x000f |
| 451 | |
| 452 | //SIM_INS |
| 453 | #define SIM_INS_MASK 0x00ff |
| 454 | #define SIM_INS_INSD 0x0100 |
| 455 | |
| 456 | //SIM_IMP3 |
| 457 | #define SIM_IMP3_MASK 0x01ff |
| 458 | #endif /*(MT6205,MT6205B,MT6218)*/ |
| 459 | |
| 460 | //#if ( (defined(MT6208)) || (defined(FPGA)) ) |
| 461 | #if defined(DRV_SIM_MT6208_SERIES) |
| 462 | #define MAX_FIFO_SIZE 31 |
| 463 | #define ACK_NULL_CHAR 0x60 |
| 464 | |
| 465 | #define LISR_COMPLETE 0x80 |
| 466 | |
| 467 | #define SIM_CTRL (SIM_base+0x0) |
| 468 | #define SIM_CONF (SIM_base+0x4) |
| 469 | #define SIM_BRR (SIM_base+0x8) |
| 470 | #define SIM_IRQEN (SIM_base+0xc) |
| 471 | #define SIM_STS (SIM_base+0x10) |
| 472 | #define SIM_DATA (SIM_base+0x14) |
| 473 | #define SIM_TOUT (SIM_base+0x18) |
| 474 | #define SIM_RETRY (SIM_base+0x1c) |
| 475 | #define SIM_TIDE (SIM_base+0x20) |
| 476 | #define SIM_COUNT (SIM_base+0x24) |
| 477 | #define SIM_ATIME (SIM_base+0x28) |
| 478 | #define SIM_DTIME (SIM_base+0x2C) |
| 479 | |
| 480 | |
| 481 | //SIM_CTRL |
| 482 | #define SIM_CTRL_SIMON 0x0001 |
| 483 | #define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */ |
| 484 | |
| 485 | //SIM_CONF |
| 486 | #define SIM_CONF_RXHSK 0x0001 |
| 487 | #define SIM_CONF_TXHSK 0x0002 |
| 488 | #define SIM_CONF_CLKPO 0x0004 |
| 489 | #define SIM_CONF_SINV 0x0008 |
| 490 | #define SIM_CONF_SDIR 0x0010 |
| 491 | #define SIM_CONF_ODDPARITY 0x0020 |
| 492 | #define SIM_CONF_SIMSEL 0x0040 |
| 493 | #define SIM_CONF_TOUTEN 0x0080 |
| 494 | |
| 495 | #define SIM_CONF_Direct 0x0000 |
| 496 | #define SIM_CONF_InDirect 0x0038 |
| 497 | |
| 498 | //SIM_BRR |
| 499 | #define SIM_BRR_CLKMSK 0x0003 |
| 500 | #define SIM_BRR_CLK_Div2 0x0000 |
| 501 | #define SIM_BRR_CLK_Div4 0x0001 |
| 502 | #define SIM_BRR_CLK_Div8 0x0002 |
| 503 | #define SIM_BRR_CLK_Div12 0x0003 |
| 504 | |
| 505 | #define SIM_BRR_ETUMSK 0x07FC |
| 506 | #define SIM_BRR_BAUDMSK 0x000C |
| 507 | #define SIM_BRR_BAUD_Div372 0x0000 //F=372, D=1 |
| 508 | #define SIM_BRR_BAUD_Div64 0x0004 //F=512, D=8 |
| 509 | #define SIM_BRR_BAUD_Div32 0x0008 //F=512, D=16 |
| 510 | |
| 511 | //SIM_IRQEN |
| 512 | #define SIM_IRQEN_TX 0x0001 |
| 513 | #define SIM_IRQEN_RX 0x0002 |
| 514 | #define SIM_IRQEN_OV 0x0004 |
| 515 | #define SIM_IRQEN_TOUT 0x0008 |
| 516 | #define SIM_IRQEN_TXERR 0x0010 |
| 517 | #define SIM_IRQEN_NATR 0x0020 |
| 518 | #define SIM_IRQEN_SIMOFF 0x0040 |
| 519 | |
| 520 | #define SIM_IRQEN_ALL 0x01bf |
| 521 | #define SIM_IRQEN_ALLOFF 0x0000 |
| 522 | /* SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT,SIM_IRQEN_OV,SIM_IRQEN_RX*/ |
| 523 | #define SIM_IRQEN_Normal 0x03e |
| 524 | |
| 525 | //SIM_STS |
| 526 | |
| 527 | #define SIM_STS_TX 0x0001 |
| 528 | #define SIM_STS_RX 0x0002 |
| 529 | #define SIM_STS_OV 0x0004 |
| 530 | #define SIM_STS_TOUT 0x0008 |
| 531 | #define SIM_STS_TXERR 0x0010 |
| 532 | #define SIM_STS_NATR 0x0020 |
| 533 | #define SIM_STS_SIMOFF 0x0040 |
| 534 | |
| 535 | //SIM_DATA |
| 536 | #define SIM_DATA_DATAMSK 0x00ff |
| 537 | #define SIM_DATA_PARITY 0x0100 |
| 538 | |
| 539 | //SIM_TOUT |
| 540 | #define SIM_TOUT_MSK 0x3fff |
| 541 | |
| 542 | //SIM_RETRY |
| 543 | #define SIM_RETRY_RXMASK 0x0007 |
| 544 | #define SIM_RETRY_TXMASK 0x0700 |
| 545 | |
| 546 | //SIM_TIDE |
| 547 | #define SIM_TIDE_RXMASK 0x001f |
| 548 | #define SIM_TIDE_TXMASK 0x1f00 |
| 549 | |
| 550 | //SIM_TXCNT |
| 551 | #define SIM_COUNT_MASK 0x001f |
| 552 | #endif /*(MT6208,FPGA)*/ |
| 553 | |
| 554 | #endif /*_SIM_HW_H*/ |
| 555 | |
| 556 | #endif /*__SIM_DRV_MULTI_DRV_ARCH__*/ |