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rjw6c1fd8f2022-11-30 14:33:01 +08001/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
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34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * adc_hw.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file is intends for adc driver.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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138 *------------------------------------------------------------------------------
139 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
140 *============================================================================
141 ****************************************************************************/
142#ifndef _ADC_HW_H
143#define _ADC_HW_H
144#include "drv_features_adc.h"
145#include "drvpdn.h"
146
147#if defined(DRV_ADC_6236_SERIES)
148/*
149MT6236 BASE=0x801c_0000
150Check bit of ADC (1b) *(BASE+0x0020)[13]=[333]
151ADC_B (6b) *(BASE+0x0020)[12:7]=[332:327]
152ADC_A (7b) *(BASE+0x0020)[6:0]=[326:320]
153*/
154#define EFUSE_ADC_BASE 0x801c0020
155#define EFUSE_ADC_A 0x801c0020
156#define EFUSE_ADC_B 0x801c0020
157#define EFUSE_ADC_ENABLE 0x2000
158#define EFUSE_ADC_A_MASK 0x7F
159#define EFUSE_ADC_B_MASK 0x1F80
160#define EFUSE_ADC_A_SHIFT 0
161#define EFUSE_ADC_B_SHIFT 7
162
163#elif defined(DRV_ADC_6252_SERIES)
164/*
165MT6252 BASE=0x8000_0000
166Check bit of ADC (1b), *(BASE+0x0020)[13]=[333]
167ADC_B (6b), *(BASE+0x0020)[12:7]=[332:327]
168ADC_A (7b), *(BASE+0x0020)[6:0]=[326:320]
169*/
170#define EFUSE_ADC_BASE 0x80000020
171#define EFUSE_ADC_A 0x80000020
172#define EFUSE_ADC_B 0x80000020
173#define EFUSE_ADC_ENABLE 0x2000
174#define EFUSE_ADC_A_MASK 0x7F
175#define EFUSE_ADC_B_MASK 0x1F80
176#define EFUSE_ADC_A_SHIFT 0
177#define EFUSE_ADC_B_SHIFT 7
178
179#elif defined(DRV_ADC_6251_SERIES)
180
181#define EFUSE_ADC_BASE 0x80000100
182#define EFUSE_ADC_A 0x80000100
183#define EFUSE_ADC_B 0x80000100
184#define EFUSE_ADC_ENABLE 0x0002
185#define EFUSE_ADC_A_MASK 0x7FC00
186#define EFUSE_ADC_B_MASK 0x3FC
187#define EFUSE_ADC_A_SHIFT 10
188#define EFUSE_ADC_B_SHIFT 2
189
190#elif defined(DRV_ADC_6256_SERIES)
191
192#define EFUSE_ADC_BASE 0x80000100
193#define EFUSE_ADC_A 0x80000100
194#define EFUSE_ADC_B 0x80000100
195#define EFUSE_ADC_ENABLE 0x0002
196#define EFUSE_ADC_A_MASK 0x7FC00
197#define EFUSE_ADC_B_MASK 0x3FC
198#define EFUSE_ADC_A_SHIFT 10
199#define EFUSE_ADC_B_SHIFT 2
200
201#elif defined(DRV_ADC_6575_SERIES)
202
203#define EFUSE_ADC_BASE 0xC1019040
204#define EFUSE_ADC_ENABLE 0x0
205#define EFUSE_O_VBG 0xC1019040
206#define EFUSE_O_VBG_MASK 0x1FF00
207#define EFUSE_O_VBG_SHIFT 0x8
208#define EFUSE_ADC_OE 0xC1019044
209#define EFUSE_ADC_OE_MASK 0xFF
210#define EFUSE_ADC_OE_SHIFT 0
211#define EFUSE_ADC_GE 0xC1019048
212#define EFUSE_ADC_GE_MASK 0xFF
213#define EFUSE_ADC_GE_SHIFT 0
214
215#define TS_CON1 0xC0007804
216#define TS_CON2 0xC0007808
217
218#elif defined(DRV_ADC_6250_SERIES) // 10 bits ADC
219
220#define EFUSE_ADC_BASE 0xA01C0200
221#define EFUSE_ADC_A 0xA01C0200
222#define EFUSE_ADC_B 0xA01C0200
223#define EFUSE_ADC_ENABLE 0x0002
224#define EFUSE_ADC_A_MASK 0x1FC00 // 7 bits
225#define EFUSE_ADC_B_MASK 0xFC // 6 bits
226#define EFUSE_ADC_A_SHIFT 10
227#define EFUSE_ADC_B_SHIFT 2
228
229
230#else
231/*
2321. Check bit of ADC (1b), *(0x80000020)[18]=[210]
2332. ADC_B (6b), *(0x80000020)[17:12]=[209:204]
2343. ADC_A (7b), *(0x80000020)[11:5]=[203:197]
235*/
236#define EFUSE_ADC_BASE 0x80000020
237#define EFUSE_ADC_A 0x80000020
238#define EFUSE_ADC_B 0x80000020
239#define EFUSE_ADC_ENABLE 0x40000
240#define EFUSE_ADC_A_MASK 0xFE0
241#define EFUSE_ADC_B_MASK 0x3F000
242#define EFUSE_ADC_A_SHIFT 5
243#define EFUSE_ADC_B_SHIFT 12
244
245#endif
246
247#if defined(DRV_ADC_LIMIT_REG) || defined(FPGA)
248#if !defined(DRV_ADC_OFF)
249 /*******************
250 * GPADC Registers *
251 *******************/
252 #define AUXADC_DATA (AUXADC_base+0x0000) /* Sampled data */
253 #define AUXADC_CTRL (AUXADC_base+0x0004) /* Control of A/D Converter */
254 #define AUXADC_STAT (AUXADC_base+0x0008) /* A/D Status..reg=0,if write AUXADC_CTRL reg*/
255 #define AUXADC_CTRL2 (AUXADC_base+0x000c) /* Special Control of A/D Converter */
256
257 #define AUXADC_STAT_RDY 0x0001 /*ADC ready*/
258
259 #define AUXADC_CTRL2_CALI 0x0001 /*ADC Calibration*/
260 #define AUXADC_CTRL2_MON 0x0020 /*DACMON*/
261 #define AUXADC_CTRL2_BYP 0x0040 /*DACBYP*/
262#endif // #if !defined(DRV_ADC_OFF)
263
264 /*ADC pin selection, ADC phy. channel*/
265
266 #define ADC_MAX_CHANNEL 5
267 #define ADC_ERR_CHANNEL_NO 50
268#endif /*(DRV_ADC_LIMIT_REG,FPGA)*/
269/*************************************************************************/
270#if defined(DRV_ADC_BASIC_REG)
271#if !defined(DRV_ADC_OFF)
272 #define AUXADC_SYNC (AUXADC_base+0x0000)
273 #define AUXADC_IMM (AUXADC_base+0x0004)
274#if defined(DRV_ADC_6575_SERIES)
275 #define AUXADC_CON1_SET (AUXADC_base+0x0008)
276 #define AUXADC_CON1_CLR (AUXADC_base+0x000C)
277 #define AUXADC_SYN (AUXADC_base+0x0010)
278 #define AUXADC_CON (AUXADC_base+0x0014)
279 #define AUXADC_DAT(_line) (AUXADC_base+0x0018+(4*_line))
280#else
281 #define AUXADC_SYN (AUXADC_base+0x0008)
282 #define AUXADC_CON (AUXADC_base+0x000c)
283 #define AUXADC_DAT(_line) (AUXADC_base+0x0010+(4*_line))
284#endif
285
286#if defined(DRV_ADC_6256_SERIES)
287 #define AUX_CON2 (PLL_base+0x1708)
288#else
289 #define AUX_CON2 (ABBSYS_base+0x8708)
290#endif
291
292#if defined(DRV_ADC_6250_SERIES)
293
294 #define ABBA_WR_PATH0 (ABBSYS_base + 0x0)
295 #define ABB_WR_PATH0 (ABB_D_base + 0x0010)
296 #define ABB_AUX_CON0 (ABB_D_base + 0x0028)
297 #define ABB_RSV_CON1 (ABB_D_base + 0x0004)
298 #define AUXADC_TS_CON (AUXADC_base + 0x0058)
299
300
301 #define ABBA_AUX_PWDB 0x0100
302 #define F26M_CLK_EN 0x8000
303 #define AUX_PWDB 0x0100
304 #define AUX_FIFO_CLK_EN 0x8000
305 #define AUX_FIFO_EN 0x0080
306 #define AUXADC_FSM_CTRL 0x0040
307 #define AUXADC_26M_CLK_CTRL 0x0004
308 #define AUXADC_TP_SPL 0x0001
309#endif
310
311 /*AUXADC_SYNC*/
312 #define AUXADC_SYNC_CHAN(_line) (0x0001<<_line) /*Time event 1*/
313
314 /*AUXADC_IMM*/
315 #define AUXADC_IMM_CHAN(_line) (0x0001<<_line)
316
317 /*AUXADC_SYN*/
318 #define AUXADC_SYN_BIT (0x0001) /*Time event 0*/
319
320 /*AUXADC_CON*/
321 #define AUXADC_CON_RUN (0x0001)
322#ifndef DRV_ADC_NO_TEST_DACMON
323 #define AUXADC_CON_CALI_MASK (0x007c)
324 #define AUXADC_CON_TESTDACMON (0x0080)
325#endif // #ifndef DRV_ADC_NO_TEST_DACMON
326#if defined(DRV_ADC_SW_RESET)
327 #define AUXADC_CON_SW_RESET (0x0080)
328#endif // #if defined(DRV_ADC_SW_RESET)
329 #define AUXADC_CON_AUTOCLR0 (0x0100)
330 #define AUXADC_CON_AUTOCLR1 (0x0200)
331 #define AUXADC_CON_PUWAIT_EN (0x0800)
332 #define AUXADC_CON_AUTOSET (0x8000)
333#endif // #if !defined(DRV_ADC_OFF)
334
335
336 #define ADC_ERR_CHANNEL_NO 50
337#endif /*(MT6205B,MT6218)*/
338
339#if ( defined(DRV_ADC_BASIC_REG) || defined(DRV_ADC_TDMA_TIME) )
340#if !defined(DRV_ADC_OFF)
341 #if defined(DRV_ADC_TDMA_EVENT_REG_POS1)
342 #define AUXADC_TDMA_EVENT0 (TDMA_base+0x1c0)
343 #define AUXADC_TDMA_EVENT1 (TDMA_base+0x1c4)
344 #elif defined(DRV_ADC_TDMA_EVENT_REG_POS2)
345 #define AUXADC_TDMA_EVENT0 (TDMA_base+0x400)
346
347 #if defined(MT6229_S00)
348 #define AUXADC_TDMA_EVENT1 (TDMA_base+0x400)/*HW bug*/
349 #else
350 #define AUXADC_TDMA_EVENT1 (TDMA_base+0x404)/**/
351 #endif
352
353 #else
354 #define AUXADC_TDMA_EVENT0 (TDMA_base+0x1b0)
355 #define AUXADC_TDMA_EVENT1 (TDMA_base+0x1b4)
356 #endif
357
358 #if defined(DRV_ADC_TDMA_EN_REG_POS1)
359 #define AUXADC_TDMA_EN (TDMA_base+0x16C)
360 #else
361 #define AUXADC_TDMA_EN (TDMA_base+0x164)
362 #endif
363 /*AUXADC_TDMA_EN*/
364 #define AUXADC_TDMA_EN_EVT0 (0x0001)
365 #define AUXADC_TDMA_EN_EVT1 (0x0002)
366#endif // #if !defined(DRV_ADC_OFF)
367#endif // #if ( defined(DRV_ADC_BASIC_REG) || defined(DRV_ADC_TDMA_TIME) )
368
369
370#if defined(__OLD_PDN_ARCH__)
371#if defined(ADC_CG_PDN_CON0)
372 #if defined(__OLD_PDN_DEFINE__)
373 #define ADC_CG_PDN_CON_ADDR (DRVPDN_CON0)
374 #define ADC_CG_PDN_CON_BIT (DRVPDN_CON0_AUXADC)
375 #elif defined(__CLKG_DEFINE__) // #if defined(__OLD_PDN_DEFINE__)
376 #define ADC_CG_PDN_CON_ADDR (CG_CON0)
377 #define ADC_CG_PDN_CON_BIT (CG_CON0_AUXADC)
378 #endif // #if defined(__OLD_PDN_DEFINE__)
379
380#elif defined(ADC_CG_PDN_CON1) // #if defined(ADC_CG_PDN_CON0)
381 #if defined(__OLD_PDN_DEFINE__)
382 #define ADC_CG_PDN_CON_ADDR (DRVPDN_CON1)
383 #define ADC_CG_PDN_CON_BIT (DRVPDN_CON1_AUXADC)
384 #elif defined(__CLKG_DEFINE__) // #if defined(__OLD_PDN_DEFINE__)
385 #define ADC_CG_PDN_CON_ADDR (CG_CON1)
386 #define ADC_CG_PDN_CON_BIT (CG_CON1_AUXADC)
387 #endif // #if defined(__OLD_PDN_DEFINE__)
388#elif defined(ADC_CG_PDN_CON3) // #if defined(ADC_CG_PDN_CON0)
389 #if defined(__OLD_PDN_DEFINE__)
390 #define ADC_CG_PDN_CON_ADDR (DRVPDN_CON3)
391 #define ADC_CG_PDN_CON_BIT (DRVPDN_CON3_AUXADC)
392 #elif defined(__CLKG_DEFINE__) // #if defined(__OLD_PDN_DEFINE__)
393 #define ADC_CG_PDN_CON_ADDR (CG_CON3)
394 #define ADC_CG_PDN_CON_BIT (CG_CON3_AUXADC)
395 #endif // #if defined(__OLD_PDN_DEFINE__)
396#else // #if defined(ADC_CG_PDN_CON0)
397 #if defined(__OLD_PDN_DEFINE__)
398 #define ADC_CG_PDN_CON_ADDR (DRVPDN_CON2)
399 #define ADC_CG_PDN_CON_BIT (DRVPDN_CON2_AUXADC)
400 #elif defined(__CLKG_DEFINE__) // #if defined(__OLD_PDN_DEFINE__)
401 #define ADC_CG_PDN_CON_ADDR (CG_CON2)
402 #define ADC_CG_PDN_CON_BIT (CG_CON2_AUXADC)
403 #endif // #if defined(__OLD_PDN_DEFINE__)
404#endif // #if defined(ADC_CG_PDN_CON0)
405#endif // #if defined(__OLD_PDN_ARCH__)
406
407
408#if defined(DRV_ADC_NOT_EXIST)
409 #define ADC_ERR_CHANNEL_NO 50
410#endif // #if defined(DRV_ADC_NOT_EXIST)
411
412#if !defined(DRV_ADC_OFF)
413#if !defined(ADC_MAX_CHANNEL)
414 #define ADC_MAX_CHANNEL 1
415 #define ADC_ERR_CHANNEL_NO 50
416#endif // #if defined(DRV_ADC_NOT_EXIST)
417#endif // #if !defined(DRV_ADC_OFF)
418
419#endif /*_ADC_HW_H*/
420