| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2011 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * dcl_pmu6327_hw.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Maui_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file is for PMIC6327 H/W configuration. |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
| 58 | * removed! |
| 59 | * removed! |
| 60 | * removed! |
| 61 | * |
| 62 | * removed! |
| 63 | * removed! |
| 64 | * removed! |
| 65 | * |
| 66 | * removed! |
| 67 | * removed! |
| 68 | * removed! |
| 69 | * |
| 70 | * removed! |
| 71 | * removed! |
| 72 | * removed! |
| 73 | *------------------------------------------------------------------------------ |
| 74 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 75 | *============================================================================ |
| 76 | ****************************************************************************/ |
| 77 | |
| 78 | |
| 79 | #ifndef __DCL_PMIC6327_HW_H_STRUCT__ |
| 80 | #define __DCL_PMIC6327_HW_H_STRUCT__ |
| 81 | |
| 82 | |
| 83 | #include "dcl_pmic_features.h" |
| 84 | |
| 85 | #if defined(PMIC_6327_REG_API) |
| 86 | #define PMIC_BANK0 0 |
| 87 | |
| 88 | #define PMIC6327_E1_VERSION 0x01 |
| 89 | |
| 90 | #define PMIC6327_E1_CID_CODE 0x27 |
| 91 | |
| 92 | //RegisterTOP |
| 93 | |
| 94 | // (0x000) CID0 |
| 95 | // (RO) |
| 96 | #define CID0_ADDR 0x00 |
| 97 | #define CID0_MASK 0xFF |
| 98 | #define CID0_SHIFT 0 |
| 99 | |
| 100 | // (0x001) I2C0 |
| 101 | // (RW) |
| 102 | #define SDA_DE_ADDR 0x01 |
| 103 | #define SDA_DE_MASK 0xF0 |
| 104 | #define SDA_DE_SHIFT 4 |
| 105 | |
| 106 | // (RW) |
| 107 | #define SCL_DE_ADDR 0x01 |
| 108 | #define SCL_DE_MASK 0x0F |
| 109 | #define SCL_DE_SHIFT 0 |
| 110 | |
| 111 | // (0x002) STATUS0 |
| 112 | // (RO) |
| 113 | #define VMD_STATUS_ADDR 0x02 |
| 114 | #define VMD_STATUS_MASK 0x80 |
| 115 | #define VMD_STATUS_SHIFT 7 |
| 116 | |
| 117 | // (RO) |
| 118 | #define VIO18_STATUS_ADDR 0x02 |
| 119 | #define VIO18_STATUS_MASK 0x20 |
| 120 | #define VIO18_STATUS_SHIFT 5 |
| 121 | |
| 122 | // (RO) |
| 123 | #define VRF18_STATUS_ADDR 0x02 |
| 124 | #define VRF18_STATUS_MASK 0x10 |
| 125 | #define VRF18_STATUS_SHIFT 4 |
| 126 | |
| 127 | // (RO) |
| 128 | #define VTCXO_STATUS_ADDR 0x02 |
| 129 | #define VTCXO_STATUS_MASK 0x02 |
| 130 | #define VTCXO_STATUS_SHIFT 1 |
| 131 | |
| 132 | // (RO) |
| 133 | #define VA25_STATUS_ADDR 0x02 |
| 134 | #define VA25_STATUS_MASK 0x01 |
| 135 | #define VA25_STATUS_SHIFT 0 |
| 136 | |
| 137 | // (0x003) STATUS1 |
| 138 | // (RO) |
| 139 | #define VM_STATUS_ADDR 0x03 |
| 140 | #define VM_STATUS_MASK 0x40 |
| 141 | #define VM_STATUS_SHIFT 6 |
| 142 | |
| 143 | // (RO) |
| 144 | #define VSIM_STATUS_ADDR 0x03 |
| 145 | #define VSIM_STATUS_MASK 0x08 |
| 146 | #define VSIM_STATUS_SHIFT 3 |
| 147 | |
| 148 | // (0x004) STATUS2 |
| 149 | // (RO) |
| 150 | #define VMC_STATUS_ADDR 0x04 |
| 151 | #define VMC_STATUS_MASK 0x20 |
| 152 | #define VMC_STATUS_SHIFT 5 |
| 153 | |
| 154 | // (0x005) PGSTATUS0 |
| 155 | // (RO) |
| 156 | #define VMD_PG_STATUS_ADDR 0x05 |
| 157 | #define VMD_PG_STATUS_MASK 0x80 |
| 158 | #define VMD_PG_STATUS_SHIFT 7 |
| 159 | |
| 160 | // (RO) |
| 161 | #define VTCXO_PG_STATUS_ADDR 0x05 |
| 162 | #define VTCXO_PG_STATUS_MASK 0x01 |
| 163 | #define VTCXO_PG_STATUS_SHIFT 0 |
| 164 | |
| 165 | // (0x006) PGSTATUS1 |
| 166 | // (RO) |
| 167 | #define VIO18_PG_STATUS_ADDR 0x06 |
| 168 | #define VIO18_PG_STATUS_MASK 0x20 |
| 169 | #define VIO18_PG_STATUS_SHIFT 5 |
| 170 | |
| 171 | // (RO) |
| 172 | #define VA25_PG_STATUS_ADDR 0x06 |
| 173 | #define VA25_PG_STATUS_MASK 0x08 |
| 174 | #define VA25_PG_STATUS_SHIFT 3 |
| 175 | |
| 176 | // (0x007) OCSTATUS0 |
| 177 | // (RO) |
| 178 | #define QI_VM_OC_STATUS_ADDR 0x07 |
| 179 | #define QI_VM_OC_STATUS_MASK 0x40 |
| 180 | #define QI_VM_OC_STATUS_SHIFT 6 |
| 181 | |
| 182 | // (RO) |
| 183 | #define QI_VMC_OC_STATUS_ADDR 0x07 |
| 184 | #define QI_VMC_OC_STATUS_MASK 0x20 |
| 185 | #define QI_VMC_OC_STATUS_SHIFT 5 |
| 186 | |
| 187 | // (RO) |
| 188 | #define QI_VSIM_OC_STATUS_ADDR 0x07 |
| 189 | #define QI_VSIM_OC_STATUS_MASK 0x08 |
| 190 | #define QI_VSIM_OC_STATUS_SHIFT 3 |
| 191 | |
| 192 | // (0x008) OCSTATUS1 |
| 193 | // (RO) |
| 194 | #define QI_VMD_OC_STATUS_ADDR 0x08 |
| 195 | #define QI_VMD_OC_STATUS_MASK 0x80 |
| 196 | #define QI_VMD_OC_STATUS_SHIFT 7 |
| 197 | |
| 198 | // (RO) |
| 199 | #define QI_VIO18_OC_STATUS_ADDR 0x08 |
| 200 | #define QI_VIO18_OC_STATUS_MASK 0x20 |
| 201 | #define QI_VIO18_OC_STATUS_SHIFT 5 |
| 202 | |
| 203 | // (RO) |
| 204 | #define QI_VRF18_OC_STATUS_ADDR 0x08 |
| 205 | #define QI_VRF18_OC_STATUS_MASK 0x10 |
| 206 | #define QI_VRF18_OC_STATUS_SHIFT 4 |
| 207 | |
| 208 | // (RO) |
| 209 | #define QI_VTCXO_OC_STATUS_ADDR 0x08 |
| 210 | #define QI_VTCXO_OC_STATUS_MASK 0x02 |
| 211 | #define QI_VTCXO_OC_STATUS_SHIFT 1 |
| 212 | |
| 213 | // (RO) |
| 214 | #define QI_VA25_OC_STATUS_ADDR 0x08 |
| 215 | #define QI_VA25_OC_STATUS_MASK 0x01 |
| 216 | #define QI_VA25_OC_STATUS_SHIFT 0 |
| 217 | |
| 218 | // (0x009) BGR0 |
| 219 | // (RW) |
| 220 | #define RG_BGR_RSEL_ADDR 0x09 |
| 221 | #define RG_BGR_RSEL_MASK 0x70 |
| 222 | #define RG_BGR_RSEL_SHIFT 4 |
| 223 | |
| 224 | // (RW) |
| 225 | #define rg_sw_bgr_trim_ADDR 0x09 |
| 226 | #define rg_sw_bgr_trim_MASK 0x04 |
| 227 | #define rg_sw_bgr_trim_SHIFT 2 |
| 228 | |
| 229 | // (RW) |
| 230 | #define RG_BGR_UNCHOP_PH_ADDR 0x09 |
| 231 | #define RG_BGR_UNCHOP_PH_MASK 0x02 |
| 232 | #define RG_BGR_UNCHOP_PH_SHIFT 1 |
| 233 | |
| 234 | // (RW) |
| 235 | #define RG_BGR_UNCHOP_ADDR 0x09 |
| 236 | #define RG_BGR_UNCHOP_MASK 0x01 |
| 237 | #define RG_BGR_UNCHOP_SHIFT 0 |
| 238 | |
| 239 | // (0x00A) BGR1 |
| 240 | // (RW) |
| 241 | #define RG_BGR_TEST_EN_ADDR 0x0A |
| 242 | #define RG_BGR_TEST_EN_MASK 0x80 |
| 243 | #define RG_BGR_TEST_EN_SHIFT 7 |
| 244 | |
| 245 | // (RW) |
| 246 | #define RG_BGR_TEST_RSTB_ADDR 0x0A |
| 247 | #define RG_BGR_TEST_RSTB_MASK 0x40 |
| 248 | #define RG_BGR_TEST_RSTB_SHIFT 6 |
| 249 | |
| 250 | // (RW) |
| 251 | #define RG_BGR_TRIM_EN_ADDR 0x0A |
| 252 | #define RG_BGR_TRIM_EN_MASK 0x20 |
| 253 | #define RG_BGR_TRIM_EN_SHIFT 5 |
| 254 | |
| 255 | // (RW) |
| 256 | #define RG_BGR_TRIM_ADDR 0x0A |
| 257 | #define RG_BGR_TRIM_MASK 0x1F |
| 258 | #define RG_BGR_TRIM_SHIFT 0 |
| 259 | |
| 260 | // (0x00B) I2C_RST0 |
| 261 | // (RW) |
| 262 | #define I2C_RST0_ADDR 0x0B |
| 263 | #define I2C_RST0_MASK 0xFF |
| 264 | #define I2C_RST0_SHIFT 0 |
| 265 | |
| 266 | // (0x00C) MODES |
| 267 | // (RW) |
| 268 | #define SDA_DRV_SEL_ADDR 0x0C |
| 269 | #define SDA_DRV_SEL_MASK 0x04 |
| 270 | #define SDA_DRV_SEL_SHIFT 2 |
| 271 | |
| 272 | // (RW) |
| 273 | #define RG_BGR_TRIM_MODE_ADDR 0x0C |
| 274 | #define RG_BGR_TRIM_MODE_MASK 0x02 |
| 275 | #define RG_BGR_TRIM_MODE_SHIFT 1 |
| 276 | |
| 277 | // (RW) |
| 278 | #define RG_BUCK_TRIM_MODE_ADDR 0x0C |
| 279 | #define RG_BUCK_TRIM_MODE_MASK 0x01 |
| 280 | #define RG_BUCK_TRIM_MODE_SHIFT 0 |
| 281 | |
| 282 | // (0x00D) SCAN_MODE |
| 283 | // (RW) |
| 284 | #define RG_SCAN_KEY_ADDR 0x0D |
| 285 | #define RG_SCAN_KEY_MASK 0xFF |
| 286 | #define RG_SCAN_KEY_SHIFT 0 |
| 287 | |
| 288 | // (0x00E) I2C_TIMEOUT |
| 289 | // (RW) |
| 290 | #define I2C_TIMEOUT_ADDR 0x0E |
| 291 | #define I2C_TIMEOUT_MASK 0xF0 |
| 292 | #define I2C_TIMEOUT_SHIFT 4 |
| 293 | |
| 294 | // (0x00F) PAD_GPO |
| 295 | // (RW) |
| 296 | #define PAD_SRCLKEN_GPO_ADDR 0x0F |
| 297 | #define PAD_SRCLKEN_GPO_MASK 0xF0 |
| 298 | #define PAD_SRCLKEN_GPO_SHIFT 4 |
| 299 | |
| 300 | // (RW) |
| 301 | #define PAD_SYSRSTB_GPO_ADDR 0x0F |
| 302 | #define PAD_SYSRSTB_GPO_MASK 0x0E |
| 303 | #define PAD_SYSRSTB_GPO_SHIFT 1 |
| 304 | |
| 305 | //Register STRUP |
| 306 | |
| 307 | // (0x020) STRUP_CTRL1 |
| 308 | // (RW) |
| 309 | #define RG_THRDET_SEL_ADDR 0x20 |
| 310 | #define RG_THRDET_SEL_MASK 0x40 |
| 311 | #define RG_THRDET_SEL_SHIFT 6 |
| 312 | |
| 313 | // (RW) |
| 314 | #define RG_THR_HWPDN_EN_ADDR 0x20 |
| 315 | #define RG_THR_HWPDN_EN_MASK 0x20 |
| 316 | #define RG_THR_HWPDN_EN_SHIFT 5 |
| 317 | |
| 318 | // (RW) |
| 319 | #define RG_STRUP_THR_SEL_ADDR 0x20 |
| 320 | #define RG_STRUP_THR_SEL_MASK 0x18 |
| 321 | #define RG_STRUP_THR_SEL_SHIFT 3 |
| 322 | |
| 323 | // (RW) |
| 324 | #define RG_THR_TMODE_ADDR 0x20 |
| 325 | #define RG_THR_TMODE_MASK 0x02 |
| 326 | #define RG_THR_TMODE_SHIFT 1 |
| 327 | |
| 328 | // (RW) |
| 329 | #define RG_PMU_PGDET_DIS_ADDR 0x20 |
| 330 | #define RG_PMU_PGDET_DIS_MASK 0x01 |
| 331 | #define RG_PMU_PGDET_DIS_SHIFT 0 |
| 332 | |
| 333 | // (0x021) STRUP_CTRL2 |
| 334 | // (RW) |
| 335 | #define RG_VREF_BG_ADDR 0x21 |
| 336 | #define RG_VREF_BG_MASK 0x70 |
| 337 | #define RG_VREF_BG_SHIFT 4 |
| 338 | |
| 339 | // (RW) |
| 340 | #define RG_STRUP_IREF_TRIM_ADDR 0x21 |
| 341 | #define RG_STRUP_IREF_TRIM_MASK 0x0F |
| 342 | #define RG_STRUP_IREF_TRIM_SHIFT 0 |
| 343 | |
| 344 | // (0x022) STRUP_CTRL3 |
| 345 | // (RW) |
| 346 | #define RG_RST_DRVSEL_ADDR 0x22 |
| 347 | #define RG_RST_DRVSEL_MASK 0x40 |
| 348 | #define RG_RST_DRVSEL_SHIFT 6 |
| 349 | |
| 350 | // (RW) |
| 351 | #define RG_UVLO_VTHL_ADDR 0x22 |
| 352 | #define RG_UVLO_VTHL_MASK 0x03 |
| 353 | #define RG_UVLO_VTHL_SHIFT 0 |
| 354 | |
| 355 | // (0x023) STRUP_RSV1 |
| 356 | // (RW) |
| 357 | #define RG_PMU_RSV_ADDR 0x23 |
| 358 | #define RG_PMU_RSV_MASK 0xF0 |
| 359 | #define RG_PMU_RSV_SHIFT 4 |
| 360 | |
| 361 | // (0x024) STRUP_TST_CTL |
| 362 | // (RW) |
| 363 | #define RG_BIAS_GEN_EN_FORCE_ADDR 0x24 |
| 364 | #define RG_BIAS_GEN_EN_FORCE_MASK 0x20 |
| 365 | #define RG_BIAS_GEN_EN_FORCE_SHIFT 5 |
| 366 | |
| 367 | // (RW) |
| 368 | #define RG_STRUP_PWRON_FORCE_ADDR 0x24 |
| 369 | #define RG_STRUP_PWRON_FORCE_MASK 0x10 |
| 370 | #define RG_STRUP_PWRON_FORCE_SHIFT 4 |
| 371 | |
| 372 | // (RW) |
| 373 | #define RG_STRUP_FT_CTRL_ADDR 0x24 |
| 374 | #define RG_STRUP_FT_CTRL_MASK 0x03 |
| 375 | #define RG_STRUP_FT_CTRL_SHIFT 0 |
| 376 | |
| 377 | // (0x025) STRUP_THR_CTL |
| 378 | // (RO) |
| 379 | #define PMU_THR_STATUS_ADDR 0x25 |
| 380 | #define PMU_THR_STATUS_MASK 0x70 |
| 381 | #define PMU_THR_STATUS_SHIFT 4 |
| 382 | |
| 383 | // (RW) |
| 384 | #define RG_THERMAL_TEST_ADDR 0x25 |
| 385 | #define RG_THERMAL_TEST_MASK 0x0C |
| 386 | #define RG_THERMAL_TEST_SHIFT 2 |
| 387 | |
| 388 | // (RW) |
| 389 | #define RG_ESDDEG_EN_ADDR 0x25 |
| 390 | #define RG_ESDDEG_EN_MASK 0x01 |
| 391 | #define RG_ESDDEG_EN_SHIFT 0 |
| 392 | |
| 393 | //RegisterVCORE |
| 394 | |
| 395 | // (0x050) VMD_CON0 |
| 396 | // (RW) |
| 397 | #define RG_VMD_CSL_ADDR 0x50 |
| 398 | #define RG_VMD_CSL_MASK 0x30 |
| 399 | #define RG_VMD_CSL_SHIFT 4 |
| 400 | |
| 401 | // (RW) |
| 402 | #define RG_VMD_CC_ADDR 0x50 |
| 403 | #define RG_VMD_CC_MASK 0x0C |
| 404 | #define RG_VMD_CC_SHIFT 2 |
| 405 | |
| 406 | // (RW) |
| 407 | #define RG_VMD_RZSEL_ADDR 0x50 |
| 408 | #define RG_VMD_RZSEL_MASK 0x03 |
| 409 | #define RG_VMD_RZSEL_SHIFT 0 |
| 410 | |
| 411 | // (0x051) VMD_CON1 |
| 412 | // (RW) |
| 413 | #define RG_VMD_SLP_ADDR 0x51 |
| 414 | #define RG_VMD_SLP_MASK 0xC0 |
| 415 | #define RG_VMD_SLP_SHIFT 6 |
| 416 | |
| 417 | // (RW) |
| 418 | #define RG_VMD_ZX_OS_ADDR 0x51 |
| 419 | #define RG_VMD_ZX_OS_MASK 0x30 |
| 420 | #define RG_VMD_ZX_OS_SHIFT 4 |
| 421 | |
| 422 | // (RW) |
| 423 | #define RG_VMD_SLEW_ADDR 0x51 |
| 424 | #define RG_VMD_SLEW_MASK 0x0C |
| 425 | #define RG_VMD_SLEW_SHIFT 2 |
| 426 | |
| 427 | // (RW) |
| 428 | #define RG_VMD_SLEW_NMOS_ADDR 0x51 |
| 429 | #define RG_VMD_SLEW_NMOS_MASK 0x03 |
| 430 | #define RG_VMD_SLEW_NMOS_SHIFT 0 |
| 431 | |
| 432 | // (0x052) VMD_CON2 |
| 433 | // (RW) |
| 434 | #define RG_VMD_MODESET_ADDR 0x52 |
| 435 | #define RG_VMD_MODESET_MASK 0x01 |
| 436 | #define RG_VMD_MODESET_SHIFT 0 |
| 437 | |
| 438 | // (0x053) VMD_CON3 |
| 439 | // (RO) |
| 440 | #define QI_VMD_EN_ADDR 0x53 |
| 441 | #define QI_VMD_EN_MASK 0x80 |
| 442 | #define QI_VMD_EN_SHIFT 7 |
| 443 | |
| 444 | // (RW) |
| 445 | #define RG_VMD_EN_ADDR 0x53 |
| 446 | #define RG_VMD_EN_MASK 0x01 |
| 447 | #define RG_VMD_EN_SHIFT 0 |
| 448 | |
| 449 | // (0x054) VMD_CON4 |
| 450 | // (RW) |
| 451 | #define RG_VMD_VFBADJ_ADDR 0x54 |
| 452 | #define RG_VMD_VFBADJ_MASK 0x0E |
| 453 | #define RG_VMD_VFBADJ_SHIFT 1 |
| 454 | |
| 455 | // (RW) |
| 456 | #define RG_VMD_NDIS_EN_ADDR 0x54 |
| 457 | #define RG_VMD_NDIS_EN_MASK 0x01 |
| 458 | #define RG_VMD_NDIS_EN_SHIFT 0 |
| 459 | |
| 460 | // (0x055) VMD_CON5 |
| 461 | // (RW) |
| 462 | #define RG_VMD_VOSEL_ADDR 0x55 |
| 463 | #define RG_VMD_VOSEL_MASK 0x1F |
| 464 | #define RG_VMD_VOSEL_SHIFT 0 |
| 465 | |
| 466 | // (0x056) VMD_CON6 |
| 467 | // (RW) |
| 468 | #define RG_VMD_VOSEL_CON1_ADDR 0x56 |
| 469 | #define RG_VMD_VOSEL_CON1_MASK 0x1F |
| 470 | #define RG_VMD_VOSEL_CON1_SHIFT 0 |
| 471 | |
| 472 | // (0x057) VMD_CON7 |
| 473 | // (RW) |
| 474 | #define RG_VMD_VOSEL_SFCHG_EN_ADDR 0x57 |
| 475 | #define RG_VMD_VOSEL_SFCHG_EN_MASK 0x04 |
| 476 | #define RG_VMD_VOSEL_SFCHG_EN_SHIFT 2 |
| 477 | |
| 478 | // (RW) |
| 479 | #define RG_VMD_CTRL_ADDR 0x57 |
| 480 | #define RG_VMD_CTRL_MASK 0x01 |
| 481 | #define RG_VMD_CTRL_SHIFT 0 |
| 482 | |
| 483 | // (0x058) VMD_CON8 |
| 484 | // (RO) |
| 485 | #define QI_VMD_VOSEL_ADDR 0x58 |
| 486 | #define QI_VMD_VOSEL_MASK 0x1F |
| 487 | #define QI_VMD_VOSEL_SHIFT 0 |
| 488 | |
| 489 | // (0x05A) VMD_CON10 |
| 490 | // (RW) |
| 491 | #define RG_TIMESTEP_ADDR 0x5A |
| 492 | #define RG_TIMESTEP_MASK 0x01 |
| 493 | #define RG_TIMESTEP_SHIFT 0 |
| 494 | |
| 495 | // (RW) |
| 496 | #define RG_VOLTSTEP_ADDR 0x5A |
| 497 | #define RG_VOLTSTEP_MASK 0x02 |
| 498 | #define RG_VOLTSTEP_SHIFT 1 |
| 499 | |
| 500 | // (0x05B) VMD_CON11 |
| 501 | // (RW) |
| 502 | #define RG_VMD_VH_ADDR 0x5B |
| 503 | #define RG_VMD_VH_MASK 0x70 |
| 504 | #define RG_VMD_VH_SHIFT 4 |
| 505 | |
| 506 | // (RW) |
| 507 | #define RG_VMD_VL_ADDR 0x5B |
| 508 | #define RG_VMD_VL_MASK 0x0E |
| 509 | #define RG_VMD_VL_SHIFT 1 |
| 510 | |
| 511 | // (RW) |
| 512 | #define RG_VMD_GM_ADDR 0x5B |
| 513 | #define RG_VMD_GM_MASK 0x01 |
| 514 | #define RG_VMD_GM_SHIFT 0 |
| 515 | |
| 516 | // (0x05C) VMD_CON12 |
| 517 | // (RW) |
| 518 | #define RG_VMD_CSR_ADDR 0x5C |
| 519 | #define RG_VMD_CSR_MASK 0x07 |
| 520 | #define RG_VMD_CSR_SHIFT 0 |
| 521 | |
| 522 | // (0x05D) VMD_CON13 |
| 523 | // (RW) |
| 524 | #define VMD_OC_WND_ADDR 0x5D |
| 525 | #define VMD_OC_WND_MASK 0x0C |
| 526 | #define VMD_OC_WND_SHIFT 2 |
| 527 | |
| 528 | // (RW) |
| 529 | #define VMD_OC_THD_ADDR 0x5D |
| 530 | #define VMD_OC_THD_MASK 0x03 |
| 531 | #define VMD_OC_THD_SHIFT 0 |
| 532 | |
| 533 | //RegisterVRF18 |
| 534 | |
| 535 | // (0x060) VRF18_CON0 |
| 536 | // (RW) |
| 537 | #define RG_VRF18_CSL_ADDR 0x60 |
| 538 | #define RG_VRF18_CSL_MASK 0x30 |
| 539 | #define RG_VRF18_CSL_SHIFT 4 |
| 540 | |
| 541 | // (RW) |
| 542 | #define RG_VRF18_CC_ADDR 0x60 |
| 543 | #define RG_VRF18_CC_MASK 0x0C |
| 544 | #define RG_VRF18_CC_SHIFT 2 |
| 545 | |
| 546 | // (RW) |
| 547 | #define RG_VRF18_RZSEL_ADDR 0x60 |
| 548 | #define RG_VRF18_RZSEL_MASK 0x03 |
| 549 | #define RG_VRF18_RZSEL_SHIFT 0 |
| 550 | |
| 551 | // (0x061) VRF18_CON1 |
| 552 | // (RW) |
| 553 | #define RG_VRF18_SLP_ADDR 0x61 |
| 554 | #define RG_VRF18_SLP_MASK 0xC0 |
| 555 | #define RG_VRF18_SLP_SHIFT 6 |
| 556 | |
| 557 | // (RW) |
| 558 | #define RG_VRF18_ZX_OS_ADDR 0x61 |
| 559 | #define RG_VRF18_ZX_OS_MASK 0x30 |
| 560 | #define RG_VRF18_ZX_OS_SHIFT 4 |
| 561 | |
| 562 | // (RW) |
| 563 | #define RG_VRF18_SLEW_ADDR 0x61 |
| 564 | #define RG_VRF18_SLEW_MASK 0x0C |
| 565 | #define RG_VRF18_SLEW_SHIFT 2 |
| 566 | |
| 567 | // (RW) |
| 568 | #define RG_VRF18_SLEW_NMOS_ADDR 0x61 |
| 569 | #define RG_VRF18_SLEW_NMOS_MASK 0x03 |
| 570 | #define RG_VRF18_SLEW_NMOS_SHIFT 0 |
| 571 | |
| 572 | // (0x062) VRF18_CON2 |
| 573 | // (RW) |
| 574 | #define RG_VRF18_AVP_EN_ADDR 0x62 |
| 575 | #define RG_VRF18_AVP_EN_MASK 0x02 |
| 576 | #define RG_VRF18_AVP_EN_SHIFT 1 |
| 577 | |
| 578 | // (RW) |
| 579 | #define RG_VRF18_MODESET_ADDR 0x62 |
| 580 | #define RG_VRF18_MODESET_MASK 0x01 |
| 581 | #define RG_VRF18_MODESET_SHIFT 0 |
| 582 | |
| 583 | // (0x063) VRF18_CON3 |
| 584 | // (RO) |
| 585 | #define QI_VRF18_EN_ADDR 0x63 |
| 586 | #define QI_VRF18_EN_MASK 0x80 |
| 587 | #define QI_VRF18_EN_SHIFT 7 |
| 588 | |
| 589 | // (RW) |
| 590 | #define RG_VRF18_ON_CTRL_ADDR 0x63 |
| 591 | #define RG_VRF18_ON_CTRL_MASK 0x02 |
| 592 | #define RG_VRF18_ON_CTRL_SHIFT 1 |
| 593 | |
| 594 | // (RW) |
| 595 | #define RG_VRF18_EN_ADDR 0x63 |
| 596 | #define RG_VRF18_EN_MASK 0x01 |
| 597 | #define RG_VRF18_EN_SHIFT 0 |
| 598 | |
| 599 | // (0x064) VRF18_CON4 |
| 600 | // (RW) |
| 601 | #define RG_VRF18_STBTD_ADDR 0x64 |
| 602 | #define RG_VRF18_STBTD_MASK 0xC0 |
| 603 | #define RG_VRF18_STBTD_SHIFT 6 |
| 604 | |
| 605 | // (RW) |
| 606 | #define RG_VRF18_BURST_ADDR 0x64 |
| 607 | #define RG_VRF18_BURST_MASK 0x30 |
| 608 | #define RG_VRF18_BURST_SHIFT 4 |
| 609 | |
| 610 | // (RW) |
| 611 | #define RG_VRF18_OCFB_EN_ADDR 0x64 |
| 612 | #define RG_VRF18_OCFB_EN_MASK 0x02 |
| 613 | #define RG_VRF18_OCFB_EN_SHIFT 1 |
| 614 | |
| 615 | // (RW) |
| 616 | #define RG_VRF18_NDIS_EN_ADDR 0x64 |
| 617 | #define RG_VRF18_NDIS_EN_MASK 0x01 |
| 618 | #define RG_VRF18_NDIS_EN_SHIFT 0 |
| 619 | |
| 620 | // (0x065) VRF18_CON5 |
| 621 | // (RW) |
| 622 | #define RG_VRF18_VOSEL_ADDR 0x65 |
| 623 | #define RG_VRF18_VOSEL_MASK 0x1F |
| 624 | #define RG_VRF18_VOSEL_SHIFT 0 |
| 625 | |
| 626 | // (0x066) VRF18_CON6 |
| 627 | // (RW) |
| 628 | #define RG_VRF18_RSV_ADDR 0x66 |
| 629 | #define RG_VRF18_RSV_MASK 0x0F |
| 630 | #define RG_VRF18_RSV_SHIFT 0 |
| 631 | |
| 632 | // (0x069) VRF18_CON9 |
| 633 | // (RW) |
| 634 | #define RG_VRF18_VH_ADDR 0x69 |
| 635 | #define RG_VRF18_VH_MASK 0x70 |
| 636 | #define RG_VRF18_VH_SHIFT 4 |
| 637 | |
| 638 | // (RW) |
| 639 | #define RG_VRF18_VL_ADDR 0x69 |
| 640 | #define RG_VRF18_VL_MASK 0x0E |
| 641 | #define RG_VRF18_VL_SHIFT 1 |
| 642 | |
| 643 | // (RW) |
| 644 | #define RG_VRF18_GMSEL_ADDR 0x69 |
| 645 | #define RG_VRF18_GMSEL_MASK 0x01 |
| 646 | #define RG_VRF18_GMSEL_SHIFT 0 |
| 647 | |
| 648 | // (0x06A) VRF18_CON10 |
| 649 | // (RW) |
| 650 | #define RG_VRF18_CSR_ADDR 0x6A |
| 651 | #define RG_VRF18_CSR_MASK 0x07 |
| 652 | #define RG_VRF18_CSR_SHIFT 0 |
| 653 | |
| 654 | // (0x06B) VRF18_CON11 |
| 655 | // (RW) |
| 656 | #define RG_VRF18_OC_WND_ADDR 0x6B |
| 657 | #define RG_VRF18_OC_WND_MASK 0x0C |
| 658 | #define RG_VRF18_OC_WND_SHIFT 2 |
| 659 | |
| 660 | // (RW) |
| 661 | #define RG_VRF18_OC_THD_ADDR 0x6B |
| 662 | #define RG_VRF18_OC_THD_MASK 0x03 |
| 663 | #define RG_VRF18_OC_THD_SHIFT 0 |
| 664 | |
| 665 | //RegisterDigLDO |
| 666 | |
| 667 | // (0x080) DIGLDO_CON0 |
| 668 | // (RW) |
| 669 | #define RG_VIO18_CAL_ADDR 0x80 |
| 670 | #define RG_VIO18_CAL_MASK 0x0F |
| 671 | #define RG_VIO18_CAL_SHIFT 0 |
| 672 | |
| 673 | // (0x082) DIGLDO_CON1 |
| 674 | // (RW) |
| 675 | #define RG_VIO18_STBTD_ADDR 0x82 |
| 676 | #define RG_VIO18_STBTD_MASK 0x30 |
| 677 | #define RG_VIO18_STBTD_SHIFT 4 |
| 678 | |
| 679 | // (RW) |
| 680 | #define RG_VIO18_OCFB_EN_ADDR 0x82 |
| 681 | #define RG_VIO18_OCFB_EN_MASK 0x04 |
| 682 | #define RG_VIO18_OCFB_EN_SHIFT 2 |
| 683 | |
| 684 | // (RW) |
| 685 | #define RG_VIO18_NDIS_EN_ADDR 0x82 |
| 686 | #define RG_VIO18_NDIS_EN_MASK 0x02 |
| 687 | #define RG_VIO18_NDIS_EN_SHIFT 1 |
| 688 | |
| 689 | // (RW) |
| 690 | #define RG_VIO18_EN_ADDR 0x82 |
| 691 | #define RG_VIO18_EN_MASK 0x01 |
| 692 | #define RG_VIO18_EN_SHIFT 0 |
| 693 | |
| 694 | // (0x083) DIGLDO_CON2 |
| 695 | // (RW) |
| 696 | #define RG_VSIM_CAL_ADDR 0x83 |
| 697 | #define RG_VSIM_CAL_MASK 0x0F |
| 698 | #define RG_VSIM_CAL_SHIFT 0 |
| 699 | |
| 700 | // (0x084) DIGLDO_CON3 |
| 701 | // (RW) |
| 702 | #define RG_VSIM_VOSEL_ADDR 0x84 |
| 703 | #define RG_VSIM_VOSEL_MASK 0x10 |
| 704 | #define RG_VSIM_VOSEL_SHIFT 4 |
| 705 | |
| 706 | // (RW) |
| 707 | #define RG_VSIM_EN_ADDR 0x84 |
| 708 | #define RG_VSIM_EN_MASK 0x01 |
| 709 | #define RG_VSIM_EN_SHIFT 0 |
| 710 | |
| 711 | // (0x085) DIGLDO_CON4 |
| 712 | // (RW) |
| 713 | #define RG_VSIM_STBTD_ADDR 0x85 |
| 714 | #define RG_VSIM_STBTD_MASK 0x30 |
| 715 | #define RG_VSIM_STBTD_SHIFT 4 |
| 716 | |
| 717 | // (RW) |
| 718 | #define RG_VSIM_OCFB_EN_ADDR 0x85 |
| 719 | #define RG_VSIM_OCFB_EN_MASK 0x02 |
| 720 | #define RG_VSIM_OCFB_EN_SHIFT 1 |
| 721 | |
| 722 | // (RW) |
| 723 | #define RG_VSIM_NDIS_EN_ADDR 0x85 |
| 724 | #define RG_VSIM_NDIS_EN_MASK 0x01 |
| 725 | #define RG_VSIM_NDIS_EN_SHIFT 0 |
| 726 | |
| 727 | // (0x086) DIGLDO_CON5 |
| 728 | // (RW) |
| 729 | #define RG_VMC_CAL_ADDR 0x86 |
| 730 | #define RG_VMC_CAL_MASK 0x0F |
| 731 | #define RG_VMC_CAL_SHIFT 0 |
| 732 | |
| 733 | // (0x087) DIGLDO_CON6 |
| 734 | // (RW) |
| 735 | #define RG_VMC_VOSEL_ADDR 0x87 |
| 736 | #define RG_VMC_VOSEL_MASK 0x70 |
| 737 | #define RG_VMC_VOSEL_SHIFT 4 |
| 738 | |
| 739 | // (0x088) DIGLDO_CON7 |
| 740 | // (RW) |
| 741 | #define RG_VMC_STBTD_ADDR 0x88 |
| 742 | #define RG_VMC_STBTD_MASK 0x30 |
| 743 | #define RG_VMC_STBTD_SHIFT 4 |
| 744 | |
| 745 | // (RW) |
| 746 | #define RG_VMC_STB_SEL_ADDR 0x88 |
| 747 | #define RG_VMC_STB_SEL_MASK 0x08 |
| 748 | #define RG_VMC_STB_SEL_SHIFT 3 |
| 749 | |
| 750 | // (RW) |
| 751 | #define RG_VMC_OCFB_EN_ADDR 0x88 |
| 752 | #define RG_VMC_OCFB_EN_MASK 0x04 |
| 753 | #define RG_VMC_OCFB_EN_SHIFT 2 |
| 754 | |
| 755 | // (RW) |
| 756 | #define RG_VMC_NDIS_EN_ADDR 0x88 |
| 757 | #define RG_VMC_NDIS_EN_MASK 0x02 |
| 758 | #define RG_VMC_NDIS_EN_SHIFT 1 |
| 759 | |
| 760 | // (RW) |
| 761 | #define RG_VMC_EN_ADDR 0x88 |
| 762 | #define RG_VMC_EN_MASK 0x01 |
| 763 | #define RG_VMC_EN_SHIFT 0 |
| 764 | |
| 765 | // (0x089) DIGLDO_CON8 |
| 766 | // (RW) |
| 767 | #define RG_VM_CAL_ADDR 0x89 |
| 768 | #define RG_VM_CAL_MASK 0x0F |
| 769 | #define RG_VM_CAL_SHIFT 0 |
| 770 | |
| 771 | // (0x08A) DIGLDO_CON9 |
| 772 | // (RW) |
| 773 | #define RG_VM_VOSEL_ADDR 0x8A |
| 774 | #define RG_VM_VOSEL_MASK 0x30 |
| 775 | #define RG_VM_VOSEL_SHIFT 4 |
| 776 | |
| 777 | // (RW) |
| 778 | #define RG_VM_EN_ADDR 0x8A |
| 779 | #define RG_VM_EN_MASK 0x01 |
| 780 | #define RG_VM_EN_SHIFT 0 |
| 781 | |
| 782 | // (0x08B) DIGLDO_CON10 |
| 783 | // (RW) |
| 784 | #define RG_VM_STBTD_ADDR 0x8B |
| 785 | #define RG_VM_STBTD_MASK 0x30 |
| 786 | #define RG_VM_STBTD_SHIFT 4 |
| 787 | |
| 788 | // (RW) |
| 789 | #define RG_VM_OCFB_EN_ADDR 0x8B |
| 790 | #define RG_VM_OCFB_EN_MASK 0x02 |
| 791 | #define RG_VM_OCFB_EN_SHIFT 1 |
| 792 | |
| 793 | // (RW) |
| 794 | #define RG_VM_NDIS_EN_ADDR 0x8B |
| 795 | #define RG_VM_NDIS_EN_MASK 0x01 |
| 796 | #define RG_VM_NDIS_EN_SHIFT 0 |
| 797 | |
| 798 | // (0x08C) DIGLDO_CON11 |
| 799 | // (RO) |
| 800 | #define QI_VMC_MODE_ADDR 0x8C |
| 801 | #define QI_VMC_MODE_MASK 0x80 |
| 802 | #define QI_VMC_MODE_SHIFT 7 |
| 803 | |
| 804 | // (RW) |
| 805 | #define VMC_LP_MODE_SET_ADDR 0x8C |
| 806 | #define VMC_LP_MODE_SET_MASK 0x02 |
| 807 | #define VMC_LP_MODE_SET_SHIFT 1 |
| 808 | |
| 809 | // (RW) |
| 810 | #define VMC_LP_SEL_ADDR 0x8C |
| 811 | #define VMC_LP_SEL_MASK 0x01 |
| 812 | #define VMC_LP_SEL_SHIFT 0 |
| 813 | |
| 814 | // (0x08D) DIGLDO_CON12 |
| 815 | // (RO) |
| 816 | #define QI_VM_MODE_ADDR 0x8D |
| 817 | #define QI_VM_MODE_MASK 0x80 |
| 818 | #define QI_VM_MODE_SHIFT 7 |
| 819 | |
| 820 | // (RW) |
| 821 | #define VM_LP_MODE_SET_ADDR 0x8D |
| 822 | #define VM_LP_MODE_SET_MASK 0x02 |
| 823 | #define VM_LP_MODE_SET_SHIFT 1 |
| 824 | |
| 825 | // (RW) |
| 826 | #define VM_LP_SEL_ADDR 0x8D |
| 827 | #define VM_LP_SEL_MASK 0x01 |
| 828 | #define VM_LP_SEL_SHIFT 0 |
| 829 | |
| 830 | // (0x08F) DIGLDO_CON14 |
| 831 | // (RW) |
| 832 | #define RG_RSV_DLDOS_ADDR 0x8F |
| 833 | #define RG_RSV_DLDOS_MASK 0xFF |
| 834 | #define RG_RSV_DLDOS_SHIFT 0 |
| 835 | |
| 836 | //RegisterAnaLDO |
| 837 | |
| 838 | // (0x0A0) ANALDO_CON0 |
| 839 | // (RW) |
| 840 | #define RG_VTCXO_CAL_ADDR 0xA0 |
| 841 | #define RG_VTCXO_CAL_MASK 0x0F |
| 842 | #define RG_VTCXO_CAL_SHIFT 0 |
| 843 | |
| 844 | // (0x0A1) ANALDO_CON1 |
| 845 | // (RO) |
| 846 | #define QI_VTCXO_EN_ADDR 0xA1 |
| 847 | #define QI_VTCXO_EN_MASK 0x80 |
| 848 | #define QI_VTCXO_EN_SHIFT 7 |
| 849 | |
| 850 | // (RW) |
| 851 | #define VTCXO_ON_CTRL_ADDR 0xA1 |
| 852 | #define VTCXO_ON_CTRL_MASK 0x02 |
| 853 | #define VTCXO_ON_CTRL_SHIFT 1 |
| 854 | |
| 855 | // (RW) |
| 856 | #define RG_VTCXO_EN_ADDR 0xA1 |
| 857 | #define RG_VTCXO_EN_MASK 0x01 |
| 858 | #define RG_VTCXO_EN_SHIFT 0 |
| 859 | |
| 860 | // (0x0A2) ANALDO_CON2 |
| 861 | // (RW) |
| 862 | #define RG_VTCXO_STBTD_ADDR 0xA2 |
| 863 | #define RG_VTCXO_STBTD_MASK 0x30 |
| 864 | #define RG_VTCXO_STBTD_SHIFT 4 |
| 865 | |
| 866 | // (RW) |
| 867 | #define RG_VTCXO_OCFB_EN_ADDR 0xA2 |
| 868 | #define RG_VTCXO_OCFB_EN_MASK 0x02 |
| 869 | #define RG_VTCXO_OCFB_EN_SHIFT 1 |
| 870 | |
| 871 | // (RW) |
| 872 | #define RG_VTCXO_NDIS_EN_ADDR 0xA2 |
| 873 | #define RG_VTCXO_NDIS_EN_MASK 0x01 |
| 874 | #define RG_VTCXO_NDIS_EN_SHIFT 0 |
| 875 | |
| 876 | // (0x0A3) ANALDO_CON3 |
| 877 | // (RW) |
| 878 | #define RG_VA25_CAL_ADDR 0xA3 |
| 879 | #define RG_VA25_CAL_MASK 0x0F |
| 880 | #define RG_VA25_CAL_SHIFT 0 |
| 881 | |
| 882 | // (0x0A4) ANALDO_CON4 |
| 883 | // (RO) |
| 884 | #define QI_VA25_EN_ADDR 0xA4 |
| 885 | #define QI_VA25_EN_MASK 0x80 |
| 886 | #define QI_VA25_EN_SHIFT 7 |
| 887 | |
| 888 | // (RW) |
| 889 | #define RG_VA25_EN_ADDR 0xA4 |
| 890 | #define RG_VA25_EN_MASK 0x01 |
| 891 | #define RG_VA25_EN_SHIFT 0 |
| 892 | |
| 893 | // (0x0A5) ANALDO_CON5 |
| 894 | // (RW) |
| 895 | #define RG_VA25_STBTD_ADDR 0xA5 |
| 896 | #define RG_VA25_STBTD_MASK 0x30 |
| 897 | #define RG_VA25_STBTD_SHIFT 4 |
| 898 | |
| 899 | // (RW) |
| 900 | #define RG_VA25_OCFB_EN_ADDR 0xA5 |
| 901 | #define RG_VA25_OCFB_EN_MASK 0x02 |
| 902 | #define RG_VA25_OCFB_EN_SHIFT 1 |
| 903 | |
| 904 | // (RW) |
| 905 | #define RG_VA25_NDIS_EN_ADDR 0xA5 |
| 906 | #define RG_VA25_NDIS_EN_MASK 0x01 |
| 907 | #define RG_VA25_NDIS_EN_SHIFT 0 |
| 908 | |
| 909 | // (0x0A6) ANALDO_CON6 |
| 910 | // (RO) |
| 911 | #define QI_VA25_MODE_ADDR 0xA6 |
| 912 | #define QI_VA25_MODE_MASK 0x80 |
| 913 | #define QI_VA25_MODE_SHIFT 7 |
| 914 | |
| 915 | // (RW) |
| 916 | #define VA25_LP_SET_ADDR 0xA6 |
| 917 | #define VA25_LP_SET_MASK 0x02 |
| 918 | #define VA25_LP_SET_SHIFT 1 |
| 919 | |
| 920 | // (RW) |
| 921 | #define VA25_LP_SEL_ADDR 0xA6 |
| 922 | #define VA25_LP_SEL_MASK 0x01 |
| 923 | #define VA25_LP_SEL_SHIFT 0 |
| 924 | |
| 925 | // (0x0A7) ANALDO_CON7 |
| 926 | // (RO) |
| 927 | #define QI_VTCXO_MODE_ADDR 0xA7 |
| 928 | #define QI_VTCXO_MODE_MASK 0x80 |
| 929 | #define QI_VTCXO_MODE_SHIFT 7 |
| 930 | |
| 931 | // (RW) |
| 932 | #define VTCXO_LP_SET_ADDR 0xA7 |
| 933 | #define VTCXO_LP_SET_MASK 0x02 |
| 934 | #define VTCXO_LP_SET_SHIFT 1 |
| 935 | |
| 936 | // (RW) |
| 937 | #define VTCXO_LP_SEL_ADDR 0xA7 |
| 938 | #define VTCXO_LP_SEL_MASK 0x01 |
| 939 | #define VTCXO_LP_SEL_SHIFT 0 |
| 940 | |
| 941 | // (0x0A8) ANALDO_CON8 |
| 942 | // (RW) |
| 943 | #define RG_VA25_STB_ADDR 0xA8 |
| 944 | #define RG_VA25_STB_MASK 0x02 |
| 945 | #define RG_VA25_STB_SHIFT 1 |
| 946 | |
| 947 | // (RW) |
| 948 | #define RG_VTCXO_STB_ADDR 0xA8 |
| 949 | #define RG_VTCXO_STB_MASK 0x01 |
| 950 | #define RG_VTCXO_STB_SHIFT 0 |
| 951 | |
| 952 | //RegisterBuckK |
| 953 | |
| 954 | // (0x0B0) BUCK_K_CON0 |
| 955 | // (RW) |
| 956 | #define RG_SMPS_TESTMODE_ADDR 0xB0 |
| 957 | #define RG_SMPS_TESTMODE_MASK 0x3F |
| 958 | #define RG_SMPS_TESTMODE_SHIFT 0 |
| 959 | |
| 960 | // (0x0B2) BUCK_K_CON2 |
| 961 | // (RW) |
| 962 | #define RG_SMPS_RSV_ADDR 0xB2 |
| 963 | #define RG_SMPS_RSV_MASK 0xFF |
| 964 | #define RG_SMPS_RSV_SHIFT 0 |
| 965 | |
| 966 | // (0x0B3) BUCK_K_CON3 |
| 967 | // (RW) |
| 968 | #define rg_auto_k_ADDR 0xB3 |
| 969 | #define rg_auto_k_MASK 0x40 |
| 970 | #define rg_auto_k_SHIFT 6 |
| 971 | |
| 972 | // (RW) |
| 973 | #define rg_k_start_manual_ADDR 0xB3 |
| 974 | #define rg_k_start_manual_MASK 0x10 |
| 975 | #define rg_k_start_manual_SHIFT 4 |
| 976 | |
| 977 | // (RW) |
| 978 | #define rg_k_map_sel_ADDR 0xB3 |
| 979 | #define rg_k_map_sel_MASK 0x02 |
| 980 | #define rg_k_map_sel_SHIFT 1 |
| 981 | |
| 982 | // (RW) |
| 983 | #define rg_k_rst_done_ADDR 0xB3 |
| 984 | #define rg_k_rst_done_MASK 0x01 |
| 985 | #define rg_k_rst_done_SHIFT 0 |
| 986 | |
| 987 | // (0x0B4) BUCK_K_CON4 |
| 988 | // (RW) |
| 989 | #define rg_k_control_smps_ADDR 0xB4 |
| 990 | #define rg_k_control_smps_MASK 0x3F |
| 991 | #define rg_k_control_smps_SHIFT 0 |
| 992 | |
| 993 | // (0x0B5) BUCK_K_CON5 |
| 994 | // (RO) |
| 995 | #define k_control_ADDR 0xB5 |
| 996 | #define k_control_MASK 0xFC |
| 997 | #define k_control_SHIFT 2 |
| 998 | |
| 999 | // (RO) |
| 1000 | #define k_done_ADDR 0xB5 |
| 1001 | #define k_done_MASK 0x02 |
| 1002 | #define k_done_SHIFT 1 |
| 1003 | |
| 1004 | // (RO) |
| 1005 | #define k_result_ADDR 0xB5 |
| 1006 | #define k_result_MASK 0x01 |
| 1007 | #define k_result_SHIFT 0 |
| 1008 | |
| 1009 | // (0x0B6) BUCK_K_CON6 |
| 1010 | // (RW) |
| 1011 | #define efuse_enb_ADDR 0xB6 |
| 1012 | #define efuse_enb_MASK 0x80 |
| 1013 | #define efuse_enb_SHIFT 7 |
| 1014 | |
| 1015 | // (RW) |
| 1016 | #define efuse_read_ADDR 0xB6 |
| 1017 | #define efuse_read_MASK 0x40 |
| 1018 | #define efuse_read_SHIFT 6 |
| 1019 | |
| 1020 | // (RW) |
| 1021 | #define efuse_program_ADDR 0xB6 |
| 1022 | #define efuse_program_MASK 0x20 |
| 1023 | #define efuse_program_SHIFT 5 |
| 1024 | |
| 1025 | // (RW) |
| 1026 | #define efuse_address_ADDR 0xB6 |
| 1027 | #define efuse_address_MASK 0x1F |
| 1028 | #define efuse_address_SHIFT 0 |
| 1029 | |
| 1030 | // (0x0B7) BUCK_K_CON7 |
| 1031 | // (RW) |
| 1032 | #define efuse_address_msb_ADDR 0xB7 |
| 1033 | #define efuse_address_msb_MASK 0x80 |
| 1034 | #define efuse_address_msb_SHIFT 7 |
| 1035 | |
| 1036 | // (RW) |
| 1037 | #define rg_sw_osc_trim_ADDR 0xB7 |
| 1038 | #define rg_sw_osc_trim_MASK 0x01 |
| 1039 | #define rg_sw_osc_trim_SHIFT 0 |
| 1040 | |
| 1041 | // (0x0B8) BUCK_K_CON8 |
| 1042 | // (RO) |
| 1043 | #define efuse_dout0_ADDR 0xB8 |
| 1044 | #define efuse_dout0_MASK 0xFF |
| 1045 | #define efuse_dout0_SHIFT 0 |
| 1046 | |
| 1047 | // (0x0B9) BUCK_K_CON9 |
| 1048 | // (RO) |
| 1049 | #define efuse_dout1_ADDR 0xB9 |
| 1050 | #define efuse_dout1_MASK 0xFF |
| 1051 | #define efuse_dout1_SHIFT 0 |
| 1052 | |
| 1053 | // (0x0BA) BUCK_K_CON10 |
| 1054 | // (RO) |
| 1055 | #define efuse_dout2_ADDR 0xBA |
| 1056 | #define efuse_dout2_MASK 0xFF |
| 1057 | #define efuse_dout2_SHIFT 0 |
| 1058 | |
| 1059 | // (0x0BB) BUCK_K_CON11 |
| 1060 | // (RO) |
| 1061 | #define efuse_dout3_ADDR 0xBB |
| 1062 | #define efuse_dout3_MASK 0xFF |
| 1063 | #define efuse_dout3_SHIFT 0 |
| 1064 | |
| 1065 | // (0x0BC) BUCK_K_CON12 |
| 1066 | // (RO) |
| 1067 | #define efuse_dout4_ADDR 0xBC |
| 1068 | #define efuse_dout4_MASK 0xFF |
| 1069 | #define efuse_dout4_SHIFT 0 |
| 1070 | |
| 1071 | // (0x0BD) BUCK_K_CON13 |
| 1072 | // (RO) |
| 1073 | #define efuse_dout5_ADDR 0xBD |
| 1074 | #define efuse_dout5_MASK 0xFF |
| 1075 | #define efuse_dout5_SHIFT 0 |
| 1076 | |
| 1077 | // (0x0BE) BUCK_K_CON14 |
| 1078 | // (RO) |
| 1079 | #define efuse_dout6_ADDR 0xBE |
| 1080 | #define efuse_dout6_MASK 0xFF |
| 1081 | #define efuse_dout6_SHIFT 0 |
| 1082 | |
| 1083 | // (0x0BF) BUCK_K_CON15 |
| 1084 | // (RO) |
| 1085 | #define efuse_dout7_ADDR 0xBF |
| 1086 | #define efuse_dout7_MASK 0xFF |
| 1087 | #define efuse_dout7_SHIFT 0 |
| 1088 | |
| 1089 | //RegisterPAD |
| 1090 | |
| 1091 | // (0x0D0) PAD_CTRL_CON0 |
| 1092 | // (RW) |
| 1093 | #define SCK_PU_ADDR 0xD0 |
| 1094 | #define SCK_PU_MASK 0x20 |
| 1095 | #define SCK_PU_SHIFT 5 |
| 1096 | |
| 1097 | // (RW) |
| 1098 | #define SCK_PD_ADDR 0xD0 |
| 1099 | #define SCK_PD_MASK 0x10 |
| 1100 | #define SCK_PD_SHIFT 4 |
| 1101 | |
| 1102 | // (RW) |
| 1103 | #define SCK_E2_ADDR 0xD0 |
| 1104 | #define SCK_E2_MASK 0x08 |
| 1105 | #define SCK_E2_SHIFT 3 |
| 1106 | |
| 1107 | // (RW) |
| 1108 | #define SCK_E4_ADDR 0xD0 |
| 1109 | #define SCK_E4_MASK 0x04 |
| 1110 | #define SCK_E4_SHIFT 2 |
| 1111 | |
| 1112 | // (RW) |
| 1113 | #define SCK_SMT_ADDR 0xD0 |
| 1114 | #define SCK_SMT_MASK 0x02 |
| 1115 | #define SCK_SMT_SHIFT 1 |
| 1116 | |
| 1117 | // (RW) |
| 1118 | #define SCK_SR_ADDR 0xD0 |
| 1119 | #define SCK_SR_MASK 0x01 |
| 1120 | #define SCK_SR_SHIFT 0 |
| 1121 | |
| 1122 | // (0x0D1) PAD_CTRL_CON1 |
| 1123 | // (RW) |
| 1124 | #define SDA_PU_ADDR 0xD1 |
| 1125 | #define SDA_PU_MASK 0x20 |
| 1126 | #define SDA_PU_SHIFT 5 |
| 1127 | |
| 1128 | // (RW) |
| 1129 | #define SDA_PD_ADDR 0xD1 |
| 1130 | #define SDA_PD_MASK 0x10 |
| 1131 | #define SDA_PD_SHIFT 4 |
| 1132 | |
| 1133 | // (RW) |
| 1134 | #define SDA_E2_ADDR 0xD1 |
| 1135 | #define SDA_E2_MASK 0x08 |
| 1136 | #define SDA_E2_SHIFT 3 |
| 1137 | |
| 1138 | // (RW) |
| 1139 | #define SDA_E4_ADDR 0xD1 |
| 1140 | #define SDA_E4_MASK 0x04 |
| 1141 | #define SDA_E4_SHIFT 2 |
| 1142 | |
| 1143 | // (RW) |
| 1144 | #define SDA_SMT_ADDR 0xD1 |
| 1145 | #define SDA_SMT_MASK 0x02 |
| 1146 | #define SDA_SMT_SHIFT 1 |
| 1147 | |
| 1148 | // (RW) |
| 1149 | #define SDA_SR_ADDR 0xD1 |
| 1150 | #define SDA_SR_MASK 0x01 |
| 1151 | #define SDA_SR_SHIFT 0 |
| 1152 | |
| 1153 | // (0x0D2) PAD_CTRL_CON2 |
| 1154 | // (RW) |
| 1155 | #define SRCLKEN_PU_ADDR 0xD2 |
| 1156 | #define SRCLKEN_PU_MASK 0x20 |
| 1157 | #define SRCLKEN_PU_SHIFT 5 |
| 1158 | |
| 1159 | // (RW) |
| 1160 | #define SRCLKEN_PD_ADDR 0xD2 |
| 1161 | #define SRCLKEN_PD_MASK 0x10 |
| 1162 | #define SRCLKEN_PD_SHIFT 4 |
| 1163 | |
| 1164 | // (RW) |
| 1165 | #define SRCLKEN_E2_ADDR 0xD2 |
| 1166 | #define SRCLKEN_E2_MASK 0x08 |
| 1167 | #define SRCLKEN_E2_SHIFT 3 |
| 1168 | |
| 1169 | // (RW) |
| 1170 | #define SRCLKEN_E4_ADDR 0xD2 |
| 1171 | #define SRCLKEN_E4_MASK 0x04 |
| 1172 | #define SRCLKEN_E4_SHIFT 2 |
| 1173 | |
| 1174 | // (RW) |
| 1175 | #define SRCLKEN_SMT_ADDR 0xD2 |
| 1176 | #define SRCLKEN_SMT_MASK 0x02 |
| 1177 | #define SRCLKEN_SMT_SHIFT 1 |
| 1178 | |
| 1179 | // (RW) |
| 1180 | #define SRCLKEN_SR_ADDR 0xD2 |
| 1181 | #define SRCLKEN_SR_MASK 0x01 |
| 1182 | #define SRCLKEN_SR_SHIFT 0 |
| 1183 | |
| 1184 | // (0x0E0) VERSION |
| 1185 | // (RO) |
| 1186 | #define VERSION_ADDR 0xE0 |
| 1187 | #define VERSION_MASK 0xFF |
| 1188 | #define VERSION_SHIFT 0 |
| 1189 | |
| 1190 | // (0x0F0) BIST_CTRL_CON0 |
| 1191 | // (RW) |
| 1192 | #define RG_VTCXO_BIST_EN_ADDR 0xF0 |
| 1193 | #define RG_VTCXO_BIST_EN_MASK 0x08 |
| 1194 | #define RG_VTCXO_BIST_EN_SHIFT 3 |
| 1195 | |
| 1196 | // (RW) |
| 1197 | #define RG_VA25_BIST_EN_ADDR 0xF0 |
| 1198 | #define RG_VA25_BIST_EN_MASK 0x01 |
| 1199 | #define RG_VA25_BIST_EN_SHIFT 0 |
| 1200 | |
| 1201 | // (0x0F1) BIST_CTRL_CON1 |
| 1202 | // (RW) |
| 1203 | #define RG_VM_BIST_EN_ADDR 0xF1 |
| 1204 | #define RG_VM_BIST_EN_MASK 0x08 |
| 1205 | #define RG_VM_BIST_EN_SHIFT 3 |
| 1206 | |
| 1207 | // (RW) |
| 1208 | #define RG_VMC_BIST_EN_ADDR 0xF1 |
| 1209 | #define RG_VMC_BIST_EN_MASK 0x04 |
| 1210 | #define RG_VMC_BIST_EN_SHIFT 2 |
| 1211 | |
| 1212 | // (RW) |
| 1213 | #define RG_VIO18_BIST_EN_ADDR 0xF1 |
| 1214 | #define RG_VIO18_BIST_EN_MASK 0x02 |
| 1215 | #define RG_VIO18_BIST_EN_SHIFT 1 |
| 1216 | |
| 1217 | // (RW) |
| 1218 | #define RG_VSIM_BIST_EN_ADDR 0xF1 |
| 1219 | #define RG_VSIM_BIST_EN_MASK 0x01 |
| 1220 | #define RG_VSIM_BIST_EN_SHIFT 0 |
| 1221 | |
| 1222 | // (0x0F2) BIST_CTRL_CON2 |
| 1223 | // (RW) |
| 1224 | #define RG_ABIST_MUX_ADDR 0xF2 |
| 1225 | #define RG_ABIST_MUX_MASK 0x0F |
| 1226 | #define RG_ABIST_MUX_SHIFT 0 |
| 1227 | |
| 1228 | //Register Group |
| 1229 | |
| 1230 | //Memory |
| 1231 | |
| 1232 | #define PMIC_BANK0_MAX_REG_IDX RG_ABIST_MUX_ADDR |
| 1233 | #define PMIC_BANK0_REG_NUM (PMIC_BANK0_MAX_REG_IDX + 1) |
| 1234 | |
| 1235 | #endif //#if defined(PMIC_6327_REG_API) |
| 1236 | |
| 1237 | #endif // #ifndef __DCL_PMIC6327_HW_H_STRUCT__ |