| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * dcl_pmu6236_hw.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Maui_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file is for PMU6236 |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
| 58 | * removed! |
| 59 | * removed! |
| 60 | * removed! |
| 61 | * |
| 62 | * removed! |
| 63 | * removed! |
| 64 | * removed! |
| 65 | * |
| 66 | * removed! |
| 67 | * removed! |
| 68 | * removed! |
| 69 | * |
| 70 | * removed! |
| 71 | * removed! |
| 72 | * removed! |
| 73 | * |
| 74 | * |
| 75 | *------------------------------------------------------------------------------ |
| 76 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 77 | *============================================================================ |
| 78 | ****************************************************************************/ |
| 79 | |
| 80 | |
| 81 | #ifndef __DCL_PMIC6236_HW_H_STRUCT__ |
| 82 | #define __DCL_PMIC6236_HW_H_STRUCT__ |
| 83 | |
| 84 | |
| 85 | #include "dcl_pmic_features.h" |
| 86 | |
| 87 | #if defined(PMIC_6236_REG_API) |
| 88 | |
| 89 | #define PMU_BASE MIXED_base |
| 90 | #define PMU_END (PMU_BASE+0x1000) |
| 91 | |
| 92 | // ===================================================================================== |
| 93 | |
| 94 | #define PMIC_LDO_BASE0 (PMU_BASE+0x800) |
| 95 | #define PMIC_LDO_BASE1 (PMU_BASE+0x804) |
| 96 | |
| 97 | #define PMIC_VRF_CON0 (PMU_BASE+0x800) |
| 98 | #define PMIC_VRF_CON1 (PMU_BASE+0x804) |
| 99 | #define PMIC_VRF_CON2 (PMU_BASE+0x808) |
| 100 | #define PMIC_VRF_CON3 (PMU_BASE+0x80C) |
| 101 | |
| 102 | #define PMIC_VTCXO_CON0 (PMU_BASE+0x810) |
| 103 | #define PMIC_VTCXO_CON1 (PMU_BASE+0x814) |
| 104 | #define PMIC_VTCXO_CON2 (PMU_BASE+0x818) |
| 105 | |
| 106 | #define PMIC_VA_CON0 (PMU_BASE+0x820) |
| 107 | #define PMIC_VA_CON1 (PMU_BASE+0x824) |
| 108 | #define PMIC_VA_CON2 (PMU_BASE+0x828) |
| 109 | |
| 110 | #define PMIC_VCAMA_CON0 (PMU_BASE+0x830) |
| 111 | #define PMIC_VCAMA_CON1 (PMU_BASE+0x834) |
| 112 | #define PMIC_VCAMA_CON2 (PMU_BASE+0x838) |
| 113 | |
| 114 | #define PMIC_VCAMD_CON0 (PMU_BASE+0x840) |
| 115 | #define PMIC_VCAMD_CON1 (PMU_BASE+0x844) |
| 116 | #define PMIC_VCAMD_CON2 (PMU_BASE+0x848) |
| 117 | |
| 118 | #define PMIC_VIO_CON0 (PMU_BASE+0x850) |
| 119 | #define PMIC_VIO_CON1 (PMU_BASE+0x854) |
| 120 | #define PMIC_VIO_CON2 (PMU_BASE+0x858) |
| 121 | |
| 122 | #define PMIC_VUSB_CON0 (PMU_BASE+0x860) |
| 123 | #define PMIC_VUSB_CON1 (PMU_BASE+0x864) |
| 124 | #define PMIC_VUSB_CON2 (PMU_BASE+0x868) |
| 125 | |
| 126 | #define PMIC_VBT_CON0 (PMU_BASE+0x870) |
| 127 | #define PMIC_VBT_CON1 (PMU_BASE+0x874) |
| 128 | #define PMIC_VBT_CON2 (PMU_BASE+0x878) |
| 129 | |
| 130 | #define PMIC_VSIM_CON0 (PMU_BASE+0x880) |
| 131 | #define PMIC_VSIM_CON1 (PMU_BASE+0x884) |
| 132 | #define PMIC_VSIM_CON2 (PMU_BASE+0x888) |
| 133 | #define PMIC_VSIM_CON3 (PMU_BASE+0x88C) |
| 134 | |
| 135 | #define PMIC_VSIM2_CON0 (PMU_BASE+0x890) |
| 136 | #define PMIC_VSIM2_CON1 (PMU_BASE+0x894) |
| 137 | #define PMIC_VSIM2_CON2 (PMU_BASE+0x898) |
| 138 | #define PMIC_VSIM2_CON3 (PMU_BASE+0x89C) |
| 139 | |
| 140 | #define PMIC_VBACKUP_CON0 (PMU_BASE+0x8A0) |
| 141 | #define PMIC_VBACKUP_CON1 (PMU_BASE+0x8A4) |
| 142 | #define PMIC_VBACKUP_CON2 (PMU_BASE+0x8A8) |
| 143 | |
| 144 | #define PMIC_VBIR_CON0 (PMU_BASE+0x8B0) |
| 145 | #define PMIC_VBIR_CON1 (PMU_BASE+0x8B4) |
| 146 | #define PMIC_VBIR_CON2 (PMU_BASE+0x8B8) |
| 147 | |
| 148 | #define PMIC_VMC_CON0 (PMU_BASE+0x8C0) |
| 149 | #define PMIC_VMC_CON1 (PMU_BASE+0x8C4) |
| 150 | #define PMIC_VMC_CON2 (PMU_BASE+0x8C8) |
| 151 | |
| 152 | #define PMIC_VCORE_CON0 (PMU_BASE+0x900) |
| 153 | #define PMIC_VCORE_CON1 (PMU_BASE+0x904) |
| 154 | #define PMIC_VCORE_CON2 (PMU_BASE+0x908) |
| 155 | #define PMIC_VCORE_CON3 (PMU_BASE+0x90C) |
| 156 | #define PMIC_VCORE_CON4 (PMU_BASE+0x910) |
| 157 | #define PMIC_VCORE_CON5 (PMU_BASE+0x914) |
| 158 | #define PMIC_VCORE_CON6 (PMU_BASE+0x918) |
| 159 | |
| 160 | #define PMIC_VM_CON0 (PMU_BASE+0x920) |
| 161 | #define PMIC_VM_CON1 (PMU_BASE+0x924) |
| 162 | #define PMIC_VM_CON2 (PMU_BASE+0x928) |
| 163 | #define PMIC_VM_CON3 (PMU_BASE+0x92C) |
| 164 | #define PMIC_VM_CON4 (PMU_BASE+0x930) |
| 165 | #define PMIC_VM_CON5 (PMU_BASE+0x934) |
| 166 | #define PMIC_VM_CON6 (PMU_BASE+0x938) |
| 167 | |
| 168 | |
| 169 | #define PMIC_BOOST_CON0 (PMU_BASE+0xB00) |
| 170 | #define PMIC_BOOST_CON1 (PMU_BASE+0xB04) |
| 171 | #define PMIC_BOOST_CON2 (PMU_BASE+0xB08) |
| 172 | #define PMIC_BOOST_CON3 (PMU_BASE+0xB0C) |
| 173 | |
| 174 | #define PMIC_BL_CON0 (PMU_BASE+0xB80) |
| 175 | #define PMIC_BL_CON1 (PMU_BASE+0xB84) |
| 176 | |
| 177 | |
| 178 | #define PMIC_CHR_CON0 (PMU_BASE+0xA00) |
| 179 | #define PMIC_CHR_CON1 (PMU_BASE+0xA04) |
| 180 | #define PMIC_CHR_CON2 (PMU_BASE+0xA08) |
| 181 | #define PMIC_CHR_CON3 (PMU_BASE+0xA0C) |
| 182 | #define PMIC_CHR_CON4 (PMU_BASE+0xA10) |
| 183 | #define PMIC_CHR_CON5 (PMU_BASE+0xA14) |
| 184 | #define PMIC_CHR_CON6 (PMU_BASE+0xA18) |
| 185 | #define PMIC_CHR_CON7 (PMU_BASE+0xA1C) |
| 186 | #define PMIC_CHR_CON8 (PMU_BASE+0xA20) |
| 187 | #define PMIC_CHR_CON9 (PMU_BASE+0xA24) |
| 188 | |
| 189 | #define PMIC_STRUP_CON0 (PMU_BASE+0xA80) |
| 190 | #define PMIC_STRUP_CON1 (PMU_BASE+0xA84) |
| 191 | |
| 192 | #define PMIC_ISINK0_CON0 (PMU_BASE+0xC00) |
| 193 | #define PMIC_ISINK0_CON1 (PMU_BASE+0xC04) |
| 194 | |
| 195 | #define PMIC_ISINK1_CON0 (PMU_BASE+0xC10) |
| 196 | #define PMIC_ISINK2_CON0 (PMU_BASE+0xC20) |
| 197 | #define PMIC_ISINK3_CON0 (PMU_BASE+0xC30) |
| 198 | #define PMIC_ISINK4_CON0 (PMU_BASE+0xC40) |
| 199 | |
| 200 | #define PMIC_KPLED_CON0 (PMU_BASE+0xC80) |
| 201 | #define PMIC_KPLED_CON1 (PMU_BASE+0xC84) |
| 202 | |
| 203 | #define PMIC_FLASH_CON0 (PMU_BASE+0xC90) |
| 204 | #define PMIC_FLASH_CON1 (PMU_BASE+0xC94) |
| 205 | |
| 206 | |
| 207 | #define PMIC_SPK_CON0 (PMU_BASE+0xD00) |
| 208 | #define PMIC_SPK_CON1 (PMU_BASE+0xD04) |
| 209 | #define PMIC_SPK_CON2 (PMU_BASE+0xD08) |
| 210 | #define PMIC_SPK_CON3 (PMU_BASE+0xD0C) |
| 211 | |
| 212 | |
| 213 | #define PMIC_TEST_CON0 (PMU_BASE+0xF00) |
| 214 | #define PMIC_TEST_CON1 (PMU_BASE+0xF04) |
| 215 | |
| 216 | #define PMIC_OC_CON0 (PMU_BASE+0xE00) |
| 217 | #define PMIC_OC_CON1 (PMU_BASE+0xE04) |
| 218 | #define PMIC_OC_CON2 (PMU_BASE+0xE08) |
| 219 | #define PMIC_OC_CON3 (PMU_BASE+0xE0C) |
| 220 | #define PMIC_OC_CON4 (PMU_BASE+0xE10) |
| 221 | #define PMIC_OC_CON5 (PMU_BASE+0xE14) |
| 222 | #define PMIC_OC_CON6 (PMU_BASE+0xE18) |
| 223 | #define PMIC_OC_CON7 (PMU_BASE+0xE1C) |
| 224 | |
| 225 | |
| 226 | #define LDO_EN_MASK 0x0001 |
| 227 | #define LD0_EN_SHIFT 0 |
| 228 | #define LDO_ON_SEL_MASK 0x0002 |
| 229 | #define LDO_ON_SEL_SHIFT 1 |
| 230 | #define LDO_SENSE_MASK 0x0004 |
| 231 | #define LDO_SENSE_SHIFT 2 |
| 232 | #define LDO_OCFB_EN_MASK 0x2000 |
| 233 | #define LDO_OCFB_EN_SHIFT 13 |
| 234 | #define LDO_STATUS_MASK 0x8000 |
| 235 | #define LDO_STATUS_SHIFT 15 |
| 236 | |
| 237 | #define LDO_CAL_MASK 0x00F0 |
| 238 | #define LDO_CAL_SHIFT 4 |
| 239 | |
| 240 | |
| 241 | // ===================================================================================== |
| 242 | // (0x800) VRF_CON0 |
| 243 | #define VRF_EN_MASK 0x0001 |
| 244 | #define VRF_EN_SHIFT 0 |
| 245 | #define VRF_ON_SEL_MASK 0x0002 |
| 246 | #define VRF_ON_SEL_SHIFT 1 |
| 247 | #define VRF_REMOTE_SENSE_MASK 0x0004 |
| 248 | #define VRF_REMOTE_SENSE_SHIFT 2 |
| 249 | #define VRF_NDIS_EN_MASK 0x0400 |
| 250 | #define VRF_NDIS_EN_SHIFT 10 |
| 251 | #define VRF_STB_EN_MASK 0x0800 |
| 252 | #define VRF_STB_EN_SHIFT 11 |
| 253 | #define VRF_OC_AUTO_OFF_MASK 0x1000 |
| 254 | #define VRF_OC_AUTO_OFF_SHIFT 12 |
| 255 | #define VRF_OCFB_EN_MASK 0x2000 |
| 256 | #define VRF_OCFB_EN_SHIFT 13 |
| 257 | #define VRF_STATUS_MASK 0x8000 |
| 258 | #define VRF_STATUS_SHIFT 15 |
| 259 | |
| 260 | // (0x804) VRF_CON1 |
| 261 | #define VRF_CAL_MASK 0x00F0 |
| 262 | #define VRF_CAL_SHIFT 4 |
| 263 | |
| 264 | // (0x810) VTCXO_CON0 |
| 265 | #define VTCXO_EN_MASK 0x0001 |
| 266 | #define VTCXO_EN_SHIFT 0 |
| 267 | #define VTCXO_ON_SEL_MASK 0x0002 |
| 268 | #define VTCXO_ON_SEL_SHIFT 1 |
| 269 | #define VTCXO_REMOTE_SENSE_MASK 0x0004 |
| 270 | #define VTCXO_REMOTE_SENSE_SHIFT 2 |
| 271 | #define VTCXO_NDIS_EN_MASK 0x0400 |
| 272 | #define VTCXO_NDIS_EN_SHIFT 10 |
| 273 | #define VTCXO_STB_EN_MASK 0x0800 |
| 274 | #define VTCXO_STB_EN_SHIFT 11 |
| 275 | #define VTCXO_OC_AUTO_OFF_MASK 0x1000 |
| 276 | #define VTCXO_OC_AUTO_OFF_SHIFT 12 |
| 277 | #define VTCXO_OCFB_EN_MASK 0x2000 |
| 278 | #define VTCXO_OCFB_EN_SHIFT 13 |
| 279 | #define VTCXO_STATUS_MASK 0x8000 |
| 280 | #define VTCXO_STATUS_SHIFT 15 |
| 281 | |
| 282 | // (0x814) VTCXO_CON1 |
| 283 | #define VTCXO_CAL_MASK 0x00F0 |
| 284 | #define VTCXO_CAL_SHIFT 4 |
| 285 | |
| 286 | // (0x820) VA_CON0 |
| 287 | #define VA_REMOTE_SENSE_MASK 0x0004 |
| 288 | #define VA_REMOTE_SENSE_SHIFT 2 |
| 289 | #define VA_NDIS_EN_MASK 0x0400 |
| 290 | #define VA_NDIS_EN_SHIFT 10 |
| 291 | #define VA_STB_EN_MASK 0x0800 |
| 292 | #define VA_STB_EN_SHIFT 11 |
| 293 | #define VA_OC_AUTO_OFF_MASK 0x1000 |
| 294 | #define VA_OC_AUTO_OFF_SHIFT 12 |
| 295 | #define VA_OCFB_EN_MASK 0x2000 |
| 296 | #define VA_OCFB_EN_SHIFT 13 |
| 297 | #define VA_STATUS_MASK 0x8000 |
| 298 | #define VA_STATUS_SHIFT 15 |
| 299 | |
| 300 | // (0x824) VA_CON1 |
| 301 | #define VA_CAL_MASK 0x00F0 |
| 302 | #define VA_CAL_SHIFT 4 |
| 303 | |
| 304 | // (0x830) VCAMA_CON0 |
| 305 | #define VCAMA_EN_MASK 0x0001 |
| 306 | #define VCAMA_EN_SHIFT 0 |
| 307 | #define VCAMA_ON_SEL_MASK 0x0002 |
| 308 | #define VCAMA_ON_SEL_SHIFT 1 |
| 309 | #define VCAMA_VOSEL_MASK 0x0030 |
| 310 | #define VCAMA_VOSEL_SHIFT 4 |
| 311 | #define VCAMA_NDIS_EN_MASK 0x0400 |
| 312 | #define VCAMA_NDIS_EN_SHIFT 10 |
| 313 | #define VCAMA_STB_EN_MASK 0x0800 |
| 314 | #define VCAMA_STB_EN_SHIFT 11 |
| 315 | #define VCAMA_OC_AUTO_OFF_MASK 0x1000 |
| 316 | #define VCAMA_OC_AUTO_OFF_SHIFT 12 |
| 317 | #define VCAMA_OCFB_EN_MASK 0x2000 |
| 318 | #define VCAMA_OCFB_EN_SHIFT 13 |
| 319 | #define VCAMA_STATUS_MASK 0x8000 |
| 320 | #define VCAMA_STATUS_SHIFT 15 |
| 321 | |
| 322 | // (0x834) VCAMA_CON1 |
| 323 | #define VCAMA_CAL_MASK 0x00F0 |
| 324 | #define VCAMA_CAL_SHIFT 4 |
| 325 | |
| 326 | // (0x838) VCAMA_CON2 |
| 327 | #define VCAMA_OC_TD_MASK 0x0030 |
| 328 | #define VCAMA_OC_TD_SHIFT 4 |
| 329 | #define VCAMA_STB_TD_MASK 0x00C0 |
| 330 | #define VCAMA_STB_TD_SHIFT 6 |
| 331 | |
| 332 | // (0x840) VCAMD_CON0 |
| 333 | #define VCAMD_EN_MASK 0x0001 |
| 334 | #define VCAMD_EN_SHIFT 0 |
| 335 | #define VCAMD_ON_SEL_MASK 0x0002 |
| 336 | #define VCAMD_ON_SEL_SHIFT 1 |
| 337 | #define VCAMD_VOSEL_MASK 0x0070 |
| 338 | #define VCAMD_VOSEL_SHIFT 4 |
| 339 | #define VCAMD_NDIS_EN_MASK 0x0400 |
| 340 | #define VCAMD_NDIS_EN_SHIFT 10 |
| 341 | #define VCAMD_STB_EN_MASK 0x0800 |
| 342 | #define VCAMD_STB_EN_SHIFT 11 |
| 343 | #define VCAMD_OC_AUTO_OFF_MASK 0x1000 |
| 344 | #define VCAMD_OC_AUTO_OFF_SHIFT 12 |
| 345 | #define VCAMD_OCFB_EN_MASK 0x2000 |
| 346 | #define VCAMD_OCFB_EN_SHIFT 13 |
| 347 | #define VCAMD_STATUS_MASK 0x8000 |
| 348 | #define VCAMD_STATUS_SHIFT 15 |
| 349 | |
| 350 | // (0x844) VCAMD CON1 |
| 351 | #define VCAMD_CAL_MASK 0x00F0 |
| 352 | #define VCAMD_CAL_SHIFT 4 |
| 353 | |
| 354 | // (0x850) VIO_CON0 |
| 355 | #define VIO_REMOTE_SENSE_MASK 0x0004 |
| 356 | #define VIO_REMOTE_SENSE_SHIFT 2 |
| 357 | #define VIO_OC_AUTO_OFF_MASK 0x1000 |
| 358 | #define VIO_NDIS_EN_MASK 0x0400 |
| 359 | #define VIO_NDIS_EN_SHIFT 10 |
| 360 | #define VIO_STB_EN_MASK 0x0800 |
| 361 | #define VIO_STB_EN_SHIFT 11 |
| 362 | #define VIO_OC_AUTO_OFF_SHIFT 12 |
| 363 | #define VIO_OCFB_EN_MASK 0x2000 |
| 364 | #define VIO_OCFB_EN_SHIFT 13 |
| 365 | #define VIO_STATUS_MASK 0x8000 |
| 366 | #define VIO_STATUS_SHIFT 15 |
| 367 | |
| 368 | // (0x854) VIO_CON1 |
| 369 | #define VIO_CAL_MASK 0x00F0 |
| 370 | #define VIO_CAL_SHIFT 4 |
| 371 | |
| 372 | // (0x858) VIO_CON2 |
| 373 | #define VIO_OC_TD_MASK 0x0030 |
| 374 | #define VIO_OC_TD_SHIFT 4 |
| 375 | |
| 376 | // (0x860) VUSB_CON0 |
| 377 | #define VUSB_EN_MASK 0x0001 |
| 378 | #define VUSB_EN_SHIFT 0 |
| 379 | #define VUSB_NDIS_EN_MASK 0x0400 |
| 380 | #define VUSB_NDIS_EN_SHIFT 10 |
| 381 | #define VUSB_STB_EN_MASK 0x0800 |
| 382 | #define VUSB_STB_EN_SHIFT 11 |
| 383 | #define VUSB_OC_AUTO_OFF_MASK 0x1000 |
| 384 | #define VUSB_OC_AUTO_OFF_SHIFT 12 |
| 385 | #define VUSB_OCFB_EN_MASK 0x2000 |
| 386 | #define VUSB_OCFB_EN_SHIFT 13 |
| 387 | #define VUSB_STATUS_MASK 0x8000 |
| 388 | #define VUSB_STATUS_SHIFT 15 |
| 389 | |
| 390 | // (0x864) VUSB_CON1 |
| 391 | #define VUSB_CAL_MASK 0x00F0 |
| 392 | #define VUSB_CAL_SHIFT 4 |
| 393 | |
| 394 | // (0x868) VUSB_CON2 |
| 395 | #define VUSB_OC_TD_MASK 0x0030 |
| 396 | #define VUSB_OC_TD_SHIFT 4 |
| 397 | #define VUSB_STB_TD_MASK 0x00C0 |
| 398 | #define VUSB_STB_TD_SHIFT 6 |
| 399 | |
| 400 | // (0x870) VBT CON0 |
| 401 | #define VBT_EN_MASK 0x0001 |
| 402 | #define VBT_EN_SHIFT 0 |
| 403 | #define VBT_VOSEL_MASK 0x0010 |
| 404 | #define VBT_VOSEL_SHIFT 4 |
| 405 | #define VBT_NDIS_EN_MASK 0x0400 |
| 406 | #define VBT_NDIS_EN_SHIFT 10 |
| 407 | #define VBT_STB_EN_MASK 0x0800 |
| 408 | #define VBT_STB_EN_SHIFT 11 |
| 409 | #define VBT_OC_AUTO_OFF_MASK 0x1000 |
| 410 | #define VBT_OC_AUTO_OFF_SHIFT 12 |
| 411 | #define VBT_OCFB_EN_MASK 0x2000 |
| 412 | #define VBT_OCFB_EN_SHIFT 13 |
| 413 | #define VBT_STATUS_MASK 0x8000 |
| 414 | #define VBT_STATUS_SHIFT 15 |
| 415 | |
| 416 | // (0x874) VBT CON1 |
| 417 | #define VBT_CAL_MASK 0x00F0 |
| 418 | #define VBT_CAL_SHIFT 4 |
| 419 | |
| 420 | // (0x878) VBT CON2 |
| 421 | #define VBT_OC_TD_MASK 0x0030 |
| 422 | #define VBT_OC_TD_SHIFT 4 |
| 423 | #define VBT_STB_TD_MASK 0x00C0 |
| 424 | #define VBT_STB_TD_SHIFT 6 |
| 425 | |
| 426 | // (0x880) VSIM CON0 |
| 427 | #define VSIM_EN_MASK 0x0001 |
| 428 | #define VSIM_EN_SHIFT 0 |
| 429 | #define VSIM_VOSEL_MASK 0x0010 |
| 430 | #define VSIM_VOSEL_SHIFT 4 |
| 431 | #define VSIM_NDIS_EN_MASK 0x0400 |
| 432 | #define VSIM_NDIS_EN_SHIFT 10 |
| 433 | #define VSIM_STB_EN_MASK 0x0800 |
| 434 | #define VSIM_STB_EN_SHIFT 11 |
| 435 | #define VSIM_OC_AUTO_OFF_MASK 0x1000 |
| 436 | #define VSIM_OC_AUTO_OFF_SHIFT 12 |
| 437 | #define VSIM_OCFB_EN_MASK 0x2000 |
| 438 | #define VSIM_OCFB_EN_SHIFT 13 |
| 439 | #define VSIM_STATUS_MASK 0x8000 |
| 440 | #define VSIM_STATUS_SHIFT 15 |
| 441 | |
| 442 | // (0x884) VSIM_CON1 |
| 443 | #define VSIM_CAL_MASK 0x00F0 |
| 444 | #define VSIM_CAL_SHIFT 4 |
| 445 | |
| 446 | // (0x888) VSIM_CON2 |
| 447 | #define VSIM_OC_TD_MASK 0x0030 |
| 448 | #define VSIM_OC_TD_SHIFT 4 |
| 449 | |
| 450 | // (0x890) VSIM2 CON0 |
| 451 | #define VSIM2_EN_MASK 0x0001 |
| 452 | #define VSIM2_EN_SHIFT 0 |
| 453 | #define VSIM2_VOSEL_MASK 0x0070 |
| 454 | #define VSIM2_VOSEL_SHIFT 4 |
| 455 | #define VSIM2_NDIS_EN_MASK 0x0400 |
| 456 | #define VSIM2_NDIS_EN_SHIFT 10 |
| 457 | #define VSIM2_STB_EN_MASK 0x0800 |
| 458 | #define VSIM2_STB_EN_SHIFT 11 |
| 459 | #define VSIM2_OC_AUTO_OFF_MASK 0x1000 |
| 460 | #define VSIM2_OC_AUTO_OFF_SHIFT 12 |
| 461 | #define VSIM2_OCFB_EN_MASK 0x2000 |
| 462 | #define VSIM2_OCFB_EN_SHIFT 13 |
| 463 | #define VSIM2_STATUS_MASK 0x8000 |
| 464 | #define VSIM2_STATUS_SHIFT 15 |
| 465 | |
| 466 | // (0x894) VSIM2_CON1 |
| 467 | #define VSIM2_CAL_MASK 0x00F0 |
| 468 | #define VSIM2_CAL_SHIFT 4 |
| 469 | |
| 470 | // (0x898) VSIM2_CON2 |
| 471 | #define VSIM2_GPLDO_EN_MASK 0x0002 |
| 472 | #define VSIM2_GPLDO_EN_SHIFT 1 |
| 473 | |
| 474 | |
| 475 | // (0x8A0) VBACKUP_CON0 |
| 476 | #define VBACKUP_EN_MASK 0x0001 |
| 477 | #define VBACKUP_EN_SHIFT 0 |
| 478 | #define VBACKUP_NDIS_EN_MASK 0x0400 |
| 479 | #define VBACKUP_NDIS_EN_SHIFT 10 |
| 480 | #define VBACKUP_STB_EN_MASK 0x0800 |
| 481 | #define VBACKUP_STB_EN_SHIFT 11 |
| 482 | #define VBACKUP_OC_AUTO_OFF_MASK 0x1000 |
| 483 | #define VBACKUP_OC_AUTO_OFF_SHIFT 12 |
| 484 | #define VBACKUP_OCFB_EN_MASK 0x2000 |
| 485 | #define VBACKUP_OCFB_EN_SHIFT 13 |
| 486 | #define VBACKUP_STATUS_MASK 0x8000 |
| 487 | #define VBACKUP_STATUS_SHIFT 15 |
| 488 | |
| 489 | // (0x8B0) Vibr_CON0 |
| 490 | #define VIBR_EN_MASK 0x0001 |
| 491 | #define VIBR_EN_SHIFT 0 |
| 492 | #define VIBR_VOSEL_MASK 0x0070 |
| 493 | #define VIBR_VOSEL_SHIFT 4 |
| 494 | #define VIBR_NDIS_EN_MASK 0x0400 |
| 495 | #define VIBR_NDIS_EN_SHIFT 10 |
| 496 | #define VIBR_STB_EN_MASK 0x0800 |
| 497 | #define VIBR_STB_EN_SHIFT 11 |
| 498 | #define VIBR_OC_AUTO_OFF_MASK 0x1000 |
| 499 | #define VIBR_OC_AUTO_OFF_SHIFT 12 |
| 500 | #define VIBR_OCFB_EN_MASK 0x2000 |
| 501 | #define VIBR_OCFB_EN_SHIFT 13 |
| 502 | #define VIBR_STATUS_MASK 0x8000 |
| 503 | #define VIBR_STATUS_SHIFT 15 |
| 504 | |
| 505 | // (0x8B4) VIBR_CON1 |
| 506 | #define VIBR_CAL_MASK 0x00F0 |
| 507 | #define VIBR_CAL_SHIFT 4 |
| 508 | |
| 509 | // (0x8C0) VMC_CON0 |
| 510 | #define VMC_EN_MASK 0x0001 |
| 511 | #define VMC_EN_SHIFT 0 |
| 512 | #define VMC_VOSEL_MASK 0x0070 |
| 513 | #define VMC_VOSEL_SHIFT 4 |
| 514 | #define VMC_NDIS_EN_MASK 0x0400 |
| 515 | #define VMC_NDIS_EN_SHIFT 10 |
| 516 | #define VMC_STB_EN_MASK 0x0800 |
| 517 | #define VMC_STB_EN_SHIFT 11 |
| 518 | #define VMC_OC_AUTO_OFF_MASK 0x1000 |
| 519 | #define VMC_OC_AUTO_OFF_SHIFT 12 |
| 520 | #define VMC_OCFB_EN_MASK 0x2000 |
| 521 | #define VMC_OCFB_EN_SHIFT 13 |
| 522 | #define VMC_STATUS_MASK 0x8000 |
| 523 | #define VMC_STATUS_SHIFT 15 |
| 524 | |
| 525 | // (0x08C4) VMC_CON1 |
| 526 | #define VMC_CAL_MASK 0x00F0 |
| 527 | #define VMC_CAL_SHIFT 4 |
| 528 | |
| 529 | // (0x900) VCORE_CON0 |
| 530 | #define VCORE_EN_MASK 0x0001 |
| 531 | #define VCORE_EN_SHIFT 0 |
| 532 | #define VCORE_REMOTE_SENSE_MASK 0x0004 |
| 533 | #define VCORE_REMOTE_SENSE_SHIFT 2 |
| 534 | #define VCORE_VFBADJ_MASK 0x01F0 |
| 535 | #define VCORE_VFBADJ_SHIFT 4 |
| 536 | #define VCORE_STB_EN_MASK 0x0800 |
| 537 | #define VCORE_STB_EN_SHIFT 11 |
| 538 | #define VCORE_OC_AUTO_OFF_MASK 0x1000 |
| 539 | #define VCORE_OC_AUTO_OFF_SHIFT 12 |
| 540 | #define VCORE_OCFB_EN_MASK 0x2000 |
| 541 | #define VCORE_OCFB_EN_SHIFT 13 |
| 542 | #define VCORE_STATUS_MASK 0x8000 |
| 543 | #define VCORE_STATUS_SHIFT 15 |
| 544 | |
| 545 | // (0x904) VCORE_CON1 |
| 546 | #define VCORE_MODE_SET_MASK 0x0001 |
| 547 | #define VCORE_MODE_SET_SHIFT 0 |
| 548 | #define VCORE_VFBADJ_SLEEP_MASK 0x01F0 |
| 549 | #define VCORE_VFBADJ_SLEEP_SHIFT 4 |
| 550 | #define VCORE_CPMCKSEL_MASK 0x0400 |
| 551 | #define VCORE_CPMCKSEL_SHIFT 10 |
| 552 | |
| 553 | // (0x908) VCORE_CON2 |
| 554 | #define VCORE_VOSEL_MASK 0x0007 |
| 555 | #define VCORE_VOSEL_SHIFT 0 |
| 556 | #define VCORE_CAL_MASK 0x00F0 |
| 557 | #define VCORE_CAL_SHIFT 4 |
| 558 | |
| 559 | // (0x90C) VCORE_CON3 |
| 560 | #define VCORE_ICAL_EN_MASK 0x3000 |
| 561 | #define VCORE_ICAL_EN_SHIFT 12 |
| 562 | |
| 563 | // (0x914) VCORE_CON5 |
| 564 | #define VCORE_CSL_MASK 0x0700 |
| 565 | #define VCORE_CSL_SHIFT 8 |
| 566 | #define VCORE_BURST_MASK 0x3000 |
| 567 | #define VCORE_BURST_SHIFT 12 |
| 568 | |
| 569 | // (0x920) VM_CON0 |
| 570 | #define VM_REMOTE_SENSE_MASK 0x0004 |
| 571 | #define VM_REMOTE_SENSE_SHIFT 2 |
| 572 | #define VM_STB_EN_MASK 0x0800 |
| 573 | #define VM_STB_EN_SHIFT 11 |
| 574 | #define VM_OC_AUTO_OFF_MASK 0x1000 |
| 575 | #define VM_OC_AUTO_OFF_SHIFT 12 |
| 576 | #define VM_OCFB_EN_MASK 0x2000 |
| 577 | #define VM_OCFB_EN_SHIFT 13 |
| 578 | #define VM_STATUS_MASK 0x8000 |
| 579 | #define VM_STATUS_SHIFT 15 |
| 580 | |
| 581 | // (0x928) VM_CON2 |
| 582 | #define VM_CAL_MASK 0x00F0 |
| 583 | #define VM_CAL_SHIFT 4 |
| 584 | |
| 585 | // (0x92C) VM_CON3 |
| 586 | #define VM_ICAL_EN_MASK 0x3000 |
| 587 | #define VM_ICAL_EN_SHIFT 12 |
| 588 | |
| 589 | // (0x92C) VM_CON5 |
| 590 | #define VM_CSL_MASK 0x0700 |
| 591 | #define VM_CSL_SHIFT 8 |
| 592 | #define VM_BURST_MASK 0x3000 |
| 593 | #define VM_BURST_SHIFT 12 |
| 594 | |
| 595 | // (0xA00) CHR_CON0 |
| 596 | #define VCDT_LV_VTH_MASK 0x000F |
| 597 | #define VCDT_LV_VTH_SHIFT 0 |
| 598 | #define VCDT_HV_VTH_MASK 0x00F0 |
| 599 | #define VCDT_HV_VTH_SHIFT 4 |
| 600 | #define VCDT_HV_EN_MASK 0x0100 |
| 601 | #define VCDT_HV_EN_SHIFT 8 |
| 602 | #define CSDAC_EN_MASK 0x0800 |
| 603 | #define CSDAC_EN_SHIFT 11 |
| 604 | #define CHR_EN_MASK 0x1000 |
| 605 | #define CHR_EN_SHIFT 12 |
| 606 | #define CHRDET_MASK 0x2000 |
| 607 | #define CHRDET_SHIFT 13 |
| 608 | #define VCDT_HV_DET_MASK 0x8000 |
| 609 | #define VCDT_HV_DET_SHIFT 15 |
| 610 | |
| 611 | // (0xA04) CHR_CON1 |
| 612 | #define VBAT_CV_VTH_MASK 0x001F |
| 613 | #define VBAT_CV_VTH_SHIFT 0 |
| 614 | #define VBAT_CC_VTH_MASK 0x00C0 |
| 615 | #define VBAT_CC_VTH_SHIFT 6 |
| 616 | #define VBAT_CV_EN_MASK 0x0100 |
| 617 | #define VBAT_CV_EN_SHIFT 8 |
| 618 | #define VBAT_CC_EN_MASK 0x0200 |
| 619 | #define VBAT_CC_EN_SHIFT 9 |
| 620 | #define VBAT_CV_DET_MASK 0x4000 |
| 621 | #define VBAT_CV_DET_SHIFT 14 |
| 622 | #define VBAT_CC_DET_MASK 0x8000 |
| 623 | #define VBAT_CC_DET_SHIFT 15 |
| 624 | |
| 625 | // (0xA08) CHR_CON2 |
| 626 | #define CS_EN_MASK 0x1000 |
| 627 | #define CS_EN_SHIFT 12 |
| 628 | #define CS_VTH_MASK 0x0700 |
| 629 | #define CS_VTH_SHIFT 8 |
| 630 | |
| 631 | // (0xA0C) CHR_CON3 |
| 632 | #define CSDAC_DLY_MASK 0x30 |
| 633 | #define CSDAC_DLY_SHIFT 4 |
| 634 | #define CSDAC_STP_MASK 0x3 |
| 635 | #define CSDAC_STP_SHIFT 0 |
| 636 | |
| 637 | // (0xA14) CHR_CON5 |
| 638 | #define PCHR_FLAG_SEL_MASK 0x000F |
| 639 | #define PCHR_FLAG_SEL_SHIFT 0 |
| 640 | #define PCHR_FLAG_EN_MASK 0x0080 |
| 641 | #define PCHR_FLAG_EN_SHIFT 7 |
| 642 | #define PCHR_FLAG_OUT_MASK 0x0F00 |
| 643 | #define PCHR_FLAG_OUT_SHIFT 8 |
| 644 | // PCHR command result (The value is filled into PCHR_FLAG_OUT) |
| 645 | #define PCHR_STATE_MASK 0x7 |
| 646 | #define PCHR_STATE_SHIFT 0 |
| 647 | |
| 648 | |
| 649 | // (0xA18) CHR_CON6 |
| 650 | #define CHRWDT_TD_MASK 0x0007 |
| 651 | #define CHRWDT_TD_SHIFT 0 |
| 652 | #define CHRWDT_EN_MASK 0x0010 |
| 653 | #define CHRWDT_EN_SHIFT 4 |
| 654 | |
| 655 | // (0xA1C) CHR_CON7 |
| 656 | #define CHRWDT_INT_EN_MASK 0x0001 |
| 657 | #define CHRWDT_INT_EN_SHIFT 0 |
| 658 | #define CHRWDT_FLAG_MASK 0x0002 |
| 659 | #define CHRWDT_FLAG_SHIFT 1 |
| 660 | |
| 661 | // (0xA20) CHR_CON8 |
| 662 | #define ADCIN_VBAT_EN 0x1000 |
| 663 | #define ADCIN_VBAT_EN_SHIFT 12 |
| 664 | #define ADCIN_VSEN_EN 0x2000 |
| 665 | #define ADCIN_VSEN_EN_SHIFT 13 |
| 666 | #define ADCIN_VCHR_EN 0x4000 |
| 667 | #define ADCIN_VCHR_EN_SHIFT 14 |
| 668 | |
| 669 | // (0xB00) BOOST_CON0 |
| 670 | #define VBOOST_EN_MASK 0x0001 |
| 671 | #define VBOOST_EN_SHIFT 0 |
| 672 | #define VBOOST_TYPE_MASK 0x0002 |
| 673 | #define VBOOST_TYPE_SHIFT 1 |
| 674 | #define VBOOST_MODE_MASK 0x0004 |
| 675 | #define VBOOST_MODE_SHIFT 2 |
| 676 | #define VBOOST_VRSEL_MASK 0x01F0 |
| 677 | #define VBOOST_VRSEL_SHIFT 4 |
| 678 | |
| 679 | // (0xB0C) BOOST_CON3 |
| 680 | #define VBOOST_CKS_PRG_MASK 0x003F |
| 681 | #define VBOOST_CKS_PRG_SHIFT 0 |
| 682 | |
| 683 | // (0xC00) ISINK0_CON0 |
| 684 | #define ISINK0_EN_MASK 0x0001 |
| 685 | #define ISINK0_EN_SHIFT 0 |
| 686 | #define ISINK0_MODE_MASK 0x0002 |
| 687 | #define ISINK0_MODE_SHIFT 1 |
| 688 | #define ISINK0_STEP_MASK 0x0070 |
| 689 | #define ISINK0_STEP_SHIFT 4 |
| 690 | #define ISINK0_STATUS_MASK 0x8000 |
| 691 | #define ISINK0_STATUS_SHIFT 15 |
| 692 | |
| 693 | // (0xC10) ISINK1_CON0 |
| 694 | #define ISINK1_EN_MASK 0x0001 |
| 695 | #define ISINK1_EN_SHIFT 0 |
| 696 | #define ISINK1_MODE_MASK 0x0002 |
| 697 | #define ISINK1_MODE_SHIFT 1 |
| 698 | #define ISINK1_STEP_MASK 0x0070 |
| 699 | #define ISINK1_STEP_SHIFT 4 |
| 700 | #define ISINK1_STATUS_MASK 0x8000 |
| 701 | #define ISINK1_STATUS_SHIFT 15 |
| 702 | |
| 703 | // (0xC20) ISINK2_CON0 |
| 704 | #define ISINK2_EN_MASK 0x0001 |
| 705 | #define ISINK2_EN_SHIFT 0 |
| 706 | #define ISINK2_MODE_MASK 0x0002 |
| 707 | #define ISINK2_MODE_SHIFT 1 |
| 708 | #define ISINK2_STEP_MASK 0x0070 |
| 709 | #define ISINK2_STEP_SHIFT 4 |
| 710 | #define ISINK2_STATUS_MASK 0x8000 |
| 711 | #define ISINK2_STATUS_SHIFT 15 |
| 712 | |
| 713 | // (0xC30) ISINK3_CON0 |
| 714 | #define ISINK3_EN_MASK 0x0001 |
| 715 | #define ISINK3_EN_SHIFT 0 |
| 716 | #define ISINK3_MODE_MASK 0x0002 |
| 717 | #define ISINK3_MODE_SHIFT 1 |
| 718 | #define ISINK3_STEP_MASK 0x0070 |
| 719 | #define ISINK3_STEP_SHIFT 4 |
| 720 | #define ISINK3_STATUS_MASK 0x8000 |
| 721 | #define ISINK3_STATUS_SHIFT 15 |
| 722 | |
| 723 | // (0xC40) ISINK4_CON0 |
| 724 | #define ISINK4_EN_MASK 0x0001 |
| 725 | #define ISINK4_EN_SHIFT 0 |
| 726 | #define ISINK4_MODE_MASK 0x0002 |
| 727 | #define ISINK4_MODE_SHIFT 1 |
| 728 | #define ISINK4_STEP_MASK 0x0070 |
| 729 | #define ISINK4_STEP_SHIFT 4 |
| 730 | #define ISINK4_STATUS_MASK 0x8000 |
| 731 | #define ISINK4_STATUS_SHIFT 15 |
| 732 | |
| 733 | // (0xC80) KPLED CON0 |
| 734 | #define KPLED_EN_MASK 0x0001 |
| 735 | #define KPLED_EN_SHIFT 0 |
| 736 | #define KPLED_MODE_MASK 0x0002 |
| 737 | #define KPLED_MODE_SHIFT 1 |
| 738 | #define KPLED_SEL_MASK 0x0070 |
| 739 | #define KPLED_SEL_SHIFT 4 |
| 740 | #define KPLED_STATUS_MASK 0x8000 |
| 741 | #define KPLED_STATUS_SHIFT 15 |
| 742 | |
| 743 | // (0xC90) FLASH_CON0 |
| 744 | #define FLASH_EN_MASK 0x0001 |
| 745 | #define FLASH_EN_SHIFT 0 |
| 746 | #define FLASH_MODE_MASK 0x0002 |
| 747 | #define FLASH_MODE_SHIFT 1 |
| 748 | #define FLASH_SEL_MASK 0x0070 |
| 749 | #define FLASH_SEL_SHIFT 4 |
| 750 | #define FLASH_STATUS_MASK 0x8000 |
| 751 | #define FLASH_STATUS_SHIFT 15 |
| 752 | |
| 753 | // (0xD00) SPK_CON0 |
| 754 | #define SPK_EN_MASK 0x0001 |
| 755 | #define SPK_EN_SHIFT 0 |
| 756 | #define SPK_VOL_MASK 0x0010 |
| 757 | #define SPK_VOL_SHIFT 4 |
| 758 | #define SPK_OCFB_EN_MASK 0x2000 |
| 759 | #define SPK_OCFB_EN_SHIFT 13 |
| 760 | |
| 761 | // (0xE00) PMIC_OC_CON0 |
| 762 | #define VRF_OC_INT_EN_MASK 0x0001 |
| 763 | #define VRF_OC_INT_EN_SHIFT 0 |
| 764 | #define VTCXO_OC_INT_EN_MASK 0x0002 |
| 765 | #define VTCXO_OC_INT_EN_SHIFT 1 |
| 766 | #define VA_OC_INT_EN_MASK 0x0004 |
| 767 | #define VA_OC_INT_EN_SHIFT 2 |
| 768 | #define VCAMA_OC_INT_EN_MASK 0x0008 |
| 769 | #define VCAMA_OC_INT_EN_SHIFT 3 |
| 770 | #define VCAMD_OC_INT_EN_MASK 0x0010 |
| 771 | #define VCAMD_OC_INT_EN_SHIFT 4 |
| 772 | #define VIO_OC_INT_EN_MASK 0x0020 |
| 773 | #define VIO_OC_INT_EN_SHIFT 5 |
| 774 | #define VUSB_OC_INT_EN_MASK 0x0040 |
| 775 | #define VUSB_OC_INT_EN_SHIFT 6 |
| 776 | #define VBT_OC_INT_EN_MASK 0x0080 |
| 777 | #define VBT_OC_INT_EN_SHIFT 7 |
| 778 | #define VSIM_OC_INT_EN_MASK 0x0100 |
| 779 | #define VSIM_OC_INT_EN_SHIFT 8 |
| 780 | #define VSIM2_OC_INT_EN_MASK 0x0200 |
| 781 | #define VSIM2_OC_INT_EN_SHIFT 9 |
| 782 | #define VBACKUP_OC_INT_EN_MASK 0x0400 |
| 783 | #define VBACKUP_OC_INT_EN_SHIFT 10 |
| 784 | #define VIBR_OC_INT_EN_MASK 0x0800 |
| 785 | #define VIBR_OC_INT_EN_SHIFT 11 |
| 786 | #define VMC_OC_INT_EN_MASK 0x1000 |
| 787 | #define VMC_OC_INT_EN_SHIFT 12 |
| 788 | |
| 789 | // (0xE04) PMIC_OC_CON1 |
| 790 | #define VCORE_OC_INT_EN_MASK 0x0001 |
| 791 | #define VCORE_OC_INT_EN_SHIFT 0 |
| 792 | #define VM_OC_INT_EN_MASK 0x0002 |
| 793 | #define VM_OC_INT_EN_SHIFT 1 |
| 794 | |
| 795 | |
| 796 | |
| 797 | |
| 798 | //////////////////////////////////////////////////////////////// |
| 799 | |
| 800 | |
| 801 | |
| 802 | #endif // #if defined(PMIC_6236_REG_API) |
| 803 | |
| 804 | #endif // #ifndef __DCL_PMIC6236_HW_H_STRUCT__ |
| 805 | |
| 806 | |
| 807 | |
| 808 | |