| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * dcl_pmu6251_hw.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Maui_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file is intended for PMIC 6251 driver. |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
| 58 | * removed! |
| 59 | * removed! |
| 60 | * removed! |
| 61 | * |
| 62 | * removed! |
| 63 | * removed! |
| 64 | * removed! |
| 65 | * |
| 66 | * removed! |
| 67 | * removed! |
| 68 | * removed! |
| 69 | * |
| 70 | * removed! |
| 71 | * removed! |
| 72 | * removed! |
| 73 | * |
| 74 | * removed! |
| 75 | * removed! |
| 76 | * removed! |
| 77 | * |
| 78 | * removed! |
| 79 | * removed! |
| 80 | * removed! |
| 81 | * |
| 82 | * removed! |
| 83 | * removed! |
| 84 | * removed! |
| 85 | * |
| 86 | * removed! |
| 87 | * removed! |
| 88 | * removed! |
| 89 | * |
| 90 | *------------------------------------------------------------------------------ |
| 91 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 92 | *============================================================================ |
| 93 | ****************************************************************************/ |
| 94 | |
| 95 | #ifndef __PMU6251_HW_H__ |
| 96 | #define __PMU6251_HW_H__ |
| 97 | |
| 98 | #if defined(PMIC_6251_REG_API) |
| 99 | |
| 100 | #define PMU_BASE MIXED_base |
| 101 | #define PMU_END (PMU_BASE+0x1000) |
| 102 | |
| 103 | /////////////////////////////////////////////////////////////////////////////// |
| 104 | // LDO group |
| 105 | #define VRF_CON0 (PMU_BASE + 0x0800) |
| 106 | #define VTCXO_CON0 (PMU_BASE + 0x0810) |
| 107 | #define VA_CON0 (PMU_BASE + 0x0820) |
| 108 | #define VIO28_CON0 (PMU_BASE + 0x0850) |
| 109 | #define VUSB_CON0 (PMU_BASE + 0x0860) |
| 110 | #define VSF_CON0 (PMU_BASE + 0x0870) |
| 111 | #define VSIM_CON0 (PMU_BASE + 0x0880) |
| 112 | #define VSIM2_CON0 (PMU_BASE + 0x0890) |
| 113 | #define VRTC_CON0 (PMU_BASE + 0x08A0) |
| 114 | #define VIBR_CON0 (PMU_BASE + 0x08B0) |
| 115 | #define VFM_CON0 (PMU_BASE + 0x08D0) |
| 116 | #define VIO18_CON0 (PMU_BASE + 0x08F0) |
| 117 | |
| 118 | // BUCK group |
| 119 | #define VCORE_CON0 (PMU_BASE + 0x0900) |
| 120 | |
| 121 | // BOOST group |
| 122 | #define BOOST_CON0 (PMU_BASE + 0x0B00) |
| 123 | |
| 124 | // iSINK group |
| 125 | #define ISINK0_CON0 (PMU_BASE + 0x0C00) |
| 126 | #define ISINK1_CON0 (PMU_BASE + 0x0C10) |
| 127 | #define ISINK2_CON0 (PMU_BASE + 0x0C20) |
| 128 | #define ISINK3_CON0 (PMU_BASE + 0x0C30) |
| 129 | |
| 130 | // KPLED group |
| 131 | #define KPLED_CON0 (PMU_BASE + 0x0C80) |
| 132 | |
| 133 | // SPK |
| 134 | #define SPK_CON0 (PMU_BASE + 0x0D00) |
| 135 | |
| 136 | // CHR |
| 137 | #define CHR_CON0 (PMU_BASE + 0x0A00) |
| 138 | |
| 139 | #if defined(__MT6251PMU_E1_BC11_VSRC_EN_AT_TEST_CON1_BIT4__) |
| 140 | #define TEST_CON1 (PMU_BASE + 0x0F04) |
| 141 | #endif // #if defined(__MT6251PMU_E1_BC11_VSRC_EN_AT_TEST_CON1_BIT4__) |
| 142 | |
| 143 | // STARTUP |
| 144 | #define STRUP_CON0 (PMU_BASE + 0x0A80) |
| 145 | |
| 146 | /////////////////////////////////////////////////////////////////////////////// |
| 147 | |
| 148 | |
| 149 | // BC11 VSRC_EN |
| 150 | #define MT6251_E1_BC11_VSRC_EN_MASK 0x0030 |
| 151 | #define MT6251_E1_BC11_VSRC_EN_SHIFT 4 |
| 152 | |
| 153 | |
| 154 | #define CON0_OFFSET 0x00 |
| 155 | #define CON1_OFFSET 0x04 |
| 156 | #define CON2_OFFSET 0x08 |
| 157 | #define CON3_OFFSET 0x0C |
| 158 | #define CON4_OFFSET 0x10 |
| 159 | #define CON5_OFFSET 0x14 |
| 160 | #define CON6_OFFSET 0x18 |
| 161 | #define CON7_OFFSET 0x1C |
| 162 | #define CON8_OFFSET 0x20 |
| 163 | #define CON9_OFFSET 0x24 |
| 164 | |
| 165 | // LDO and BUCK cmds |
| 166 | #define LDO_BUCK_EN_OFFSET CON0_OFFSET |
| 167 | #define LDO_BUCK_EN_MASK 0x0001 |
| 168 | #define LDO_BUCK_EN_SHIFT 0 |
| 169 | |
| 170 | #define LDO_BUCK_VOL_SEL_OFFSET CON0_OFFSET |
| 171 | #define LDO_BUCK_VOL_SEL_MASK 0x01F0 |
| 172 | #define LDO_BUCK_VOL_SEL_SHIFT 4 |
| 173 | |
| 174 | #define LDO_BUCK_OC_AUTO_OFF_OFFSET CON0_OFFSET |
| 175 | #define LDO_BUCK_OC_AUTO_OFF_MASK 0x1000 |
| 176 | #define LDO_BUCK_OC_AUTO_OFF_SHIFT 12 |
| 177 | |
| 178 | #define LDO_BUCK_STB_EN_OFFSET CON0_OFFSET |
| 179 | #define LDO_BUCK_STB_EN_MASK 0x0800 |
| 180 | #define LDO_BUCK_STB_EN_SHIFT 11 |
| 181 | |
| 182 | #define LDO_BUCK_ON_SEL_OFFSET CON0_OFFSET |
| 183 | #define LDO_BUCK_ON_SEL_MASK 0x0002 |
| 184 | #define LDO_BUCK_ON_SEL_SHIFT 1 |
| 185 | |
| 186 | #define LDO_BUCK_NDIS_EN_OFFSET CON0_OFFSET |
| 187 | #define LDO_BUCK_NDIS_EN_MASK 0x0400 |
| 188 | #define LDO_BUCK_NDIS_EN_SHIFT 10 |
| 189 | |
| 190 | #define LDO_BUCK_OCFB_EN_OFFSET CON0_OFFSET |
| 191 | #define LDO_BUCK_OCFB_EN_MASK 0x2000 |
| 192 | #define LDO_BUCK_OCFB_EN_SHIFT 13 |
| 193 | |
| 194 | |
| 195 | // LDO cmds |
| 196 | #define LDO_CAL_OFFSET CON1_OFFSET |
| 197 | #define LDO_CAL_MASK 0x01F0 |
| 198 | #define LDO_CAL_SHIFT 4 |
| 199 | |
| 200 | #define LDO_STB_TD_OFFSET CON1_OFFSET |
| 201 | #define LDO_STB_TD_MASK 0x0003 |
| 202 | #define LDO_STB_TD_SHIFT 0 |
| 203 | |
| 204 | #define LDO_OC_TD_OFFSET CON2_OFFSET |
| 205 | #define LDO_OC_TD_MASK 0x0030 |
| 206 | #define LDO_OC_TD_SHIFT 4 |
| 207 | |
| 208 | // BUCK cmds |
| 209 | #define BUCK_VFBADJ_SLEEP_OFFSET CON1_OFFSET |
| 210 | #define BUCK_VFBADJ_SLEEP_MASK 0x01F0 |
| 211 | #define BUCK_VFBADJ_SLEEP_SHIFT 4 |
| 212 | |
| 213 | #define BUCK_ICAL_EN_OFFSET CON3_OFFSET |
| 214 | #define BUCK_ICAL_EN_MASK 0x3000 |
| 215 | #define BUCK_ICAL_EN_SHIFT 12 |
| 216 | |
| 217 | #define BUCK_CSL_OFFSET CON5_OFFSET |
| 218 | #define BUCK_CSL_MASK 0x0700 |
| 219 | #define BUCK_CSL_SHIFT 8 |
| 220 | |
| 221 | #define BUCK_STB_TD_OFFSET CON3_OFFSET |
| 222 | #define BUCK_STB_TD_MASK 0x00C0 |
| 223 | #define BUCK_STB_TD_SHIFT 6 |
| 224 | |
| 225 | #define BUCK_OC_THD_OFFSET CON3_OFFSET |
| 226 | #define BUCK_OC_THD_MASK 0x0300 |
| 227 | #define BUCK_OC_THD_SHIFT 8 |
| 228 | |
| 229 | #define BUCK_BURST_OFFSET CON5_OFFSET |
| 230 | #define BUCK_BURST_MASK 0x3000 |
| 231 | #define BUCK_BURST_SHIFT 12 |
| 232 | |
| 233 | // SPK |
| 234 | #define SPK_EN_OFFSET CON0_OFFSET |
| 235 | #define SPK_EN_MASK 0x0001 |
| 236 | #define SPK_EN_SHIFT 0 |
| 237 | |
| 238 | #define SPK_VOL_OFFSET CON0_OFFSET |
| 239 | #define SPK_VOL_MASK 0x01F0 |
| 240 | #define SPK_VOL_SHIFT 4 |
| 241 | |
| 242 | #define SPK_CCODE_OFFSET CON1_OFFSET |
| 243 | #define SPK_CCODE_MASK 0x00F0 |
| 244 | #define SPK_CCODE_SHIFT 4 |
| 245 | |
| 246 | #define SPK_OC_EN_OFFSET CON3_OFFSET |
| 247 | #define SPK_OC_EN_MASK 0x0400 |
| 248 | #define SPK_OC_EN_SHIFT 10 |
| 249 | |
| 250 | #define SPK_OSC_ISEL_OFFSET CON3_OFFSET |
| 251 | #define SPK_OSC_ISEL_MASK 0x00C0 |
| 252 | #define SPK_OSC_ISEL_SHIFT 6 |
| 253 | |
| 254 | #define SPK_NG_DT_DLY_OFFSET CON4_OFFSET |
| 255 | #define SPK_NG_DT_DLY_MASK 0x000f |
| 256 | #define SPK_NG_DT_DLY_SHIFT 0 |
| 257 | |
| 258 | #define SPK_OCP_BIAS_OFFSET CON4_OFFSET |
| 259 | #define SPK_OCP_BIAS_MASK 0x7000 |
| 260 | #define SPK_OCP_BIAS_SHIFT 12 |
| 261 | |
| 262 | #define SPK_OCN_BIAS_OFFSET CON4_OFFSET |
| 263 | #define SPK_OCN_BIAS_MASK 0x0700 |
| 264 | #define SPK_OCN_BIAS_SHIFT 8 |
| 265 | |
| 266 | |
| 267 | #define SPK_PG_SLEW_I_OFFSET CON5_OFFSET |
| 268 | #define SPK_PG_SLEW_I_MASK 0x3000 |
| 269 | #define SPK_PG_SLEW_I_SHIFT 12 |
| 270 | |
| 271 | #define SPK_NG_SLEW_DLY_OFFSET CON5_OFFSET |
| 272 | #define SPK_NG_SLEW_DLY_MASK 0x0007 |
| 273 | #define SPK_NG_SLEW_DLY_SHIFT 0 |
| 274 | |
| 275 | #define SPK_PG_SLEW_DLY_OFFSET CON5_OFFSET |
| 276 | #define SPK_PG_SLEW_DLY_MASK 0x0700 |
| 277 | #define SPK_PG_SLEW_DLY_SHIFT 8 |
| 278 | |
| 279 | #define SPK_AB_OBIAS_OFFSET CON7_OFFSET |
| 280 | #define SPK_AB_OBIAS_MASK 0x0030 |
| 281 | #define SPK_AB_OBIAS_SHIFT 4 |
| 282 | |
| 283 | #define SPK_MODE_OFFSET CON7_OFFSET |
| 284 | #define SPK_MODE_MASK 0x0001 |
| 285 | #define SPK_MODE_SHIFT 0 |
| 286 | |
| 287 | #define SPK_AB_OC_EN_OFFSET CON7_OFFSET |
| 288 | #define SPK_AB_OC_EN_MASK 0x0100 |
| 289 | #define SPK_AB_OC_EN_SHIFT 8 |
| 290 | |
| 291 | //ISINK |
| 292 | #define ISINK_EN_OFFSET CON0_OFFSET |
| 293 | #define ISINK_EN_MASK 0x0001 |
| 294 | #define ISINK_EN_SHIFT 0 |
| 295 | |
| 296 | #define ISINK_MODE_OFFSET CON0_OFFSET |
| 297 | #define ISINK_MODE_MASK 0x0002 |
| 298 | #define ISINK_MODE_SHIFT 1 |
| 299 | |
| 300 | #define ISINK_STEP_OFFSET CON0_OFFSET |
| 301 | #define ISINK_STEP_MASK 0x01F0 |
| 302 | #define ISINK_STEP_SHIFT 4 |
| 303 | |
| 304 | #define ISINK_VREF_CAL_OFFSET CON1_OFFSET |
| 305 | #define ISINK_VREF_CAL_MASK 0x1F00 |
| 306 | #define ISINK_VREF_CAL_SHIFT 8 |
| 307 | |
| 308 | |
| 309 | //BOOST |
| 310 | #define BOOST_TYPE_OFFSET CON0_OFFSET |
| 311 | #define BOOST_TYPE_MASK 0x0002 |
| 312 | #define BOOST_TYPE_SHIFT 1 |
| 313 | |
| 314 | #define BOOST_HW_SEL_OFFSET CON6_OFFSET |
| 315 | #define BOOST_HW_SEL_MASK 0x0001 |
| 316 | #define BOOST_HW_SEL_SHIFT 0 |
| 317 | |
| 318 | |
| 319 | //KPLED |
| 320 | #define KPLED_EN_OFFSET CON0_OFFSET |
| 321 | #define KPLED_EN_MASK 0x0001 |
| 322 | #define KPLED_EN_SHIFT 0 |
| 323 | |
| 324 | #define KPLED_MODE_OFFSET CON0_OFFSET |
| 325 | #define KPLED_MODE_MASK 0x0002 |
| 326 | #define KPLED_MODE_SHIFT 1 |
| 327 | |
| 328 | #define KPLED_SEL_OFFSET CON0_OFFSET |
| 329 | #define KPLED_SEL_MASK 0x0070 |
| 330 | #define KPLED_SEL_SHIFT 4 |
| 331 | |
| 332 | |
| 333 | //CHR |
| 334 | #define CSDAC_EN_OFFSET CON0_OFFSET |
| 335 | #define CSDAC_EN_MASK 0x0800 |
| 336 | #define CSDAC_EN_SHIFT 11 |
| 337 | |
| 338 | #define CHR_EN_OFFSET CON0_OFFSET |
| 339 | #define CHR_EN_MASK 0x1000 |
| 340 | #define CHR_EN_SHIFT 12 |
| 341 | |
| 342 | #define CHRDET_OFFSET CON0_OFFSET |
| 343 | #define CHRDET_MASK 0x2000 |
| 344 | #define CHRDET_SHIFT 13 |
| 345 | |
| 346 | #define VCDT_HV_VTH_OFFSET CON0_OFFSET |
| 347 | #define VCDT_HV_VTH_MASK 0x00F0 |
| 348 | #define VCDT_HV_VTH_SHIFT 4 |
| 349 | |
| 350 | #define VCDT_HV_EN_OFFSET CON0_OFFSET |
| 351 | #define VCDT_HV_EN_MASK 0x0100 |
| 352 | #define VCDT_HV_EN_SHIFT 8 |
| 353 | |
| 354 | #define VBAT_CV_VTH_OFFSET CON1_OFFSET |
| 355 | #define VBAT_CV_VTH_MASK 0x001F |
| 356 | #define VBAT_CV_VTH_SHIFT 0 |
| 357 | |
| 358 | #define VBAT_CV_EN_OFFSET CON1_OFFSET |
| 359 | #define VBAT_CV_EN_MASK 0x0100 |
| 360 | #define VBAT_CV_EN_SHIFT 8 |
| 361 | |
| 362 | #define VBAT_CV_DET_OFFSET CON1_OFFSET |
| 363 | #define VBAT_CV_DET_MASK 0x4000 |
| 364 | #define VBAT_CV_DET_SHIFT 14 |
| 365 | |
| 366 | #define CS_VTH_OFFSET CON2_OFFSET |
| 367 | #define CS_VTH_MASK 0x0700 |
| 368 | #define CS_VTH_SHIFT 8 |
| 369 | |
| 370 | #define BATON_HT_EN_OFFSET CON3_OFFSET |
| 371 | #define BATON_HT_EN_MASK 0x0400 |
| 372 | #define BATON_HT_EN_SHIFT 10 |
| 373 | |
| 374 | #define CSDAC_DLY_OFFSET CON3_OFFSET |
| 375 | #define CSDAC_DLY_MASK 0x0030 |
| 376 | #define CSDAC_DLY_SHIFT 4 |
| 377 | |
| 378 | #define CSDAC_STP_OFFSET CON3_OFFSET |
| 379 | #define CSDAC_STP_MASK 0x0003 |
| 380 | #define CSDAC_STP_SHIFT 0 |
| 381 | |
| 382 | #define BATON_UNDET_OFFSET CON3_OFFSET |
| 383 | #define BATON_UNDET_MASK 0x8000 |
| 384 | #define BATON_UNDET_SHIFT 15 |
| 385 | |
| 386 | #define OTG_BVALID_EN_OFFSET CON5_OFFSET |
| 387 | #define OTG_BVALID_EN_MASK 0x1000 |
| 388 | #define OTG_BVALID_EN_SHIFT 12 |
| 389 | |
| 390 | #define CHRWDT_EN_OFFSET CON6_OFFSET |
| 391 | #define CHRWDT_EN_MASK 0x0010 |
| 392 | #define CHRWDT_EN_SHIFT 4 |
| 393 | |
| 394 | #define CHRWDT_TD_OFFSET CON6_OFFSET |
| 395 | #define CHRWDT_TD_MASK 0x000F // TTTTTTTTT |
| 396 | #define CHRWDT_TD_SHIFT 0 |
| 397 | |
| 398 | #define CHRWDT_OUT_OFFSET CON7_OFFSET |
| 399 | #define CHRWDT_OUT_MASK 0x8000 |
| 400 | #define CHRWDT_OTU_SHIFT 15 |
| 401 | |
| 402 | #define CHRWDT_INT_EN_OFFSET CON7_OFFSET |
| 403 | #define CHRWDT_INT_EN_MASK 0x0001 |
| 404 | #define CHRWDT_INT_EN_SHIFT 0 |
| 405 | |
| 406 | #define CHRWDT_FLAG_WR_OFFSET CON7_OFFSET |
| 407 | #define CHRWDT_FLAG_WR_MASK 0x0002 |
| 408 | #define CHRWDT_FLAG_WR_SHIFT 1 |
| 409 | |
| 410 | #define ADC_EN_OFFSET CON8_OFFSET |
| 411 | #define ADC_EN_MASK 0x7000 // All ADC channels are enabled at same time |
| 412 | #define ADC_EN_SHIFT 12 |
| 413 | |
| 414 | #define BC11_VREF_VTH_OFFSET CON9_OFFSET |
| 415 | #define BC11_VREF_VTH_MASK 0x0001 |
| 416 | #define BC11_VREF_VTH_SHIFT 0 |
| 417 | |
| 418 | #define BC11_CMP_EN_OFFSET CON9_OFFSET |
| 419 | #define BC11_CMP_EN_MASK 0x0006 |
| 420 | #define BC11_CMP_EN_SHIFT 1 |
| 421 | |
| 422 | #define BC11_IPD_EN_OFFSET CON9_OFFSET |
| 423 | #define BC11_IPD_EN_MASK 0x0018 |
| 424 | #define BC11_IPD_EN_SHIFT 3 |
| 425 | |
| 426 | #define BC11_IPU_EN_OFFSET CON9_OFFSET |
| 427 | #define BC11_IPU_EN_MASK 0x0060 |
| 428 | #define BC11_IPU_EN_SHIFT 5 |
| 429 | |
| 430 | #define BC11_BIAS_EN_OFFSET CON9_OFFSET |
| 431 | #define BC11_BIAS_EN_MASK 0x0080 |
| 432 | #define BC11_BIAS_EN_SHIFT 7 |
| 433 | |
| 434 | #define BC11_BB_CTRL_OFFSET CON9_OFFSET |
| 435 | #define BC11_BB_CTRL_MASK 0x0100 |
| 436 | #define BC11_BB_CTRL_SHIFT 8 |
| 437 | |
| 438 | #define BC11_RST_OFFSET CON9_OFFSET |
| 439 | #define BC11_RST_MASK 0x0200 |
| 440 | #define BC11_RST_SHIFT 9 |
| 441 | |
| 442 | #define BC11_VSRC_EN_OFFSET CON9_OFFSET |
| 443 | #define BC11_VSRC_EN_MASK 0x0C00 |
| 444 | #define BC11_VSRC_EN_SHIFT 10 |
| 445 | |
| 446 | #define BC11_CMP_OUT_OFFSET CON9_OFFSET |
| 447 | #define BC11_CMP_OUT_MASK 0x8000 |
| 448 | #define BC11_CMP_OUT_SHIFT 15 |
| 449 | |
| 450 | |
| 451 | // STRUP |
| 452 | // STRUP_XXX CON0 |
| 453 | #define USBDL_EN_OFFSET CON0_OFFSET |
| 454 | #define USBDL_EN_MASK 0x0010 |
| 455 | #define USBDL_EN_SHIFT 4 |
| 456 | |
| 457 | // BOOST |
| 458 | #define BOOST_CKS_PRG_OFFSET CON3_OFFSET |
| 459 | #define BOOST_CKS_PRG_MASK 0x003F |
| 460 | #define BOOST_CKS_PRG_SHIFT 0 |
| 461 | |
| 462 | //MISC |
| 463 | #define CCI_SRCLKEN_OFFSET CON2_OFFSET |
| 464 | #define CCI_SRCLKEN_MASK 0x0002 |
| 465 | #define CCI_SRCLKEN_SHIFT 1 |
| 466 | |
| 467 | #endif // #if defined(PMIC_6251_REG_API) |
| 468 | |
| 469 | #endif // #ifndef __PMU6251_HW_H__ |