| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | |
| 2 | |
| 3 | #ifndef __DCL_PMU_COMMON_HW_STRUCT__ |
| 4 | #define __DCL_PMU_COMMON_HW_STRUCT__ |
| 5 | |
| 6 | #define CON0_OFFSET 0x00 |
| 7 | #define CON1_OFFSET 0x04 |
| 8 | #define CON2_OFFSET 0x08 |
| 9 | #define CON3_OFFSET 0x0C |
| 10 | #define CON4_OFFSET 0x10 |
| 11 | #define CON5_OFFSET 0x14 |
| 12 | #define CON6_OFFSET 0x18 |
| 13 | #define CON7_OFFSET 0x1C |
| 14 | #define CON8_OFFSET 0x20 |
| 15 | #define CON9_OFFSET 0x24 |
| 16 | |
| 17 | #if defined(__DRV_UPMU_VPA_V1__) |
| 18 | |
| 19 | //VPA CON0 |
| 20 | #define VPA_EN_OFFSET CON0_OFFSET |
| 21 | #define VPA_EN_MASK 0x1000 |
| 22 | #define VPA_EN_SHIFT 12 |
| 23 | |
| 24 | #define VPA_ANTI_RING_OFFSET CON0_OFFSET |
| 25 | #define VPA_ANTI_RING_MASK 0x0800 |
| 26 | #define VPA_ANTI_RING_SHIFT 11 |
| 27 | |
| 28 | #define VPA_RC_OFFSET CON0_OFFSET |
| 29 | #define VPA_RC_MASK 0x000c |
| 30 | #define VPA_RC_SHIFT 2 |
| 31 | |
| 32 | |
| 33 | //VPA CON2 |
| 34 | #define VPA_VOTUNE0_OFFSET CON2_OFFSET |
| 35 | #define VPA_VOTUNE0_MASK 0x001F |
| 36 | #define VPA_VOTUNE0_SHIFT 0 |
| 37 | |
| 38 | #define VPA_VOTUNE1_OFFSET CON2_OFFSET |
| 39 | #define VPA_VOTUNE1_MASK 0x1F00 |
| 40 | #define VPA_VOTUNE1_SHIFT 8 |
| 41 | |
| 42 | //VPA CON3 |
| 43 | #define VPA_VOTUNE2_OFFSET CON3_OFFSET |
| 44 | #define VPA_VOTUNE2_MASK 0x001F |
| 45 | #define VPA_VOTUNE2_SHIFT 0 |
| 46 | |
| 47 | #define VPA_VOTUNE3_OFFSET CON3_OFFSET |
| 48 | #define VPA_VOTUNE3_MASK 0x1F00 |
| 49 | #define VPA_VOTUNE3_SHIFT 8 |
| 50 | |
| 51 | //VPA CON4 |
| 52 | #define VPA_VOTUNE4_OFFSET CON4_OFFSET |
| 53 | #define VPA_VOTUNE4_MASK 0x001F |
| 54 | #define VPA_VOTUNE4_SHIFT 0 |
| 55 | |
| 56 | #define VPA_VOTUNE5_OFFSET CON4_OFFSET |
| 57 | #define VPA_VOTUNE5_MASK 0x1F00 |
| 58 | #define VPA_VOTUNE5_SHIFT 8 |
| 59 | |
| 60 | //VPA CON5 |
| 61 | #define VPA_VOTUNE6_OFFSET CON5_OFFSET |
| 62 | #define VPA_VOTUNE6_MASK 0x001F |
| 63 | #define VPA_VOTUNE6_SHIFT 0 |
| 64 | |
| 65 | #define VPA_VOTUNE7_OFFSET CON5_OFFSET |
| 66 | #define VPA_VOTUNE7_MASK 0x1F00 |
| 67 | #define VPA_VOTUNE7_SHIFT 8 |
| 68 | |
| 69 | #endif //#if defined(__DRV_UPMU_VPA_V1__) |
| 70 | |
| 71 | #if defined(__DRV_UPMU_LPOSC_V1__) |
| 72 | #define LPOSC_CON0_OFFSET 0x00 |
| 73 | #define LPOSC_CON1_OFFSET 0x04 |
| 74 | #define LPOSC_CON2_OFFSET 0x08 |
| 75 | #define LPOSC_CON3_OFFSET 0x0C |
| 76 | #define LPOSC_CON4_OFFSET 0x10 |
| 77 | |
| 78 | // LPOSC CON0 |
| 79 | #define LPOSC_EN_MASK 0x1000 |
| 80 | #define LPOSC_EN_SHIFT 12 |
| 81 | |
| 82 | //LPOSC CON1 |
| 83 | #define LPOSC_FREQ_SET_MASK 0x00ff |
| 84 | #define LPOSC_FREQ_SET_SHIFT 0 |
| 85 | |
| 86 | #define LPOSC_BUCK_FREQ_SET_MASK 0x0700 |
| 87 | #define LPOSC_BUCK_FREQ_SET_SHIFT 8 |
| 88 | |
| 89 | #define LPOSC_ACALI_EN_MASK 0x4000 |
| 90 | #define LPOSC_ACALI_EN_SHIFT 14 |
| 91 | |
| 92 | #define LPOSC_FREQ_SET_MASK 0x00ff |
| 93 | #define LPOSC_FREQ_SET_SHIFT 0 |
| 94 | |
| 95 | // LPOSC CON2 |
| 96 | #define LPOSC_FD_RES_MASK 0x0007 |
| 97 | #define LPOSC_FD_RES_SHIFT 0 |
| 98 | |
| 99 | #define LPOSC_SSC_EN_MASK 0x0008 |
| 100 | #define LPOSC_SSC_EN_SHIFT 3 |
| 101 | |
| 102 | #define LPOSC_SSC_MOD_AMP_MASK 0x0700 |
| 103 | #define LPOSC_SSC_MOD_AMP_SHIFT 8 |
| 104 | |
| 105 | #define LPOSC_RG_BUCK_BOOST_EN_MASK 0x0800 |
| 106 | #define LPOSC_RG_BUCK_BOOST_EN_SHIFT 11 |
| 107 | |
| 108 | #define LPOSC_SSC_CODE_DUR_MASK 0x7000 |
| 109 | #define LPOSC_SSC_CODE_DUR_SHIFT 12 |
| 110 | |
| 111 | #define LPOSC_LPOSC_PG_EN_MASK 0x8000 |
| 112 | #define LPOSC_LPOSC_PG_EN_SHIFT 15 |
| 113 | |
| 114 | //LPOSC CON4 |
| 115 | #define LPOSC_SW_MODE_EN_MASK 0x1000 |
| 116 | #define LPOSC_SW_MODE_EN_SHIFT 12 |
| 117 | |
| 118 | #endif //#if defined(__DRV_UPMU_BUCK_V1__) |
| 119 | |
| 120 | #if defined(__DRV_UPMU_LDO_V1__) |
| 121 | #define LDO_CON0_OFFSET 0x00 |
| 122 | #define LDO_CON1_OFFSET 0x04 |
| 123 | #define LDO_CON2_OFFSET 0x08 |
| 124 | #define LDO_CON3_OFFSET 0x0C |
| 125 | // LDO H/W register bitmap definition |
| 126 | // LDO_XXX CON0 |
| 127 | #define LDO_EN_OFFSET CON0_OFFSET |
| 128 | #define LDO_EN_MASK 0x0001 |
| 129 | #define LDO_EN_SHIFT 0 |
| 130 | |
| 131 | #define LDO_ON_SEL_OFFSET CON0_OFFSET |
| 132 | #define LDO_ON_SEL_MASK 0x0002 |
| 133 | #define LDO_ON_SEL_SHIFT 1 |
| 134 | |
| 135 | #define LDO_RS_MASK 0x0004 |
| 136 | #define LDO_RS_SHIFT 2 |
| 137 | |
| 138 | #define LDO_VOL_SEL_OFFSET CON0_OFFSET |
| 139 | #define LDO_VOL_SEL_MASK 0x01F0 |
| 140 | #define LDO_VOL_SEL_SHIFT 4 |
| 141 | |
| 142 | #define LDO_NDIS_EN_OFFSET CON0_OFFSET |
| 143 | #define LDO_NDIS_EN_MASK 0x0400 |
| 144 | #define LDO_NDIS_EN_SHIFT 10 |
| 145 | |
| 146 | #define LDO_STB_EN_OFFSET CON0_OFFSET |
| 147 | #define LDO_STB_EN_MASK 0x0800 |
| 148 | #define LDO_STB_EN_SHIFT 11 |
| 149 | |
| 150 | #define LDO_OC_AUTO_OFF_OFFSET CON0_OFFSET |
| 151 | #define LDO_OC_AUTO_OFF_MASK 0x1000 |
| 152 | #define LDO_OC_AUTO_OFF_SHIFT 12 |
| 153 | |
| 154 | #define LDO_OCFB_EN_OFFSET CON0_OFFSET |
| 155 | #define LDO_OCFB_EN_MASK 0x2000 |
| 156 | #define LDO_OCFB_EN_SHIFT 13 |
| 157 | |
| 158 | #define LDO_OC_STATUS_MASK 0x4000 |
| 159 | #define LDO_OC_STATUS_SHIFT 14 |
| 160 | |
| 161 | #define LDO_STATUS_MASK 0x8000 |
| 162 | #define LDO_STATUS_SHIFT 15 |
| 163 | |
| 164 | // LDO_XXX CON1 |
| 165 | #if defined(__DRV_UPMU_LDO_V1_STB_TD_AT_CON1_BIT0__) |
| 166 | #define LDO_STB_TD_OFFSET CON1_OFFSET |
| 167 | #define LDO_STB_TD_MASK 0x0003 |
| 168 | #define LDO_STB_TD_SHIFT 0 |
| 169 | #else |
| 170 | #define LDO_STB_TD_OFFSET CON2_OFFSET |
| 171 | #define LDO_STB_TD_MASK 0x00c0 |
| 172 | #define LDO_STB_TD_SHIFT 6 |
| 173 | #endif // #if defined(__DRV_UPMU_LDO_V1_STB_TD_AT_CON1_BIT0__) |
| 174 | |
| 175 | #define LDO_FORCE_LOW_MASK 0x0004 |
| 176 | #define LDO_FORCE_LOW_SHIFT 2 |
| 177 | |
| 178 | #define LDO_CAL_OFFSET CON1_OFFSET |
| 179 | #define LDO_CAL_MASK 0x01F0 |
| 180 | #define LDO_CAL_SHIFT 4 |
| 181 | #if defined(__DRV_UPMU_LDO_CAL_AS_SLEEP_VOLTAGE__) |
| 182 | #define LDO_VOL_SEL_SLEEP_MASK 0x01F0 |
| 183 | #define LDO_VOL_SEL_SLEEP_SHIFT 4 |
| 184 | #endif // #if defined(__DRV_UPMU_LDO_CAL_AS_SLEEP_VOLTAGE__) |
| 185 | |
| 186 | // LDO_XXX CON2 |
| 187 | #define LDO_GP_LDOEN_MASK 0x0002 |
| 188 | #define LDO_GP_LDOEN_SHIFT 1 |
| 189 | |
| 190 | #define LDO_OC_TD_OFFSET CON2_OFFSET |
| 191 | #define LDO_OC_TD_MASK 0x0030 |
| 192 | #define LDO_OC_TD_SHIFT 4 |
| 193 | /* |
| 194 | #if defined(__DRV_UPMU_LDO_V1_STB_TD_AT_CON2_BIT6__) |
| 195 | #define LDO_STB_TD_OFFSET CON2_OFFSET |
| 196 | #define LDO_STB_TD_MASK 0x00C0 |
| 197 | #define LDO_STB_TD_SHIFT 6 |
| 198 | #endif // #if defined(__DRV_UPMU_LDO_V1_STB_TD_AT_CON2_BIT6__) |
| 199 | */ |
| 200 | |
| 201 | #define LDO_ICAL_EN_MASK 0x3000 |
| 202 | #define LDO_ICAL_EN_SHIFT 12 |
| 203 | |
| 204 | // LDO_XXX CON3 |
| 205 | // Only for VSIM/VSIM2 LDO |
| 206 | #define SIMIO_DRV_MASK 0x000E |
| 207 | #define SIMIO_DRV_SHIFT 1 |
| 208 | #define SIM_BIAS_MASK 0x0030 |
| 209 | #define SIM_BIAS_SHIFT 4 |
| 210 | #define SIM_SRN_MASK 0x00C0 |
| 211 | #define SIM_SRN_SHIFT 6 |
| 212 | #define SIM_SRP_MASK 0x0300 |
| 213 | #define SIM_SRP_SHIFT 8 |
| 214 | #define SIM_CSTOP_MASK 0x0400 // Only for 6256 E2 |
| 215 | #define SIM_CSTOP_SHIFT 10 // Only for 6256 E2 |
| 216 | |
| 217 | //////////////////// SIM control |
| 218 | #if defined(__DRV_UPMU_LDO_SIM_SPECIFIC_CONFIG_FIELD_AT_CON2__) |
| 219 | #define LDO_SIM_GPIO_EN_OFFSET CON2_OFFSET |
| 220 | #define LDO_SIM_SIMIO_DRV_OFFSET CON2_OFFSET |
| 221 | #define LDO_SIM_BIAS_OFFSET CON2_OFFSET |
| 222 | #define LDO_SIM_SRN_OFFSET CON2_OFFSET |
| 223 | #define LDO_SIM_SRP_OFFSET CON2_OFFSET |
| 224 | #else |
| 225 | #define LDO_SIM_GPIO_EN_OFFSET CON3_OFFSET |
| 226 | #define LDO_SIM_SIMIO_DRV_OFFSET CON3_OFFSET |
| 227 | #define LDO_SIM_BIAS_OFFSET CON3_OFFSET |
| 228 | #define LDO_SIM_SRN_OFFSET CON3_OFFSET |
| 229 | #define LDO_SIM_SRP_OFFSET CON3_OFFSET |
| 230 | #define LDO_SIM_CSTOP_OFFSET CON3_OFFSET // Only for 6256 E2 |
| 231 | #endif //#if defined(__DRV_UPMU_LDO_SIM_SPECIFIC_CONFIG_FIELD_AT_CON2__) |
| 232 | #define LDO_SIM_GPIO_EN_MASK 0x0001 |
| 233 | #define LDO_SIM_GPIO_EN_SHIFT 0 |
| 234 | |
| 235 | #define LDO_SIM_SIMIO_DRV_MASK 0x000E |
| 236 | #define LDO_SIM_SIMIO_DRV_SHIFT 1 |
| 237 | |
| 238 | #define LDO_SIM_BIAS_MASK 0x0030 |
| 239 | #define LDO_SIM_BIAS_SHIFT 4 |
| 240 | |
| 241 | #define LDO_SIM_SRN_MASK 0x00C0 |
| 242 | #define LDO_SIM_SRN_SHIFT 6 |
| 243 | |
| 244 | #define LDO_SIM_SRP_MASK 0x0300 |
| 245 | #define LDO_SIM_SRP_SHIFT 8 |
| 246 | |
| 247 | #define LDO_SIM_CSTOP_MASK 0x0400 // Only for 6256 E2 |
| 248 | #define LDO_SIM_CSTOP_SHIFT 10 // Only for 6256 E2 |
| 249 | ///////////////////// SIM control end |
| 250 | |
| 251 | |
| 252 | #endif // #if defined(__DRV_UPMU_LDO_V1__) |
| 253 | |
| 254 | #if defined(__DRV_UPMU_BUCK_V1__) |
| 255 | #define BUCK_CON0_OFFSET 0x00 |
| 256 | #define BUCK_CON1_OFFSET 0x04 |
| 257 | #define BUCK_CON2_OFFSET 0x08 |
| 258 | #define BUCK_CON3_OFFSET 0x0C |
| 259 | #define BUCK_CON4_OFFSET 0x10 |
| 260 | #define BUCK_CON5_OFFSET 0x14 |
| 261 | #define BUCK_CON6_OFFSET 0x18 |
| 262 | // BUCK H/W register bitmap definition |
| 263 | // BUCK_XXX CON0 |
| 264 | #define BUCK_EN_OFFSET CON0_OFFSET |
| 265 | #define BUCK_EN_MASK 0x0001 |
| 266 | #define BUCK_EN_SHIFT 0 |
| 267 | |
| 268 | #define BUCK_ON_SEL_OFFSET CON0_OFFSET |
| 269 | #define BUCK_ON_SEL_MASK 0x0002 |
| 270 | #define BUCK_ON_SEL_SHIFT 1 |
| 271 | |
| 272 | #define BUCK_RS_OFFSET CON0_OFFSET |
| 273 | #define BUCK_RS_MASK 0x0004 |
| 274 | #define BUCK_RS_SHIFT 2 |
| 275 | |
| 276 | #define BUCK_ST_STR_MASK 0x0008 |
| 277 | #define BUCK_ST_STR_SHIFT 3 |
| 278 | |
| 279 | #define BUCK_VFBADJ_OFFSET CON0_OFFSET |
| 280 | #define BUCK_VFBADJ_MASK 0x01F0 |
| 281 | #define BUCK_VFBADJ_SHIFT 4 |
| 282 | |
| 283 | #define BUCK_DIS_ANTIUNSH_MASK 0x0400 |
| 284 | #define BUCK_DIS_ANTIUNSH_SHIFT 10 |
| 285 | |
| 286 | #define BUCK_STB_EN_MASK 0x0800 |
| 287 | #define BUCK_STB_EN_SHIFT 11 |
| 288 | |
| 289 | #define BUCK_OC_AUTO_OFF_MASK 0x1000 |
| 290 | #define BUCK_OC_AUTO_OFF_SHIFT 12 |
| 291 | |
| 292 | #define BUCK_OCFB_EN_OFFSET CON0_OFFSET |
| 293 | #define BUCK_OCFB_EN_MASK 0x2000 |
| 294 | #define BUCK_OCFB_EN_SHIFT 13 |
| 295 | |
| 296 | // BUCK_XXX CON1 |
| 297 | #define BUCK_MODESET_MASK 0x0001 |
| 298 | #define BUCK_MODESET_SHIFT 0 |
| 299 | |
| 300 | #define BUCK_VFBADJ_SLEEP_OFFSET CON1_OFFSET |
| 301 | #define BUCK_VFBADJ_SLEEP_MASK 0x01F0 |
| 302 | #define BUCK_VFBADJ_SLEEP_SHIFT 4 |
| 303 | |
| 304 | #define BUCK_CLK_SRC_MASK 0x0400 |
| 305 | #define BUCK_CLK_SRC_SHIFT 10 |
| 306 | |
| 307 | // BUCK_XXX CON2 |
| 308 | #define BUCK_CAL_MASK 0x01F0 |
| 309 | #define BUCK_CAL_SHIFT 4 |
| 310 | |
| 311 | // BUCK_XXX CON3 |
| 312 | #define BUCK_OC_TD_OFFSET CON3_OFFSET |
| 313 | #define BUCK_OC_TD_MASK 0x0030 |
| 314 | #define BUCK_OC_TD_SHIFT 4 |
| 315 | |
| 316 | #define BUCK_STB_TD_OFFSET CON3_OFFSET |
| 317 | #define BUCK_STB_TD_MASK 0x00C0 |
| 318 | #define BUCK_STB_TD_SHIFT 6 |
| 319 | |
| 320 | #define BUCK_OC_THD_MASK 0x0300 |
| 321 | #define BUCK_OC_THD_SHIFT 8 |
| 322 | |
| 323 | #define BUCK_OC_WND_MASK 0x0C00 |
| 324 | #define BUCK_OC_WND_SHIFT 10 |
| 325 | |
| 326 | #define BUCK_ICAL_EN_OFFSET CON3_OFFSET |
| 327 | #define BUCK_ICAL_EN_MASK 0x3000 |
| 328 | #define BUCK_ICAL_EN_SHIFT 12 |
| 329 | |
| 330 | // BUCK XXX CON4 |
| 331 | #define BUCK_ADJCKSEL_OFFSET CON4_OFFSET |
| 332 | #define BUCK_ADJCKSEL_MASK 0x0070 |
| 333 | #define BULK_ADJCKSEL_SHIFT 4 |
| 334 | |
| 335 | // BUCK XXX CON5 |
| 336 | #define BUCK_CSR_OFFSET CON5_OFFSET |
| 337 | #define BUCK_CSR_MASK 0x000F |
| 338 | #define BULK_CSR_SHIFT 0 |
| 339 | |
| 340 | #define BUCK_RZSEL_OFFSET CON5_OFFSET |
| 341 | #define BUCK_RZSEL_MASK 0x0070 |
| 342 | #define BULK_RZSEL_SHIFT 4 |
| 343 | |
| 344 | #define BUCK_CSL_OFFSET CON5_OFFSET |
| 345 | #define BUCK_CSL_MASK 0x0700 |
| 346 | #define BUCK_CSL_SHIFT 8 |
| 347 | |
| 348 | #define BUCK_BURST_OFFSET CON5_OFFSET |
| 349 | #define BUCK_BURST_MASK 0x3000 |
| 350 | #define BUCK_BURST_SHIFT 12 |
| 351 | |
| 352 | #define BUCK_GMSEL_OFFSET CON5_OFFSET |
| 353 | #define BUCK_GMSEL_MASK 0x4000 |
| 354 | #define BUCK_GMSEL_SHIFT 14 |
| 355 | |
| 356 | #define BUCK_ZX_PDN_OFFSET CON5_OFFSET |
| 357 | #define BUCK_ZX_PDN_MASK 0x8000 |
| 358 | #define BUCK_ZX_PDN_SHIFT 15 |
| 359 | |
| 360 | // BUCK XXX CON6 |
| 361 | #define BUCK_CKS_PRG_OFFSET CON6_OFFSET |
| 362 | #define BUCK_CKS_PRG_MASK 0x001f |
| 363 | #define BUCK_CKS_PRG_SHIFT 0 |
| 364 | |
| 365 | |
| 366 | #endif // #if defined(__DRV_UPMU_BUCK_V1__) |
| 367 | |
| 368 | #if defined(__DRV_UPMU_BOOST_V1__) |
| 369 | #define BOOST_CON0_OFFSET 0x00 |
| 370 | #define BOOST_CON1_OFFSET 0x04 |
| 371 | #define BOOST_CON2_OFFSET 0x08 |
| 372 | #define BOOST_CON3_OFFSET 0x0C |
| 373 | #define BOOST_CON4_OFFSET 0x10 |
| 374 | #define BOOST_CON5_OFFSET 0x14 |
| 375 | #define BOOST_CON6_OFFSET 0x18 |
| 376 | // BOOST H/W register bitmap definition |
| 377 | // BOOST_XXX CON0 |
| 378 | #define BOOST_EN_OFFSET CON0_OFFSET |
| 379 | #define BOOST_EN_MASK 0x0001 |
| 380 | #define BOOST_EN_SHIFT 0 |
| 381 | |
| 382 | #define BOOST_TYPE_MASK 0x0002 |
| 383 | #define BOOST_TYPE_SHIFT 1 |
| 384 | |
| 385 | #define BOOST_MODE_MASK 0x0004 |
| 386 | #define BOOST_MODE_SHIFT 2 |
| 387 | |
| 388 | #define BOOST_VRSEL_MASK 0x01F0 |
| 389 | #define BOOST_VRSEL_SHIFT 4 |
| 390 | |
| 391 | #define BOOST_OC_AUTO_OFF_MASK 0x1000 |
| 392 | #define BOOST_OC_AUTO_OFF_SHIFT 12 |
| 393 | |
| 394 | #define BOOST_OC_FLAG_MASK 0x4000 |
| 395 | #define BOOST_OC_FLAG_SHIFT 14 |
| 396 | |
| 397 | // BOOST_XXX CON1 |
| 398 | #define BOOST_CL_OFFSET CON1_OFFSET |
| 399 | #define BOOST_CL_MASK 0x0007 |
| 400 | #define BOOST_CL_SHIFT 0 |
| 401 | |
| 402 | #define BOOST_CS_MASK 0x0070 |
| 403 | #define BOOST_CS_SHIFT 4 |
| 404 | |
| 405 | #define BOOST_RC_MASK 0x0700 |
| 406 | #define BOOST_RC_SHIFT 8 |
| 407 | |
| 408 | #define BOOST_SS_MASK 0x7000 |
| 409 | #define BOOST_SS_SHIFT 12 |
| 410 | |
| 411 | // BOOST_XXX CON2 |
| 412 | #define BOOST_CKSEL_MASK 0x0002 |
| 413 | #define BOOST_CKSEL_SHIFT 1 |
| 414 | |
| 415 | #define BOOST_SR_PMOS_MASK 0x0070 |
| 416 | #define BOOST_SR_PMOS_SHIFT 4 |
| 417 | |
| 418 | #define BOOST_SR_NMOS_MASK 0x0700 |
| 419 | #define BOOST_SR_NMOS_SHIFT 8 |
| 420 | |
| 421 | #define BOOST_SLP_MASK 0xC000 |
| 422 | #define BOOST_SLP_SHIFT 14 |
| 423 | |
| 424 | // BOOST_XXX CON3 |
| 425 | #define BOOST_CKS_PRG_MASK 0x003F |
| 426 | #define BOOST_CKS_PRG_SHIFT 0 |
| 427 | |
| 428 | // BOOST_XXX CON4 |
| 429 | #define BOOST_OC_THD_MASK 0x0030 |
| 430 | #define BOOST_OC_THD_SHIFT 4 |
| 431 | |
| 432 | #define BOOST_OC_WND_MASK 0x00C0 |
| 433 | #define BOOST_OC_WND_SHIFT 6 |
| 434 | |
| 435 | #define BOOST_CLK_CAL_OFFSET CON4_OFFSET |
| 436 | #define BOOST_CLK_CAL_MASK 0x7000 |
| 437 | #define BOOST_CLK_CAL_SHIFT 12 |
| 438 | |
| 439 | // BOOST_XXX CON6 |
| 440 | #define BOOST_HW_SEL_MASK 0x0001 |
| 441 | #define BOOST_HW_SEL_SHIFT 0 |
| 442 | |
| 443 | #define BOOST_CC_MASK 0x0070 |
| 444 | #define BOOST_CC_SHIFT 4 |
| 445 | |
| 446 | #endif // #if defined(__DRV_UPMU_BOOST_V1__) |
| 447 | |
| 448 | |
| 449 | #if defined(__DRV_UPMU_ISINK_V1__) |
| 450 | #define ISINK_CON0_OFFSET 0x00 |
| 451 | #define ISINK_CON1_OFFSET 0x04 |
| 452 | #define ISINK_CON2_OFFSET 0x08 |
| 453 | // iSINK H/W register bitmap definition |
| 454 | // ISINK_XXX CON0 |
| 455 | #define ISINK_EN_OFFSET CON0_OFFSET |
| 456 | #define ISINK_EN_MASK 0x0001 |
| 457 | #define ISINK_EN_SHIFT 0 |
| 458 | |
| 459 | #define ISINK_MODE_OFFSET CON0_OFFSET |
| 460 | #define ISINK_MODE_MASK 0x0002 |
| 461 | #define ISINK_MODE_SHIFT 1 |
| 462 | |
| 463 | #define ISINK_STEP_OFFSET CON0_OFFSET |
| 464 | #define ISINK_STEP_MASK 0x01F0 |
| 465 | #define ISINK_STEP_SHIFT 4 |
| 466 | |
| 467 | #define ISINK_STATUS_MASK 0x8000 |
| 468 | #define ISINK_STATUS_SHIFT 15 |
| 469 | |
| 470 | // ISINK_XXX CON1 |
| 471 | #define ISINK_VREF_CAL_MASK 0x1F00 |
| 472 | #define ISINK_VREF_CAL_SHIFT 8 |
| 473 | |
| 474 | #endif // #if defined(__DRV_UPMU_ISINK_V1__) |
| 475 | |
| 476 | |
| 477 | #if defined(__DRV_UPMU_KPLED_V1__) |
| 478 | #define KPLED_CON0_OFFSET 0x00 |
| 479 | #define KPLED_CON1_OFFSET 0x04 |
| 480 | // KPLED H/W register bitmap definition |
| 481 | // KPLED_XXX CON0 |
| 482 | #define KPLED_EN_OFFSET CON0_OFFSET |
| 483 | #define KPLED_EN_MASK 0x0001 |
| 484 | #define KPLED_EN_SHIFT 0 |
| 485 | |
| 486 | #define KPLED_MODE_OFFSET CON0_OFFSET |
| 487 | #define KPLED_MODE_MASK 0x0002 |
| 488 | #define KPLED_MODE_SHIFT 1 |
| 489 | |
| 490 | #define KPLED_SEL_OFFSET CON0_OFFSET |
| 491 | #define KPLED_SEL_MASK 0x0070 |
| 492 | #define KPLED_SEL_SHIFT 4 |
| 493 | |
| 494 | #define KPLED_SFSTRT_C_OFFSET CON0_OFFSET |
| 495 | #define KPLED_SFSTRT_C_MASK 0x0300 |
| 496 | #define KPLED_SFSTRT_C_SHIFT 8 |
| 497 | |
| 498 | #define KPLED_SFSTRT_EN_OFFSET CON0_OFFSET |
| 499 | #define KPLED_SFSTRT_EN_MASK 0x0400 |
| 500 | #define KPLED_SFSTRT_EN_SHIFT 10 |
| 501 | |
| 502 | #define KPLED_STATUS_OFFSET CON0_OFFSET |
| 503 | #define KPLED_STATUS_MASK 0x8000 |
| 504 | #define KPLED_STATUS_SHIFT 15 |
| 505 | |
| 506 | #endif // #if defined(__DRV_UPMU_KPLED_V1__) |
| 507 | |
| 508 | |
| 509 | #if defined(__DRV_UPMU_SPK_V1__) |
| 510 | #define SPK_CON0_OFFSET 0x00 |
| 511 | #define SPK_CON1_OFFSET 0x04 |
| 512 | #define SPK_CON2_OFFSET 0x08 |
| 513 | #define SPK_CON3_OFFSET 0x0C |
| 514 | #define SPK_CON4_OFFSET 0x10 |
| 515 | #define SPK_CON5_OFFSET 0x14 |
| 516 | #define SPK_CON6_OFFSET 0x18 |
| 517 | #define SPK_CON7_OFFSET 0x1C |
| 518 | // SPK H/W register bitmap definition |
| 519 | // SPK_XXX CON0 |
| 520 | #define SPK_EN_MASK 0x0001 |
| 521 | #define SPK_EN_SHIFT 0 |
| 522 | |
| 523 | #define SPK_RST_MASK 0x0002 |
| 524 | #define SPK_RST_SHIFT 1 |
| 525 | |
| 526 | #define SPK_VOL_OFFSET CON0_OFFSET |
| 527 | #define SPK_VOL_MASK 0x01F0 |
| 528 | #define SPK_VOL_SHIFT 4 |
| 529 | |
| 530 | #define SPK_OC_AUTO_OFF_MASK 0x1000 |
| 531 | #define SPK_OC_AUTO_OFF_SHIFT 12 |
| 532 | |
| 533 | #define SPK_OCFB_EN_MASK 0x2000 |
| 534 | #define SPK_OCFB_EN_SHIFT 13 |
| 535 | |
| 536 | #define SPK_OC_FLAG_MASK 0x4000 |
| 537 | #define SPK_OC_FLAG_SHIFT 14 |
| 538 | |
| 539 | // SPK_XXX CON1 |
| 540 | #define SPK_PFD_MODE_MASK 0x0001 |
| 541 | #define SPK_PFD_MODE_SHIFT 0 |
| 542 | |
| 543 | #define SPK_CMODE_MASK 0x000C |
| 544 | #define SPK_CMODE_SHIFT 2 |
| 545 | |
| 546 | #define SPK_CCODE_MASK 0x00F0 |
| 547 | #define SPK_CCODE_SHIFT 4 |
| 548 | |
| 549 | // SPK_XXX CON2 |
| 550 | #define SPK_OC_THD_MASK 0x0030 |
| 551 | #define SPK_OC_THD_SHIFT 4 |
| 552 | |
| 553 | #define SPK_OC_WND_MASK 0x00C0 |
| 554 | #define SPK_OC_WND_SHIFT 6 |
| 555 | |
| 556 | // SPK_XXX CON3 |
| 557 | #define SPK_OC_EN_OFFSET CON3_OFFSET |
| 558 | #define SPK_OC_EN_MASK 0x0400 |
| 559 | #define SPK_OC_EN_SHIFT 10 |
| 560 | |
| 561 | #define SPK_OSC_ISEL_MASK 0x00C0 |
| 562 | #define SPK_OSC_ISEL_SHIFT 6 |
| 563 | |
| 564 | // SPK_XXX CON4 |
| 565 | #define SPK_NG_DT_DLY_MASK 0x000f |
| 566 | #define SPK_NG_DT_DLY_SHIFT 0 |
| 567 | #define SPK_OCN_BIAS_MASK 0x0700 |
| 568 | #define SPK_OCN_BIAS_SHIFT 8 |
| 569 | #define SPK_OCP_BIAS_MASK 0x7000 |
| 570 | #define SPK_OCP_BIAS_SHIFT 12 |
| 571 | |
| 572 | // SPK_XXX CON5 |
| 573 | #define SPK_NG_SLEW_DLY_MASK 0x0007 |
| 574 | #define SPK_NG_SLEW_DLY_SHIFT 0 |
| 575 | #define SPK_PG_SLEW_DLY_MASK 0x0700 |
| 576 | #define SPK_PG_SLEW_DLY_SHIFT 8 |
| 577 | #define SPK_PG_SLEW_I_MASK 0x3000 |
| 578 | #define SPK_PG_SLEW_I_SHIFT 12 |
| 579 | |
| 580 | |
| 581 | // SPK_XXX CON7 |
| 582 | #define SPK_AB_OBIAS_MASK 0x0030 |
| 583 | #define SPK_AB_OBIAS_SHIFT 4 |
| 584 | #define SPK_AB_OC_EN_MASK 0x0100 |
| 585 | #define SPK_AB_OC_EN_SHIFT 8 |
| 586 | #define SPK_MODE_MASK 0x0001 |
| 587 | #define SPK_MODE_SHIFT 0 |
| 588 | |
| 589 | |
| 590 | #endif // #if defined(__DRV_UPMU_SPK_V1__) |
| 591 | |
| 592 | |
| 593 | #if defined(__DRV_UPMU_SPK_V2__) |
| 594 | #define SPK_CON0_OFFSET 0x00 |
| 595 | #define SPK_CON1_OFFSET 0x04 |
| 596 | // SPK H/W register bitmap definition |
| 597 | // SPK_XXX CON0 |
| 598 | #define SPK_EN_MASK 0x0001 |
| 599 | #define SPK_EN_SHIFT 0 |
| 600 | |
| 601 | #define SPK_VOL_OFFSET CON0_OFFSET |
| 602 | #define SPK_VOL_MASK 0x001E |
| 603 | #define SPK_VOL_SHIFT 1 |
| 604 | |
| 605 | #define SPK_OUT_FLOAT_B_MASK 0x0020 |
| 606 | #define SPK_OUT_FLOAT_B_SHIFT 5 |
| 607 | |
| 608 | #define SPK_OC_EN_OFFSET CON0_OFFSET |
| 609 | #define SPK_OC_EN_MASK 0x0040 |
| 610 | #define SPK_OC_EN_SHIFT 6 |
| 611 | |
| 612 | #define SPK_OBIAS_MASK 0x00C0 |
| 613 | #define SPK_OBIAS_SHIFT 7 |
| 614 | |
| 615 | #define SPK_IN_TIE_HIGH_MASK 0x0400 |
| 616 | #define SPK_IN_TIE_HIGH_SHIFT 10 |
| 617 | |
| 618 | #define SPK_IN_FLOAT_B_MASK 0x0800 |
| 619 | #define SPK_IN_FLOAT_B_SHIFT 11 |
| 620 | |
| 621 | #define SPK_MINUS_GAIN_MASK 0x3000 |
| 622 | #define SPK_MINUS_GAIN_SHIFT 12 |
| 623 | |
| 624 | // SPK_XXX CON1 |
| 625 | #define SPK_OC_THD_MASK 0x0003 // OC_TRG |
| 626 | #define SPK_OC_THD_SHIFT 0 |
| 627 | |
| 628 | #define SPK_OC_WND_MASK 0x000C |
| 629 | #define SPK_OC_WND_SHIFT 2 |
| 630 | |
| 631 | #define SPK_OC_AUTO_OFF_MASK 0x0040 |
| 632 | #define SPK_OC_AUTO_OFF_SHIFT 6 |
| 633 | |
| 634 | #define SPK_OC_FLAG_MASK 0x8000 |
| 635 | #define SPK_OC_FLAG_SHIFT 15 |
| 636 | |
| 637 | #endif // #if defined(__DRV_UPMU_SPK_V2__) |
| 638 | |
| 639 | |
| 640 | #if defined(__DRV_UPMU_CHARGER_V1__) |
| 641 | #define CHR_CON0_OFFSET 0x00 |
| 642 | #define CHR_CON1_OFFSET 0x04 |
| 643 | #define CHR_CON2_OFFSET 0x08 |
| 644 | #define CHR_CON3_OFFSET 0x0C |
| 645 | #define CHR_CON4_OFFSET 0x10 |
| 646 | #define CHR_CON5_OFFSET 0x14 |
| 647 | #define CHR_CON6_OFFSET 0x18 |
| 648 | #define CHR_CON7_OFFSET 0x1C |
| 649 | #define CHR_CON8_OFFSET 0x20 |
| 650 | #define CHR_CON9_OFFSET 0x24 |
| 651 | #define CHR_BC11_CON0_OFFSET CHR_CON9_OFFSET |
| 652 | #define CHR_CON10_OFFSET 0x28 |
| 653 | #define CHR_BC11_CON1_OFFSET CHR_CON10_OFFSET |
| 654 | // CHARGER H/W register bitmap definition |
| 655 | // CHR_XXX CON0 |
| 656 | #define VCDT_LV_VTH_MASK 0x001F |
| 657 | #define VCDT_LV_VTH_SHIFT 0 |
| 658 | #define VCDT_HV_VTH_MASK 0x00F0 |
| 659 | #define VCDT_HV_VTH_SHIFT 4 |
| 660 | #define VCDT_HV_EN_MASK 0x0100 |
| 661 | #define VCDT_HV_EN_SHIFT 8 |
| 662 | #define PCHR_AUTO_MASK 0x0400 |
| 663 | #define PCHR_AUTO_SHIFT 10 |
| 664 | |
| 665 | #define CSDAC_EN_OFFSET CON0_OFFSET |
| 666 | #define CSDAC_EN_MASK 0x0800 |
| 667 | #define CSDAC_EN_SHIFT 11 |
| 668 | |
| 669 | #define CHR_EN_OFFSET CON0_OFFSET |
| 670 | #define CHR_EN_MASK 0x1000 |
| 671 | #define CHR_EN_SHIFT 12 |
| 672 | |
| 673 | #define CHRDET_OFFSET CON0_OFFSET |
| 674 | #define CHRDET_MASK 0x2000 |
| 675 | #define CHRDET_SHIFT 13 |
| 676 | |
| 677 | #define VCDT_LV_DET_MASK 0x4000 |
| 678 | #define VCDT_LV_DET_SHIFT 14 |
| 679 | #define VCDT_HV_DET_MASK 0x8000 |
| 680 | #define VCDT_HV_DET_SHIFT 15 |
| 681 | // CHR_XXX CON1 |
| 682 | #define VBAT_CV_VTH_OFFSET CON1_OFFSET |
| 683 | #define VBAT_CV_VTH_MASK 0x001F |
| 684 | #define VBAT_CV_VTH_SHIFT 0 |
| 685 | |
| 686 | #define VBAT_CC_VTH_MASK 0x00C0 |
| 687 | #define VBAT_CC_VTH_SHIFT 6 |
| 688 | |
| 689 | #define VBAT_CV_EN_OFFSET CON1_OFFSET |
| 690 | #define VBAT_CV_EN_MASK 0x0100 |
| 691 | #define VBAT_CV_EN_SHIFT 8 |
| 692 | |
| 693 | #define VBAT_CC_EN_MASK 0x0200 |
| 694 | #define VBAT_CC_EN_SHIFT 9 |
| 695 | |
| 696 | #define VBAT_CV_DET_OFFSET CON1_OFFSET |
| 697 | #define VBAT_CV_DET_MASK 0x4000 |
| 698 | #define VBAT_CV_DET_SHIFT 14 |
| 699 | |
| 700 | #define VBAT_CC_DET_MASK 0x8000 |
| 701 | #define VBAT_CC_DET_SHIFT 15 |
| 702 | // CHR_XXX CON2 |
| 703 | #define PCHR_TOHTC_MASK 0x0007 |
| 704 | #define PCHR_TOHTC_SHIFT 0 |
| 705 | #define PCHR_TOLTC_MASK 0x0070 |
| 706 | #define PCHR_TOLTC_SHIFT 4 |
| 707 | |
| 708 | #define CS_VTH_OFFSET CON2_OFFSET |
| 709 | #define CS_VTH_MASK 0x0700 |
| 710 | #define CS_VTH_SHIFT 8 |
| 711 | |
| 712 | #define CS_EN_MASK 0x1000 |
| 713 | #define CS_EN_SHIFT 12 |
| 714 | #if defined(__DRV_OTG_BVALID_DET_AT_CON2_BIT14__) |
| 715 | #define OTG_BVALID_DET_MASK 0x4000 |
| 716 | #define OTG_BVALID_DET_SHIFT 14 |
| 717 | #endif // #if defined(__DRV_OTG_BVALID_DET_AT_CON2_BIT14__) |
| 718 | #define CS_DET_MASK 0x8000 |
| 719 | #define CS_DET_SHIFT 15 |
| 720 | // CHR_XXX CON3 |
| 721 | #define CSDAC_STP_MASK 0x0003 |
| 722 | #define CSDAC_STP_SHIFT 0 |
| 723 | #if defined(__DRV_VBAT_OV_EN_AT_CON3_BIT3__) |
| 724 | #define VBAT_OV_EN_MASK 0x0008 |
| 725 | #define VBAT_OV_EN_SHIFT 3 |
| 726 | #endif // #if defined(__DRV_VBAT_OV_EN_AT_CON3_BIT3__) |
| 727 | #define CSDAC_DLY_MASK 0x0030 |
| 728 | #define CSDAC_DLY_SHIFT 4 |
| 729 | #define VBAT_OV_VTH_MASK 0x00C0 |
| 730 | #define VBAT_OV_VTH_SHIFT 6 |
| 731 | #if defined(__DRV_VBAT_OV_EN_AT_CON3_BIT8__) |
| 732 | #define VBAT_OV_EN_MASK 0x0100 |
| 733 | #define VBAT_OV_EN_SHIFT 8 |
| 734 | #endif // #if defined(__DRV_VBAT_OV_EN_AT_CON3_BIT8__) |
| 735 | #if defined(__DRV_BATON_EN_AT_CON3_BIT9__) |
| 736 | #define BATON_EN_MASK 0x0200 |
| 737 | #define BATON_EN_SHIFT 9 |
| 738 | #endif // #if defined(__DRV_BATON_EN_AT_CON3_BIT9__) |
| 739 | |
| 740 | #define BATON_HT_EN_MASK 0x0400 |
| 741 | #define BATON_HT_EN_SHIFT 10 |
| 742 | |
| 743 | #if defined(__DRV_BATON_EN_AT_CON3_BIT12__) |
| 744 | #define BATON_EN_MASK 0x1000 |
| 745 | #define BATON_EN_SHIFT 12 |
| 746 | #endif // #if defined(__DRV_BATON_EN_AT_CON3_BIT12__) |
| 747 | #if defined(__DRV_OTG_BVALID_EN_AT_CON3_BIT13__) |
| 748 | #define OTG_BVALID_EN_OFFSET CON3_OFFSET |
| 749 | #define OTG_BVALID_EN_MASK 0x2000 |
| 750 | #define OTG_BVALID_EN_SHIFT 13 |
| 751 | #endif // #if defined(__DRV_OTG_BVALID_EN_AT_CON3_BIT13__) |
| 752 | #define VBAT_OV_DET_MASK 0x4000 |
| 753 | #define VBAT_OV_DET_SHIFT 14 |
| 754 | #define BATON_UNDET_MASK 0x8000 |
| 755 | #define BATON_UNDET_SHIFT 15 |
| 756 | // CHR_XXX CON4 |
| 757 | #define PCHR_TEST_MASK 0x0001 |
| 758 | #define PCHR_TEST_SHIFT 0 |
| 759 | #define PCHR_CSDAC_TEST_MASK 0x0002 |
| 760 | #define PCHR_CSDAC_TEST_SHIFT 1 |
| 761 | #define PCHR_RST_MASK 0x0004 |
| 762 | #define PCHR_RST_SHIFT 2 |
| 763 | #define CSDAC_DAT_MASK 0xFF00 |
| 764 | #define CSDAC_DAT_SHIFT 8 |
| 765 | // CHR_XXX CON5 |
| 766 | #define PCHR_FLAG_SEL_MASK 0x000F |
| 767 | #define PCHR_FLAG_SEL_SHIFT 0 |
| 768 | #define PCHR_FLAG_EN_MASK 0x0080 |
| 769 | #define PCHR_FLAG_EN_SHIFT 7 |
| 770 | #define PCHR_FLAG_OUT_MASK 0x0F00 |
| 771 | #define PCHR_FLAG_OUT_SHIFT 8 |
| 772 | #if defined(__DRV_OTG_BVALID_EN_AT_CON5_BIT12__) |
| 773 | #define OTG_BVALID_EN_OFFSET CON5_OFFSET |
| 774 | #define OTG_BVALID_EN_MASK 0x1000 |
| 775 | #define OTG_BVALID_EN_SHIFT 12 |
| 776 | #endif // #if defined(__DRV_OTG_BVALID_EN_AT_CON5_BIT12__) |
| 777 | #if defined(__DRV_OTG_BVALID_DET_AT_CON5_BIT15__) |
| 778 | #define OTG_BVALID_DET_MASK 0x8000 |
| 779 | #define OTG_BVALID_DET_SHIFT 15 |
| 780 | #endif // #if defined(__DRV_OTG_BVALID_DET_AT_CON5_BIT15__) |
| 781 | |
| 782 | // CHR_XXX CON6 |
| 783 | |
| 784 | #define CHRWDT_TD_OFFSET CON6_OFFSET |
| 785 | #define CHRWDT_TD_MASK 0x000F // TTTTTTTTT |
| 786 | #define CHRWDT_TD_SHIFT 0 |
| 787 | |
| 788 | #define CHRWDT_EN_OFFSET CON6_OFFSET |
| 789 | #define CHRWDT_EN_MASK 0x0010 |
| 790 | #define CHRWDT_EN_SHIFT 4 |
| 791 | |
| 792 | // CHR_XXX CON7 |
| 793 | #define CHRWDT_INT_EN_OFFSET CON7_OFFSET |
| 794 | #define CHRWDT_INT_EN_MASK 0x0001 |
| 795 | #define CHRWDT_INT_EN_SHIFT 0 |
| 796 | |
| 797 | #define CHRWDT_FLAG_WR_MASK 0x0002 |
| 798 | #define CHRWDT_FLAG_WR_SHIFT 1 |
| 799 | #define CHRWDT_OUT_MASK 0x8000 |
| 800 | #define CHRWDT_OTU_SHIFT 15 |
| 801 | // CHR_XXX CON8 |
| 802 | #define BGR_RSEL_MASK 0x0007 |
| 803 | #define BGR_RSEL_SHIFT 0 |
| 804 | #define BGR_UNCHOP_PH_MASK 0x0010 |
| 805 | #define BGR_UNCHOP_PH_SHIFT 4 |
| 806 | #define BGR_UNCHOP_MASK 0x0020 |
| 807 | #define BGR_UNCHOP_SHIFT 5 |
| 808 | #define UVLO_VTHL_MASK 0x0300 |
| 809 | #define UVLO_VTHL_SHIFT 8 |
| 810 | |
| 811 | #define ADC_EN_OFFSET CON8_OFFSET |
| 812 | #define ADC_EN_MASK 0x7000 // All ADC channels are enabled at same time |
| 813 | #define ADC_EN_SHIFT 12 |
| 814 | // CHR_XXX CON9 (CHR_BC11_CON0) |
| 815 | |
| 816 | #if defined(__DRV_UPMU_BC11_V1__) |
| 817 | |
| 818 | #if defined(__DRV_UPMU_BC11_MAPPING_V1__) |
| 819 | #define BC11_VREF_VTH_OFFSET CON9_OFFSET |
| 820 | #define BC11_VREF_VTH_MASK 0x0001 |
| 821 | #define BC11_VREF_VTH_SHIFT 0 |
| 822 | |
| 823 | #define BC11_CMP_EN_OFFSET CON9_OFFSET |
| 824 | #define BC11_CMP_EN_MASK 0x0006 |
| 825 | #define BC11_CMP_EN_SHIFT 1 |
| 826 | |
| 827 | #define BC11_IPD_EN_OFFSET CON9_OFFSET |
| 828 | #define BC11_IPD_EN_MASK 0x0018 |
| 829 | #define BC11_IPD_EN_SHIFT 3 |
| 830 | |
| 831 | #define BC11_IPU_EN_OFFSET CON9_OFFSET |
| 832 | #define BC11_IPU_EN_MASK 0x0060 |
| 833 | #define BC11_IPU_EN_SHIFT 5 |
| 834 | |
| 835 | #define BC11_BIAS_EN_OFFSET CON9_OFFSET |
| 836 | #define BC11_BIAS_EN_MASK 0x0080 |
| 837 | #define BC11_BIAS_EN_SHIFT 7 |
| 838 | |
| 839 | #define BC11_BB_CTRL_OFFSET CON9_OFFSET |
| 840 | #define BC11_BB_CTRL_MASK 0x0100 |
| 841 | #define BC11_BB_CTRL_SHIFT 8 |
| 842 | |
| 843 | #define BC11_RST_OFFSET CON9_OFFSET |
| 844 | #define BC11_RST_MASK 0x0200 |
| 845 | #define BC11_RST_SHIFT 9 |
| 846 | |
| 847 | #if defined(__MT6251PMU_E1_BC11_VSRC_EN_AT_TEST_CON1_BIT4__) |
| 848 | #define BC11_VSRC_EN_OFFSET 0x0504 //CHR_CON0+0x0504=TEST_CON1 |
| 849 | #define BC11_VSRC_EN_MASK 0x0030 |
| 850 | #define BC11_VSRC_EN_SHIFT 4 |
| 851 | #else |
| 852 | #define BC11_VSRC_EN_OFFSET CON9_OFFSET |
| 853 | #define BC11_VSRC_EN_MASK 0x0C00 |
| 854 | #define BC11_VSRC_EN_SHIFT 10 |
| 855 | #endif //#if defined(__MT6251PMU_E1_BC11_VSRC_EN_AT_TEST_CON1_BIT4__) |
| 856 | |
| 857 | #define BC11_CMP_OUT_OFFSET CON9_OFFSET |
| 858 | #define BC11_CMP_OUT_MASK 0x8000 |
| 859 | #define BC11_CMP_OUT_SHIFT 15 |
| 860 | #endif //#if defined(__DRV_UPMU_BC11_MAPPING_V1) |
| 861 | |
| 862 | #if defined(__DRV_UPMU_BC11_MAPPING_V2__) |
| 863 | #define BC11_VREF_VTH_OFFSET CHR_CON10_OFFSET |
| 864 | #define BC11_VREF_VTH_MASK 0x0040 |
| 865 | #define BC11_VREF_VTH_SHIFT 6 |
| 866 | |
| 867 | #define BC11_CMP_EN_OFFSET CHR_CON10_OFFSET |
| 868 | #define BC11_CMP_EN_MASK 0x0003 |
| 869 | #define BC11_CMP_EN_SHIFT 0 |
| 870 | |
| 871 | #define BC11_IPD_EN_OFFSET CHR_CON10_OFFSET |
| 872 | #define BC11_IPD_EN_MASK 0x000c |
| 873 | #define BC11_IPD_EN_SHIFT 2 |
| 874 | |
| 875 | #define BC11_IPU_EN_OFFSET CHR_CON10_OFFSET |
| 876 | #define BC11_IPU_EN_MASK 0x0030 |
| 877 | #define BC11_IPU_EN_SHIFT 4 |
| 878 | |
| 879 | #define BC11_BIAS_EN_OFFSET CHR_CON10_OFFSET |
| 880 | #define BC11_BIAS_EN_MASK 0x0080 |
| 881 | #define BC11_BIAS_EN_SHIFT 7 |
| 882 | |
| 883 | #define BC11_BB_CTRL_OFFSET CHR_CON10_OFFSET |
| 884 | #define BC11_BB_CTRL_MASK 0x0100 |
| 885 | #define BC11_BB_CTRL_SHIFT 8 |
| 886 | |
| 887 | #define BC11_RST_OFFSET CHR_CON9_OFFSET |
| 888 | #define BC11_RST_MASK 0x0100 |
| 889 | #define BC11_RST_SHIFT 8 |
| 890 | |
| 891 | #define BC11_VSRC_EN_OFFSET CHR_CON9_OFFSET |
| 892 | #define BC11_VSRC_EN_MASK 0x0003 |
| 893 | #define BC11_VSRC_EN_SHIFT 0 |
| 894 | |
| 895 | #define BC11_CMP_OUT_OFFSET CHR_CON10_OFFSET |
| 896 | #define BC11_CMP_OUT_MASK 0x0200 |
| 897 | #define BC11_CMP_OUT_SHIFT 9 |
| 898 | |
| 899 | #endif //#if defined(__DRV_UPMU_BC11_MAPPING_V2__) |
| 900 | #endif // #if defined(__DRV_UPMU_BC11_V1__) |
| 901 | |
| 902 | |
| 903 | #endif // #if defined(__DRV_UPMU_CHARGER_V1__) |
| 904 | |
| 905 | #if defined(__DRV_UPMU_STRUP_V1__) |
| 906 | #define STRUP_CON0_OFFSET 0x00 |
| 907 | |
| 908 | // STRUP_XXX CON0 |
| 909 | #define USBDL_EN_OFFSET CON0_OFFSET |
| 910 | #define USBDL_EN_MASK 0x0010 |
| 911 | #define USBDL_EN_SHIFT 4 |
| 912 | #endif // #if defined(__DRV_UPMU_STRUP_V1__) |
| 913 | |
| 914 | |
| 915 | |
| 916 | |
| 917 | |
| 918 | #endif //#define __DCL_PMU_COMMON_HW_STRUCT__ |
| 919 | |