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192.168.1.100 / T800_MD / 1eb8f53f94c145708b5ea2c6b9b96ea3d613f607 / . / mcu / driver / peripheral / inc / hif_v2_internal.h
blob: 938fb51db793648a3d2327dc9492d65d04fa8490 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1#ifndef __HIF_V2_INTERNAL_H__
2#define __HIF_V2_INTERNAL_H__
3
4//#include "drv_features.h"
5//#include "kal_release.h"
6#include "reg_base.h"
7#if defined(DRV_HIF_SUPPORT) && defined(DRV_HIF_V2)
8
9
10//#define HIF0_base 0x81180000
11
12// Default: HIF0 is connected to LPCE1. HIF1 is connected to LPCE2.
13#error
14
15//define ECO solution for MT6256E4,MT6575E2 or MTK later chips
16//#if (defined(MT6256_S03) || defined(MT6575_S01) || defined(MT6577)) && defined(__AST_TL1_TDD__)
17//#if (defined(MT6256_S03)) && defined(__AST_TL1_TDD__)
18//#define HIF_ECO_SOLUTION_SUPPORT
19//#endif
20/****************************************************************************
21** Define HIF registers and Macro
22*****************************************************************************/
23#define HIF_MAX_PORT_NUM 4
24#define HIF_ENGINE_COUNT 2
25
26#define HIF_PORT_MCU_A0_LOW_ADDR(n) (HIF0_base+0x0300+n*base_add_increase)
27#define HIF_PORT_MCU_A0_HIGH_ADDR(n) (HIF0_base+0x0310+n*base_add_increase)
28#define HIF_PORT_PDMA_ADDR(n) (HIF0_base+0x0200+n*base_add_increase)
29
30#define HIF_TIMING_CONFIG_WRITE_WAIT_STATE_MASK 0x3F
31#define HIF_TIMING_CONFIG_WRITE_SETUP_TIME_MASK 0xF00
32#define HIF_TIMING_CONFIG_WRITE_HOLD_TIME_MASK 0xF000
33#define HIF_TIMING_CONFIG_READ_LATENCY_TIME_MASK 0x3F0000
34#define HIF_TIMING_CONFIG_READ_SETUP_TIME_MASK 0xF000000
35#define HIF_TIMING_CONFIG_READ_HOLD_TIME_MASK 0xF0000000
36#define HIF_TIMING_CONFIG_CHW_MASK 0xF
37#define HIF_TIMING_CONFIG_WRITE_WAIT_STATE_OFFSET 0
38#define HIF_TIMING_CONFIG_WRITE_SETUP_TIME_OFFSET 8
39#define HIF_TIMING_CONFIG_WRITE_HOLD_TIME_OFFSET 12
40#define HIF_TIMING_CONFIG_READ_LATENCY_TIME_OFFSET 16
41#define HIF_TIMING_CONFIG_READ_SETUP_TIME_OFFSET 24
42#define HIF_TIMING_CONFIG_READ_HOLD_TIME_OFFSET 28
43#define HIF_TIMING_CONFIG_CHW_OFFSET 0
44
45
46#define HIF_STA_REG(n) (HIF0_base+n*base_add_increase+0x0)
47#define HIF_INTEN_REG(n) (HIF0_base+n*base_add_increase+0x4)
48#define HIF_INTSTA_REG(n) (HIF0_base+n*base_add_increase+0x8)
49#define HIF_START_REG(n) (HIF0_base+n*base_add_increase+0xC)
50#define HIF_SWRST_REG(n) (HIF0_base+n*base_add_increase+0x10)
51#define HIF_TIME0_REG(n) (HIF0_base+n*base_add_increase+0x14)
52#define HIF_TIME1_REG(n) (HIF0_base+n*base_add_increase+0x18)
53#define HIF_CON_REG(n) (HIF0_base+n*base_add_increase+0x20)
54#define HIF_DAMOUNT_REG(n) (HIF0_base+n*base_add_increase+0x24)
55//#if defined (HIF_ECO_SOLUTION_SUPPORT)
56#define HIF_ACS_ARB_REG(n) (HIF0_base+n*base_add_increase+0x30)
57
58#define PIF_BUSY_MASK 0x2
59
60#define MCU_ACS_REQ_OFFSET 0
61#define MCU_ACS_STR_OFFSET 2
62//#endif
63
64#define HIF_BUSY_MASK 0x00000001
65#define HIF_CPL_MASK 0x00000001
66#define HIF_START_MASK 0x00000001
67#define HIF_RST_MASK 0x00000001
68#define HIF_HIFW_MASK 0x00000003
69#define HIF_WRITE_MASK 0x00000004
70#define HIF_A0_MASK 0x00000008
71#define HIF_ULTRA_MASK 0x00000010
72
73#define HIF_HIFW_OFFSET 0
74#define HIF_WRITE_OFFSET 2
75#define HIF_A0_OFFSET 3
76#define HIF_ULTRA_OFFSET 4
77
78#define SET_HIF_CE2WR_SETUP_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_WRITE_SETUP_TIME_MASK;\
79 (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_WRITE_SETUP_TIME_OFFSET;
80#define SET_HIF_CE2WR_HOLD_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_WRITE_HOLD_TIME_MASK;\
81 (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_WRITE_HOLD_TIME_OFFSET;
82#define SET_HIF_CE2RD_SETUP_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_READ_SETUP_TIME_MASK;\
83 (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_READ_SETUP_TIME_OFFSET;
84#define SET_HIF_CE2RD_HOLD_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_READ_HOLD_TIME_MASK;\
85 (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_READ_HOLD_TIME_OFFSET;
86#define SET_HIF_WRITE_WAIT_STATE(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_WRITE_WAIT_STATE_MASK;\
87 (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_WRITE_WAIT_STATE_OFFSET;
88#define SET_HIF_READ_LATENCY_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_READ_LATENCY_TIME_MASK;\
89 (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_READ_LATENCY_TIME_OFFSET;
90#define SET_HIF_CS_HIGH_WIDTH_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME1_REG(n)) &= ~HIF_TIMING_CONFIG_CHW_MASK;\
91 (*(volatile kal_uint32*)HIF_TIME1_REG(n)) |= (val)<<HIF_TIMING_CONFIG_CHW_OFFSET;
92#define SET_HIF_BUS_WIDTH(n, val) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_HIFW_MASK;\
93 (*(volatile kal_uint32*)HIF_CON_REG(n)) |= (val/8-1)<<HIF_HIFW_OFFSET;
94#define SET_HIF_WRITE(n) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_WRITE_MASK;\
95 (*(volatile kal_uint32*)HIF_CON_REG(n)) |= 1<<HIF_WRITE_OFFSET;
96#define SET_HIF_READ(n) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_WRITE_MASK;\
97 (*(volatile kal_uint32*)HIF_CON_REG(n)) |= 0<<HIF_WRITE_OFFSET;
98#define SET_HIF_A0_HIGH(n) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_A0_MASK;\
99 (*(volatile kal_uint32*)HIF_CON_REG(n)) |= 1<<HIF_A0_OFFSET;
100#define SET_HIF_A0_LOW(n) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_A0_MASK;\
101 (*(volatile kal_uint32*)HIF_CON_REG(n)) |= 0<<HIF_A0_OFFSET;
102#define SET_HIF_ULTRA(n, val) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_ULTRA_MASK;\
103 (*(volatile kal_uint32*)HIF_CON_REG(n)) |= (val)<<HIF_ULTRA_OFFSET;
104#define GET_HIF_ULTRA(n) (((*(volatile kal_uint32*)HIF_CON_REG(n))>> HIF_ULTRA_OFFSET) & 0x1);
105#define SET_HIF_DAMOUNT(n, val) (*(volatile kal_uint32*)HIF_DAMOUNT_REG(n)) = (val) - 1;
106
107#define ENABLE_HIF_INTR(n) (*(volatile kal_uint32*)HIF_INTEN_REG(n)) = 1;
108#define DISABLE_HIF_INTR(n) (*(volatile kal_uint32*)HIF_INTEN_REG(n)) = 0;
109
110#define START_HIF(n) (*(volatile kal_uint32*)HIF_START_REG(n)) = 0;\
111 (*(volatile kal_uint32*)HIF_START_REG(n)) = 1;
112#define HIF_BUSY(n) ((*(volatile kal_uint32*)HIF_STA_REG(n)) & HIF_BUSY_MASK)
113#define HIF_INT_CLEAR(n) do {volatile kal_uint32 hif_intsta = (*(volatile kal_uint32*)HIF_INTSTA_REG(n)));} while(0);
114//#if defined (HIF_ECO_SOLUTION_SUPPORT)
115#define SET_HIF_MCU_ACS_REQ(n) (*(volatile kal_uint32*)HIF_ACS_ARB_REG(n)) |= 1<<MCU_ACS_REQ_OFFSET
116#define SET_HIF_MCU_ACS_STA(n) (*(volatile kal_uint32*)HIF_ACS_ARB_REG(n)) |= 1<<MCU_ACS_STR_OFFSET
117#define CLEAR_HIF_MCU_ACS_REQ_STA(n) (*(volatile kal_uint32*)HIF_ACS_ARB_REG(n)) = 0
118#define PIF_BUSY(n) ((*(volatile kal_uint32*)HIF_ACS_ARB_REG(n)) & PIF_BUSY_MASK)
119//#endif
120
121// power gating definitions
122#error
123// End of power gating definitions
124/****************************************************************************
125** NLI arbiter definitions
126*****************************************************************************/
127#define REG_NLI_ARB_CS *((volatile unsigned int *) (NLI_ARB_base + 0x0014))
128#define REG_NLI_ARB_CONT_GRANT *((volatile unsigned int *) (NLI_ARB_base + 0x0018))
129#define REG_NLI_ARB_HANDOVER *((volatile unsigned int *) (NLI_ARB_base + 0x001C))
130
131
132#define NLI_ARB_CE0B_SEL_OFS 0
133#define NLI_ARB_CE1B_SEL_OFS 4
134#define NLI_ARB_CE2B_SEL_OFS 8
135#define NLI_ARB_CE3B_SEL_OFS 12
136#define NLI_ARB_CEB_SEL_OFS(n) (4 * n)
137
138#define NLI_ARB_CE0B_SEL_MASK 0x7
139#define NLI_ARB_CE1B_SEL_MASK 0x70
140#define NLI_ARB_CE2B_SEL_MASK 0x700
141#define NLI_ARB_CE3B_SEL_MASK 0x7000
142#define NLI_ARB_CEB_SEL_MASK(n) (0x7 << (NLI_ARB_CEB_SEL_OFS(n)))
143#define NLI_ARB_SET_LPCE_SEL(lpce_num, hif_id) \
144{ \
145 volatile unsigned int temp_REG_NLI_ARB_CS; \
146 temp_REG_NLI_ARB_CS = REG_NLI_ARB_CS; \
147 temp_REG_NLI_ARB_CS &= (~(NLI_ARB_CEB_SEL_MASK(lpce_num))); \
148 temp_REG_NLI_ARB_CS |= ((hif_id+3) << (NLI_ARB_CEB_SEL_OFS(lpce_num))); \
149 REG_NLI_ARB_CS = temp_REG_NLI_ARB_CS; \
150}
151/****************************************************************************
152** PDMA definitions
153*****************************************************************************/
154#define PDMA_OFS 0x80
155// PDMA definitions
156
157
158/****************************************************************************
159** PDMA Control Register Macros
160*****************************************************************************/
161
162#define PDMA_SET_BUF_ADDR(if_num, val) REG_PDMA_HIF_MEM_ADDR(if_num) = val;
163#define PDMA_RD_BIT 0x1
164#define PDMA_SET_RW_DIRECTION(if_num, R) REG_PDMA_HIF_CON(if_num) &= (~(PDMA_RD_BIT));\
165 REG_PDMA_HIF_CON(if_num) |= (R & 0x1);
166#define PDMA_BURST_LEN_MASK 0x70000
167#define PDMA_BURST_LEN_OFS 16
168#define PDMA_SET_BURST_LEN(if_num, len) REG_PDMA_HIF_CON(if_num) &= (~(PDMA_BURST_LEN_MASK));\
169 REG_PDMA_HIF_CON(if_num) |= ((len & 0x7) << PDMA_BURST_LEN_OFS);
170#define PDMA_SET_BUF_LEN(if_num, len) REG_PDMA_HIF_LEN(if_num) = len
171#define PDMA_START(if_num) REG_PDMA_HIF_EN(if_num) = 1;
172#define PDMA_SW_RST(if_num) REG_PDMA_HIF_RST(if_num) = 1;
173
174// End of PDMA definitions
175
176typedef struct
177{
178 kal_bool realtime_callback;
179 kal_uint32 port;
180 kal_uint32 engine_id;
181 kal_uint32 user;
182 HIF_CONFIG_T config;
183 kal_bool A0H_CPU_BUSY;
184 kal_bool A0L_CPU_BUSY;
185} HIF_INTERNAL_HANDLE_T;
186
187// HIF internal functions
188void hif0_lisr(void);
189void hif0_hisr(void);
190void hif1_lisr(void);
191void hif1_hisr(void);
192void hif_wait_for_idle(kal_uint32 engine_id);
193
194#endif
195#endif