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192.168.1.100 / T800_MD / 1eb8f53f94c145708b5ea2c6b9b96ea3d613f607 / . / mcu / driver / peripheral / inc / i2c_pmic_hw.h
blob: 1ae38c3144662203eebf1c6bf22d7223231b094b [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * i2c_pmic_hw.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file is intends for I2C DUAL driver.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
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105 *
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107 *------------------------------------------------------------------------------
108 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
109 *============================================================================
110 ****************************************************************************/
111#ifndef _I2C_PMIC_HW_H
112#define _I2C_PMIC_HW_H
113#include "drv_features.h"
114
115#include "drv_comm.h"
116#include "reg_base.h"
117
118#if defined(DRV_I2C_PMIC)
119
120#ifndef __DRV_DEBUG_I2C_PMIC_REG_READ_WRITE__
121#define I2C_PMIC_DRV_ClearBits16(addr, data) DRV_ClearBits(addr,data)
122#define I2C_PMIC_DRV_SetBits16(addr, data) DRV_SetBits(addr,data)
123#define I2C_PMIC_DRV_WriteReg16(addr, data) DRV_WriteReg(addr, data)
124#define I2C_PMIC_DRV_ReadReg16(addr) DRV_Reg(addr)
125#define I2C_PMIC_DRV_ClearBits32(addr, data) DRV_ClearBits32(addr, data)
126#define I2C_PMIC_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
127#else // #ifndef __DRV_DEBUG_I2C_PMIC_REG_READ_WRITE__
128#define I2C_PMIC_DRV_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
129#define I2C_PMIC_DRV_SetBits16(addr) DRV_DBG_SetBits(addr)
130#define I2C_PMIC_DRV_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
131#define I2C_PMIC_DRV_ReadReg16(addr) DRV_DBG_Reg(addr)
132#define I2C_PMIC_DRV_ClearBits32(addr, data) DRV_DBG_ClearBits32(addr, data)
133#define I2C_PMIC_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
134#endif // #ifndef __DRV_DEBUG_I2C_PMIC_REG_READ_WRITE__
135
136
137//#define I2CP_base I2C_DUAL_base
138#define I2CP_base I2C_base
139#define PMIC6327_I2C_ID 0xC0
140
141
142// I2CP means I2C for PMIC
143#define I2CP_DATA_PORT (I2CP_base + 0x00)
144#define I2CP_SLAVE_ADDR (I2CP_base + 0x04)
145#define I2CP_INTR_MASK (I2CP_base + 0x08)
146#define I2CP_INTR_STAT (I2CP_base + 0x0C)
147#define I2CP_CTRL (I2CP_base + 0x10)
148#define I2CP_TRANSFER_LEN (I2CP_base + 0x14)
149#define I2CP_TRANSFER_LEN_AUX (I2CP_base + 0x6c)
150#define I2CP_TRANSAC_LEN (I2CP_base + 0x18)
151#define I2CP_DELAY_LEN (I2CP_base + 0x1C)
152#define I2CP_TIMING (I2CP_base + 0x20)
153#define I2CP_START (I2CP_base + 0x24)
154#define I2CP_FIFO_STAT (I2CP_base + 0x30)
155#define I2CP_FIFO_THRESH (I2CP_base + 0x34)
156#define I2CP_FIFO_ADDR_CLR (I2CP_base + 0x38)
157#define I2CP_IO_CONFIG (I2CP_base + 0x40)
158#define I2CP_HS (I2CP_base + 0x48)
159#define I2CP_SOFTRESET (I2CP_base + 0x50)
160#define I2CP_DEBUGSTAT (I2CP_base + 0x64)
161#define I2CP_DEBUGCTRL (I2CP_base + 0x68)
162#define I2CP_TIMEOUT (I2CP_base + 0x74)
163#define I2CP_VERSION (I2CP_base + 0x78)
164
165
166// 0x00
167#define I2CP_DATA_PORT_MASK 0x00FF
168#define I2CP_DATA_PORT_SHIFT 0
169
170// 0x04
171#define I2CP_SLAVE_ADDR_MASK 0x00FF
172#define I2CP_SLAVE_ADDR_SHIFT 0
173
174// 0x08
175#define I2CP_INTR_MASK_TRANS_COMP_MASK 0x0001
176#define I2CP_INTR_MASK_TRANS_COMP_SHIFT 0
177#define I2CP_INTR_MASK_ACK_ERR_MASK 0x0002
178#define I2CP_INTR_MASK_ACK_ERR_SHIFT 1
179#define I2CP_INTR_MASK_HSNAK_ERR_MASK 0x0004
180#define I2CP_INTR_MASK_HSNAK_ERR_SHIFT 2
181#define I2CP_INTR_MASK_TIMEOUT_MASK 0x0010
182#define I2CP_INTR_MASK_TIMEOUT_SHIFT 4
183
184// 0x0C
185#define I2CP_INTR_STAT_TRANS_COMP_MASK 0x0001
186#define I2CP_INTR_STAT_TRANS_COMP_SHIFT 0
187#define I2CP_INTR_STAT_ACK_ERR_MASK 0x0002
188#define I2CP_INTR_STAT_ACK_ERR_SHIFT 1
189#define I2CP_INTR_STAT_HSNAK_ERR_MASK 0x0004
190#define I2CP_INTR_STAT_HSNAK_ERR_SHIFT 2
191#define I2CP_INTR_STAT_TIMEOUT_MASK 0x0010
192#define I2CP_INTR_STAT_TIMEOUT_SHIFT 4
193
194
195// 0x10
196#define I2CP_CTRL_RESTART_MASK 0x0002
197#define I2CP_CTRL_RESTART_SHIFT 1
198#define I2CP_CTRL_DMA_EN_MASK 0x0004
199#define I2CP_CTRL_DMA_EN_SHIFT 2
200#define I2CP_CTRL_CLK_EXT_EN_MASK 0x0008
201#define I2CP_CTRL_CLK_EXT_EN_SHIFT 3
202#define I2CP_CTRL_DIR_CHANGE_MASK 0x0010
203#define I2CP_CTRL_DIR_CHANGE_SHIFT 4
204#define I2CP_CTRL_ACKERR_DET_EN_MASK 0x0020
205#define I2CP_CTRL_ACKERR_DET_EN_SHIFT 5
206#define I2CP_CTRL_TRANSFER_LEN_CHANGE_MASK 0x0040
207#define I2CP_CTRL_TRANSFER_LEN_CHANGE_SHIFT 6
208#define I2CP_CTRL_RESET_BUS_BUSY_EN_MASK 0x0080
209#define I2CP_CTRL_RESET_BUS_BUSY_EN_SHIFT 7
210#define I2CP_CTRL_TIMEOUT_EN_MASK 0x0100
211#define I2CP_CTRL_TIMEOUT_EN_SHIFT 8
212
213// 0x14
214#define I2CP_TRANSFER_LEN_TRANSFER_LEN_MASK 0x00FF
215#define I2CP_TRANSFER_LEN_TRANSFER_LEN_SHIFT 0
216
217// 0x6c
218#define I2CP_TRANSFER_LEN_AUX_TRANSFER_LEN_AUX_MASK 0x00FF
219#define I2CP_TRANSFER_LEN_AUX_TRANSFER_LEN_AUX_SHIFT 0
220
221// 0x18
222#define I2CP_TRANSAC_LEN_TRANSAC_LEN_MASK 0x00FF
223#define I2CP_TRANSAC_LEN_TRANSAC_LEN_SHIFT 0
224
225// 0x1C
226#define I2CP_DELAY_LEN_DELAY_LEN_MASK 0x00FF
227#define I2CP_DELAY_LEN_DELAY_LEN_SHIFT 0
228
229// 0x20
230#define I2CP_TIMING_STEP_CNT_DIV_MASK 0x003F
231#define I2CP_TIMING_STEP_CNT_DIV_SHIFT 0
232#define I2CP_TIMING_SAMPLE_CNT_DIV_MASK 0x0700
233#define I2CP_TIMING_SAMPLE_CNT_DIV_SHIFT 8
234#define I2CP_TIMING_DATA_READ_MASK 0x7000
235#define I2CP_TIMING_DATA_READ_SHIFT 12
236#define I2CP_TIMING_DATA_READ_ADJ_MASK 0x8000
237#define I2CP_TIMING_DATA_READ_ADJ_SHIFT 15
238
239// 0x24
240#define I2CP_START_START_MASK 0x0001
241#define I2CP_START_START_SHIFT 0
242
243// 0x30
244#define I2CP_FIFO_STAT_RD_EMPTY_MASK 0x0001
245#define I2CP_FIFO_STAT_RD_EMPTY_SHIFT 0
246#define I2CP_FIFO_STAT_WR_FULL_MASK 0x0002
247#define I2CP_FIFO_STAT_WR_FULL_SHIFT 1
248#define I2CP_FIFO_STAT_OFFSET_MASK 0x00F0
249#define I2CP_FIFO_STAT_OFFSET_SHIFT 4
250#define I2CP_FIFO_STAT_WR_ADDR_MASK 0x0F00
251#define I2CP_FIFO_STAT_WR_ADDR_SHIFT 8
252#define I2CP_FIFO_STAT_RD_ADDR_MASK 0xF000
253#define I2CP_FIFO_STAT_RD_ADDR_SHIFT 12
254
255// 0x34
256#define I2CP_FIFO_THRESH_RX_TRIG_MASK 0x0007
257#define I2CP_FIFO_THRESH_RX_TRIG_SHIFT 0
258#define I2CP_FIFO_THRESH_TX_TRIG_MASK 0x0700
259#define I2CP_FIFO_THRESH_TX_TRIG_SHIFT 8
260
261// 0x38
262#define I2CP_FIFO_ADDR_CLR_CR_MASK 0x0001
263#define I2CP_FIFO_ADDR_CLR_CR_SHIFT 0
264
265// 0x40
266#define I2CP_IO_CONFIG_SCL_IO_MASK 0x0001
267#define I2CP_IO_CONFIG_SCL_IO_SHIFT 0
268#define I2CP_IO_CONFIG_SDA_IO_MASK 0x0002
269#define I2CP_IO_CONFIG_SDA_IO_SHIFT 1
270#define I2CP_IO_CONFIG_SYNC_EN_MASK 0x0004
271#define I2CP_IO_CONFIG_SYNC_EN_SHIFT 2
272#define I2CP_IO_CONFIG_IDLE_OE_EN_MASK 0x0008
273#define I2CP_IO_CONFIG_IDLE_OE_SIFT 3
274
275// 0x48
276#define I2CP_HS_HS_EN_MASK 0x0001
277#define I2CP_HS_HS_EN_SHIFT 0
278#define I2CP_HS_HS_NAK_ERR_DET_EN_MASK 0x0002
279#define I2CP_HS_HS_NAK_ERR_DET_EN_SHIFT 1
280#define I2CP_HS_MASTER_CODE_MASK 0x0070
281#define I2CP_HS_MASTER_CODE_SHIFT 4
282#define I2CP_HS_HS_STEP_CNT_DIV_MASK 0x0700
283#define I2CP_HS_HS_STEP_CNT_DIV_SHIFT 8
284#define I2CP_HS_HS_SAMPLE_CNT_DIV_MASK 0x7000
285#define I2CP_HS_HS_SAMPLE_CNT_DIV_SHIFT 12
286
287// 0x50
288#define I2CP_SOFTRESET_SOFTRESET_MASK 0x0001
289#define I2CP_SOFTRESET_SOFTRESET_SHIFT 0
290
291//0x64
292#define I2CP_DEBUG_STAT_MASTER_STAT_MASK 0x001f
293#define I2CP_DEBUG_STAT_MASTER_STAT_SHIFT 0
294#define I2CP_DEBUG_STAT_MASTER_READ_MASK 0x0020
295#define I2CP_DEBUG_STAT_MASTER_READ_SHIFT 5
296#define I2CP_DEBUG_STAT_MASTER_WRITE_MASK 0x0040
297#define I2CP_DEBUG_STAT_MASTER_WRITE_SHIFT 6
298#define I2CP_DEBUG_STAT_BUS_BUSY_MASK 0x0080
299#define I2CP_DEBUG_STAT_BUS_BUSY_SHIFT 7
300
301
302
303///////////////////////////////////////////////////////////////////////////////
304// Ch1 macros
305#define I2C_PMIC_CLEAR_FIFO(val) I2C_PMIC_DRV_WriteReg16(I2CP_FIFO_ADDR_CLR, (kal_uint16)1)
306#define I2C_PMIC_CLEAR_INTR_STAT(val) {\
307 kal_uint16 tmp;\
308 tmp = I2C_PMIC_DRV_ReadReg16(I2CP_INTR_STAT);\
309 tmp &= (I2CP_INTR_STAT_TRANS_COMP_MASK | I2CP_INTR_STAT_ACK_ERR_MASK|I2CP_INTR_STAT_HSNAK_ERR_MASK|I2CP_INTR_STAT_TIMEOUT_MASK);\
310 tmp |= (val);\
311 I2C_PMIC_DRV_WriteReg16(I2CP_INTR_STAT, tmp);\
312}
313#define I2C_PMIC_SET_SLAVE_ADDR(val) I2C_PMIC_DRV_WriteReg16(I2CP_SLAVE_ADDR, (kal_uint16)val)
314#define I2C_PMIC_SET_TRANSFER_LEN(len1, len2) {\
315 kal_uint16 tmp;\
316 tmp = I2C_PMIC_DRV_ReadReg16(I2CP_TRANSFER_LEN);\
317 tmp &= ~(I2CP_TRANSFER_LEN_TRANSFER_LEN_MASK);\
318 tmp |= ((kal_uint16)len1 << I2CP_TRANSFER_LEN_TRANSFER_LEN_SHIFT);\
319 I2C_PMIC_DRV_WriteReg16(I2CP_TRANSFER_LEN, tmp);\
320 tmp = I2C_PMIC_DRV_ReadReg16(I2CP_TRANSFER_LEN_AUX);\
321 tmp &= ~(I2CP_TRANSFER_LEN_AUX_TRANSFER_LEN_AUX_MASK);\
322 tmp |= ((kal_uint16)len1 << I2CP_TRANSFER_LEN_AUX_TRANSFER_LEN_AUX_SHIFT);\
323 I2C_PMIC_DRV_WriteReg16(I2CP_TRANSFER_LEN_AUX, tmp);\
324}
325
326#define I2C_PMIC_SET_TIMING(sample_cnt, step_cnt) {\
327 kal_uint16 tmp;\
328 tmp = I2C_PMIC_DRV_ReadReg16(I2CP_TIMING);\
329 tmp &= ~(I2CP_TIMING_STEP_CNT_DIV_MASK | I2CP_TIMING_SAMPLE_CNT_DIV_MASK);\
330 tmp |= ((kal_uint16)sample_cnt << I2CP_TIMING_SAMPLE_CNT_DIV_SHIFT);\
331 tmp |= ((kal_uint16)step_cnt << I2CP_TIMING_STEP_CNT_DIV_SHIFT);\
332 I2C_PMIC_DRV_WriteReg16(I2CP_TIMING, tmp);\
333}
334
335#define I2C_PMIC_SET_TRANSAC_LEN(len) I2C_PMIC_DRV_WriteReg16(I2CP_TRANSAC_LEN, (kal_uint16)len);
336#define I2C_PMIC_SET_DIR_CHANGE(val) {\
337 kal_uint16 tmp;\
338 tmp = I2C_PMIC_DRV_ReadReg16(I2CP_CTRL);\
339 tmp &= ~I2CP_CTRL_DIR_CHANGE_MASK;\
340 tmp |= ((kal_uint16)val << I2CP_CTRL_DIR_CHANGE_SHIFT);\
341 I2C_PMIC_DRV_WriteReg16(I2CP_CTRL, tmp);\
342}
343
344
345#define I2C_PMIC_SET_ACKERR_DET_EN(val) {\
346 kal_uint16 tmp;\
347 tmp = I2C_PMIC_DRV_ReadReg16(I2CP_CTRL);\
348 tmp &= ~I2CP_CTRL_ACKERR_DET_EN_MASK;\
349 tmp |= ((kal_uint16)val << I2CP_CTRL_ACKERR_DET_EN_SHIFT);\
350 I2C_PMIC_DRV_WriteReg16(I2CP_CTRL, tmp);\
351}
352
353#define I2C_PMIC_SET_CLK_EXT_EN(val) {\
354 kal_uint16 tmp;\
355 tmp = I2C_PMIC_DRV_ReadReg16(I2CP_CTRL);\
356 tmp &= ~I2CP_CTRL_CLK_EXT_EN_MASK;\
357 tmp |= ((kal_uint16)val << I2CP_CTRL_CLK_EXT_EN_SHIFT);\
358 I2C_PMIC_DRV_WriteReg16(I2CP_CTRL, tmp);\
359}
360
361
362#define I2C_PMIC_SET_RESTART(val) {\
363 kal_uint16 tmp;\
364 tmp = I2C_PMIC_DRV_ReadReg16(I2CP_CTRL);\
365 tmp &= ~I2CP_CTRL_RESTART_MASK;\
366 tmp |= ((kal_uint16)val << I2CP_CTRL_RESTART_SHIFT);\
367 I2C_PMIC_DRV_WriteReg16(I2CP_CTRL, tmp);\
368}
369
370
371#define I2C_PMIC_SET_INTR(val) {\
372 kal_uint16 tmp;\
373 tmp = I2C_PMIC_DRV_ReadReg16(I2CP_INTR_MASK);\
374 tmp |= (val & (I2CP_INTR_MASK_TRANS_COMP_MASK | I2CP_INTR_MASK_ACK_ERR_MASK | I2CP_INTR_MASK_HSNAK_ERR_MASK));\
375 I2C_PMIC_DRV_WriteReg16(I2CP_INTR_MASK, (kal_uint16)tmp);\
376}
377
378#define I2C_PMIC_CLR_INTR(val) {\
379 kal_uint16 tmp;\
380 tmp = I2C_PMIC_DRV_ReadReg16(I2CP_INTR_MASK);\
381 tmp &= ~(val & (I2CP_INTR_MASK_TRANS_COMP_MASK | I2CP_INTR_MASK_ACK_ERR_MASK | I2CP_INTR_MASK_HSNAK_ERR_MASK) );\
382 I2C_PMIC_DRV_WriteReg16(I2CP_INTR_MASK, (kal_uint16)tmp);\
383}
384
385
386#define I2C_PMIC_SET_DATA_PORT(val) I2C_PMIC_DRV_WriteReg16(I2CP_DATA_PORT, (kal_uint16)val)
387#define I2C_PMIC_GET_START() ((I2C_PMIC_DRV_ReadReg16(I2CP_START)&I2CP_START_START_MASK)>>I2CP_START_START_SHIFT)
388#define I2C_PMIC_SET_START(val) I2C_PMIC_DRV_WriteReg16(I2CP_START, I2CP_START_START_MASK);
389
390
391
392#endif // #if defined(DRV_I2C_PMIC)
393
394#endif // #ifndef _I2C_PMIC_HW_H
395