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192.168.1.100 / T800_MD / 1eb8f53f94c145708b5ea2c6b9b96ea3d613f607 / . / mcu / driver / peripheral / inc / rtc_sw_new.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * rtc_sw.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file is intends for RTC driver and adaption.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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264 *
265 *------------------------------------------------------------------------------
266 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
267 *============================================================================
268 ****************************************************************************/
269#ifndef _RTC_SW_H
270#define _RTC_SW_H
271
272#include "drv_comm.h"
273#include "kal_general_types.h"
274#include "kal_public_defs.h"
275
276#define ONE_SHOT_DIS 0
277#define ONE_SHOT_EN 1
278
279#define RTC_BBPU_KEY 0x4300
280
281#define RTC_BBPU_ALARM_SW 0x0001
282#if defined(DRV_RTC_BBPU_AS_6205) || defined(DRV_RTC_BBPU_AS_6208) || defined(FPGA)
283 #define RTC_BBPU_PWR_POLARITY 0x0002
284#endif /*DRV_RTC_BBPU_AS_6205,DRV_RTC_BBPU_AS_6208,FPGA*/
285
286#if defined(DRV_RTC_BBPU_AS_6205B) || defined(DRV_RTC_BBPU_AS_6238)
287 #define RTC_BBPU_WRITE_EN 0x0002
288 #define RTC_BBPU_PWR_SW 0x0004
289 #define RTC_BBPU_AUTOPDN 0x0008
290 #if defined(DRV_RTC_BBPU_AS_6238)
291 #define RTC_BBPU_CLRPKY 0x0010
292 #define RTC_BBPU_RELOAD 0x0020
293 #define RTC_BBPU_CBUSY 0x0040
294 #define RTC_BBPU_DBING 0x0080
295 #endif
296#endif /*DRV_RTC_BBPU_AS_6205B*/
297
298#if defined(DRV_RTC_BBPU_AS_6218)
299 #define RTC_BBPU_PWR_POLARITY 0x0002
300 #define RTC_BBPU_PWR_SW 0x0004
301 #define RTC_BBPU_AUTOPDN 0x0008
302#endif /*DRV_RTC_BBPU_AS_6218*/
303
304#if defined(DRV_RTC_BBPU_AS_6205)
305 #define RTC_BBPU_PWR_SW 0x0004
306 #define RTC_BBPU_PDN_XOSC32K 0x0010
307#endif /*(DRV_RTC_BBPU_AS_6205)*/
308#if defined(DRV_RTC_BBPU_AS_6208) || defined(FPGA)
309 #define RTC_BBPU_PDN_XOSC32K 0x0004
310 #define RTC_BBPU_PWR_SW 0x0010
311#endif /*(DRV_RTC_BBPU_AS_6208,FPGA)*/
312
313#if defined(DRV_RTC_BBPU_AS_6276)
314 #define RTC_BBPU_PWR_SW 0x0004
315 #define RTC_BBPU_AUTOPDN 0x0008
316 #define RTC_BBPU_CLRPKY 0x0010
317 #define RTC_BBPU_RELOAD 0x0020
318 #define RTC_BBPU_CBUSY 0x0040
319#endif /*DRV_RTC_BBPU_AS_6205B*/
320
321
322#if defined(DRV_RTC_BBPU_AS_6205) || defined(DRV_RTC_BBPU_AS_6208) || defined(FPGA)
323 #define RTC_BBPU_POWERON (RTC_BBPU_PDN_XOSC32K|RTC_BBPU_PWR_SW|RTC_BBPU_PWR_POLARITY|RTC_BBPU_ALARM_SW|RTC_BBPU_KEY)
324 #define RTC_BBPU_POWEROFF (RTC_BBPU_PDN_XOSC32K|RTC_BBPU_PWR_POLARITY|RTC_BBPU_ALARM_SW|RTC_BBPU_KEY)
325#endif /*DRV_RTC_BBPU_AS_6205,DRV_RTC_BBPU_AS_6208,FPGA*/
326
327#if defined(DRV_RTC_BBPU_AS_6205B) || defined(DRV_RTC_BBPU_AS_6238)
328 #define RTC_BBPU_POWERON (RTC_BBPU_PWR_SW|RTC_BBPU_WRITE_EN|RTC_BBPU_ALARM_SW|RTC_BBPU_AUTOPDN|RTC_BBPU_KEY)
329 #define RTC_BBPU_POWEROFF (RTC_BBPU_WRITE_EN|RTC_BBPU_ALARM_SW|RTC_BBPU_AUTOPDN|RTC_BBPU_KEY)
330#endif /*DRV_RTC_BBPU_AS_6205B*/
331/*0227 TY removes RTC_BBPU_ALARM_SW*/
332#if defined(DRV_RTC_BBPU_AS_6218)
333 #define RTC_BBPU_POWERON (RTC_BBPU_PWR_SW|RTC_BBPU_PWR_POLARITY|RTC_BBPU_ALARM_SW|RTC_BBPU_AUTOPDN|RTC_BBPU_KEY)
334 #define RTC_BBPU_POWEROFF (RTC_BBPU_PWR_POLARITY|RTC_BBPU_ALARM_SW|RTC_BBPU_AUTOPDN|RTC_BBPU_KEY)
335#endif /*DRV_RTC_BBPU_AS_6218*/
336
337#if defined(DRV_RTC_BBPU_AS_6276)
338 #define RTC_BBPU_POWERON (RTC_BBPU_PWR_SW|RTC_BBPU_ALARM_SW|RTC_BBPU_AUTOPDN|RTC_BBPU_KEY)
339 #define RTC_BBPU_POWEROFF (RTC_BBPU_ALARM_SW|RTC_BBPU_AUTOPDN|RTC_BBPU_KEY)
340#endif /*DRV_RTC_BBPU_AS_6205B*/
341
342typedef struct __rtc
343{
344 kal_uint8 rtc_sec; /* seconds after the minute - [0,59] */
345 kal_uint8 rtc_min; /* minutes after the hour - [0,59] */
346 kal_uint8 rtc_hour; /* hours after the midnight - [0,23] */
347 kal_uint8 rtc_day; /* day of the month - [1,31] */
348 kal_uint8 rtc_mon; /* months - [1,12] */
349 kal_uint8 rtc_wday; /* days in a week - [1,7] */
350 kal_uint8 rtc_year; /* years - [0,127] */
351} t_rtc;
352
353typedef struct
354{
355 void (*rtc_tcfunc)(void);
356 void (*rtc_alfunc)(void);
357}rtc_callbac;
358
359typedef struct
360{
361 kal_hisrid hisr;
362}rtc_module;
363
364typedef struct
365{
366kal_bool time_valid;
367t_rtc rtc_time;
368kal_bool ticks_diff_valid;
369kal_int32 ticks_diff_per_hour;
370} rtc_nvram_data;
371
372typedef struct{
373 module_type dest_mod_id;
374 sap_type sap_id;
375 msg_type msg_id;
376}RTC_REG_MODULE_ILM_INFO_T;
377
378typedef enum
379{
380 rtc_pdn1 = 0,
381 rtc_pdn2,
382 rtc_max_index
383} RTC_PDN_INDEX;
384
385#if defined(DRV_RTC_REG_SPAR)
386typedef enum
387{
388 rtc_spar0 = 0,
389 rtc_spar1,
390 rtc_spar_max_index
391}RTC_SPAR_INDEX;
392#endif
393
394#if defined(DRV_RTC_GPIO)
395typedef enum {
396 RTC_GPIO_DISABLE = 0,
397 RTC_GPIO_EXPORT_32K,
398 RTC_GPIO_EXPORT_COREDETB,
399}RTC_GPIO_MODE_enum;
400
401typedef enum {
402 RTC_GPIO_NO_PULL = 0,
403 RTC_GPIO_PULL_DOWN,
404 RTC_GPIO_PULL_UP
405}RTC_GPIO_PULL_TYPE_enum;
406
407typedef enum {
408 RTC_GPIO_DS_4mA = 0,
409 RTC_GPIO_DS_8mA,
410 RTC_GPIO_DS_12mA,
411 RTC_GPIO_DS_16mA
412}RTC_GPIO_DRIVING_STRENGTH_enum;
413#endif //defined(DRV_RTC_GPIO)
414
415#if defined(DRV_RTC_REG_COMM)
416
417kal_uint16 RTC_Read_PDN(RTC_PDN_INDEX PDNIndex);
418void RTC_Set_PDN_bits(RTC_PDN_INDEX PDNIndex,kal_uint16 flag);
419void RTC_Clear_PDN_bits(RTC_PDN_INDEX PDNIndex,kal_uint16 flag);
420void RTC_Write_PDN_bits(RTC_PDN_INDEX PDNIndex,kal_uint16 flag);
421
422#endif //#if defined(DRV_RTC_REG_COMM)
423
424#if defined(DRV_RTC_REG_SPAR)
425kal_uint16 RTC_Read_SPAR(RTC_SPAR_INDEX SPARIndex);
426void RTC_Write_SPAR(RTC_SPAR_INDEX SPARIndex, kal_uint16 flag);
427#endif // End of #if defined(DRV_RTC_REG_SPAR)
428// ============================================================
429// Exported APIs, used by modules other than driver level functions
430extern void RTC_Config_(kal_uint8 AL_EN,kal_uint8 TC_EN);
431extern void RTC_InitTC_Time(t_rtc *rtctime);
432extern void RTC_GetTime_(t_rtc *rtctime);
433extern void RTC_SetAlarm(t_rtc *rtctime);
434extern kal_bool RTC_GetALTime(t_rtc *rtctime);
435extern kal_bool RTC_isFisrtOn(void);
436extern void RTC_setPWRKey(void);
437extern void RTC_setXOSC_(void);
438extern void RTC_unlockPROT(void);
439#if defined(DRV_RTC_LOW_POWER_DETECT)
440extern void RTC_Clear_LPSTA_RAW(void);
441extern void RTC_Set_GPIO_Output_Mode(kal_bool value,kal_bool is_SlewRateOn);
442extern kal_bool RTC_Get_GPIO_Input(void);
443extern void RTC_Set_GPIO_Input_Mode(RTC_GPIO_PULL_TYPE_enum PullType,RTC_GPIO_DRIVING_STRENGTH_enum PullDs,kal_bool is_SmithTrigger);
444extern void RTC_Set_GPIO_Mode(RTC_GPIO_MODE_enum Mode);
445#endif //#if defined(DRV_RTC_LOW_POWER_DETECT)
446
447// ============================================================
448// MoDIS parser skip start
449// Exported functions, used by driver level functions
450extern kal_bool isPWROnByRTC(void);
451extern void RTC_IRQOneShotEnable(kal_uint8 oneShotEN);
452extern void RTC_LISR(void);
453extern void RTC_init_(void (*RTC_TCCallback)(void),void (*RTC_ALCallback)(void));
454extern kal_bool RTC_is_MS_FirstPowerOn_(void);
455extern kal_bool RTC_is_config_valid(void);
456extern kal_bool RTC_is_Time_Valid(t_rtc *time);
457extern void RTC_GetTimeOnly(t_rtc *rtctime );
458extern kal_uint8 RTC_read_xosc_reg(void);
459extern void RTC_write_xosc_reg(kal_uint16 reg_value);
460extern void RTC_SaveTC_Time(t_rtc *rtctime);
461extern void RTC_set_First_PowerOn(kal_bool isFirstPowerOn);
462extern kal_bool RTC_Bootloader_PowerOn_(void);
463
464#if defined(DRV_RTC_HW_CALI)
465extern void RTC_wait_busy(void);
466extern void RTC_write_trigger(void);
467extern void RTC_write_trigger_wait(void);
468#endif /* defined(DRV_RTC_HW_CALI) */
469// MoDIS parser skip end
470
471// ============================================================
472// MoDIS parser skip start
473// Unknown functions, maybe previous owner forgot to delete
474extern void RTC_BBPUOpen(kal_bool open);
475extern void RTC_BBPWRUP_init(void);
476// MoDIS parser skip end
477
478#if defined(DRV_RTC_REG_COMM)
479//pwic may change pdn value during booting, save the original value of pdn1.
480extern kal_uint16 originalPDN1;
481extern kal_uint16 RTC_original_pnd1(void);
482#endif
483
484#if !defined(__FUE__) && !defined(__UBL__)
485extern kal_bool RTC_Set_Module_ILM_Info(RTC_REG_MODULE_ILM_INFO_T *Module_ilm_info);
486#endif
487
488#if !defined(DRV_RTC_OFF)
489#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
490#define DRV_RTC_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
491#define DRV_RTC_Reg(addr) DRV_DBG_Reg(addr)
492#define DRV_RTC_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
493#define DRV_RTC_Reg32(addr) DRV_DBG_Reg32(addr)
494#define DRV_RTC_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
495#define DRV_RTC_Reg8(addr) DRV_DBG_Reg8(addr)
496#define DRV_RTC_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
497#define DRV_RTC_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
498#define DRV_RTC_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
499#define DRV_RTC_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
500#define DRV_RTC_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
501#define DRV_RTC_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
502#define DRV_RTC_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
503#define DRV_RTC_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
504#define DRV_RTC_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
505#else
506#define DRV_RTC_WriteReg(addr,data) DRV_WriteReg(addr,data)
507#define DRV_RTC_Reg(addr) DRV_Reg(addr)
508#define DRV_RTC_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
509#define DRV_RTC_Reg32(addr) DRV_Reg32(addr)
510#define DRV_RTC_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
511#define DRV_RTC_Reg8(addr) DRV_Reg8(addr)
512#define DRV_RTC_ClearBits(addr,data) DRV_ClearBits(addr,data)
513#define DRV_RTC_SetBits(addr,data) DRV_SetBits(addr,data)
514#define DRV_RTC_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
515#define DRV_RTC_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
516#define DRV_RTC_SetBits32(addr,data) DRV_SetBits32(addr,data)
517#define DRV_RTC_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
518#define DRV_RTC_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
519#define DRV_RTC_SetBits8(addr,data) DRV_SetBits8(addr,data)
520#define DRV_RTC_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
521#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
522
523#else //!defined(DRV_RTC_OFF)
524
525#define DRV_RTC_WriteReg(addr,data)
526#define DRV_RTC_Reg(addr) drv_dummy_return()
527#define DRV_RTC_WriteReg32(addr,data)
528#define DRV_RTC_Reg32(addr) drv_dummy_return()
529#define DRV_RTC_WriteReg8(addr,data)
530#define DRV_RTC_Reg8(addr) drv_dummy_return()
531#define DRV_RTC_ClearBits(addr,data)
532#define DRV_RTC_SetBits(addr,data)
533#define DRV_RTC_SetData(addr, bitmask, value)
534#define DRV_RTC_ClearBits32(addr,data)
535#define DRV_RTC_SetBits32(addr,data)
536#define DRV_RTC_SetData32(addr, bitmask, value)
537#define DRV_RTC_ClearBits8(addr,data)
538#define DRV_RTC_SetBits8(addr,data)
539#define DRV_RTC_SetData8(addr, bitmask, value)
540
541#endif //!defined(DRV_RTC_OFF)
542
543#endif
544