| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * rwg_hw.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Maui_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file is intended for Random Waveform Generator (Enhaced PWM) driver. |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
| 58 | * removed! |
| 59 | * removed! |
| 60 | * removed! |
| 61 | * |
| 62 | * removed! |
| 63 | * removed! |
| 64 | * removed! |
| 65 | * |
| 66 | * removed! |
| 67 | * removed! |
| 68 | * removed! |
| 69 | * |
| 70 | * removed! |
| 71 | * removed! |
| 72 | * removed! |
| 73 | * |
| 74 | * removed! |
| 75 | * removed! |
| 76 | * removed! |
| 77 | * |
| 78 | * removed! |
| 79 | * removed! |
| 80 | * removed! |
| 81 | * |
| 82 | * removed! |
| 83 | * removed! |
| 84 | * removed! |
| 85 | * |
| 86 | * removed! |
| 87 | * removed! |
| 88 | * removed! |
| 89 | * |
| 90 | * removed! |
| 91 | * removed! |
| 92 | * removed! |
| 93 | * |
| 94 | *------------------------------------------------------------------------------ |
| 95 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 96 | *============================================================================ |
| 97 | ****************************************************************************/ |
| 98 | #ifndef RWG_HW_H |
| 99 | #define RWG_HW_H |
| 100 | #include "drv_features_pwm.h" |
| 101 | |
| 102 | /*add by RHR suggest Add*/ |
| 103 | #include "reg_base.h" |
| 104 | /*add by RHR suggest Add*/ |
| 105 | |
| 106 | #if defined(DRV_PWM_RWG) |
| 107 | #ifndef DRV_PWM_OFF |
| 108 | |
| 109 | #define PWM_ENABLE (PWM_base+0x0000) /* PWM Enable */ |
| 110 | #define PWM4_DELAY (PWM_base+0x0004) /* PWM4 Delay Duration */ |
| 111 | #define PWM5_DELAY (PWM_base+0x0008) /* PWM5 Delay Duration */ |
| 112 | #define PWM6_DELAY (PWM_base+0x000C) /* PWM6 Delay Duration */ |
| 113 | |
| 114 | #define PWM1_CON (PWM_base+0x0010) /* PWM1 Control */ |
| 115 | #define PWM1_HDURATION (PWM_base+0x0014) /* PWM1 High Duration */ |
| 116 | #define PWM1_LDURATION (PWM_base+0x0018) /* PWM1 Low Duration */ |
| 117 | #define PWM1_GDURATION (PWM_base+0x001C) /* PWM1 Guard Duration */ |
| 118 | #define PWM1_BUF0_BASE_ADDR (PWM_base+0x0020) /* PWM1 Buffer0 Base Address */ |
| 119 | #define PWM1_BUF0_SIZE (PWM_base+0x0024) /* PWM1 Buffer0 Size */ |
| 120 | #define PWM1_BUF1_BASE_ADDR (PWM_base+0x0028) /* PWM1 Buffer1 Base Address */ |
| 121 | #define PWM1_BUF1_SIZE (PWM_base+0x002C) /* PWM1 Buffer1 Size */ |
| 122 | #define PWM1_SEND_DATA0 (PWM_base+0x0030) /* PWM1 Send Data0 */ |
| 123 | #define PWM1_SEND_DATA1 (PWM_base+0x0034) /* PWM1 Send Data1 */ |
| 124 | #define PWM1_WAVE_NUM (PWM_base+0x0038) /* PWM1 Wave Number */ |
| 125 | #define PWM1_DATA_WIDTH (PWM_base+0x003C) /* PWM1 Data Width */ |
| 126 | #define PWM1_THRESH (PWM_base+0x0040) /* PWM1 Threshold */ |
| 127 | #define PWM1_SEND_WAVENUM (PWM_base+0x0044) /* PWM1 Send Wave Number */ |
| 128 | #define PWM1_VALID (PWM_base+0x0048) /* PWM1 Valid */ |
| 129 | |
| 130 | #define PWM2_CON (PWM_base+0x0050) /* PWM2 Control */ |
| 131 | #define PWM2_HDURATION (PWM_base+0x0054) /* PWM2 High Duration */ |
| 132 | #define PWM2_LDURATION (PWM_base+0x0058) /* PWM2 Low Duration */ |
| 133 | #define PWM2_GDURATION (PWM_base+0x005C) /* PWM2 Guard Duration */ |
| 134 | #define PWM2_BUF0_BASE_ADDR (PWM_base+0x0060) /* PWM2 Buffer0 Base Address */ |
| 135 | #define PWM2_BUF0_SIZE (PWM_base+0x0064) /* PWM2 Buffer0 Size */ |
| 136 | #define PWM2_BUF1_BASE_ADDR (PWM_base+0x0068) /* PWM2 Buffer1 Base Address */ |
| 137 | #define PWM2_BUF1_SIZE (PWM_base+0x006C) /* PWM2 Buffer1 Size */ |
| 138 | #define PWM2_SEND_DATA0 (PWM_base+0x0070) /* PWM2 Send Data0 */ |
| 139 | #define PWM2_SEND_DATA1 (PWM_base+0x0074) /* PWM2 Send Data1 */ |
| 140 | #define PWM2_WAVE_NUM (PWM_base+0x0078) /* PWM2 Wave Number */ |
| 141 | #define PWM2_DATA_WIDTH (PWM_base+0x007C) /* PWM2 Data Width */ |
| 142 | #define PWM2_THRESH (PWM_base+0x0080) /* PWM2 Threshold */ |
| 143 | #define PWM2_SEND_WAVENUM (PWM_base+0x0084) /* PWM2 Send Wave Number */ |
| 144 | #define PWM2_VALID (PWM_base+0x0088) /* PWM2 Valid */ |
| 145 | |
| 146 | #define PWM3_CON (PWM_base+0x0090) /* PWM3 Control */ |
| 147 | #define PWM3_HDURATION (PWM_base+0x0094) /* PWM3 High Duration */ |
| 148 | #define PWM3_LDURATION (PWM_base+0x0098) /* PWM3 Low Duration */ |
| 149 | #define PWM3_GDURATION (PWM_base+0x009C) /* PWM3 Guard Duration */ |
| 150 | #define PWM3_BUF0_BASE_ADDR (PWM_base+0x00A0) /* PWM3 Buffer0 Base Address */ |
| 151 | #define PWM3_BUF0_SIZE (PWM_base+0x00A4) /* PWM3 Buffer0 Size */ |
| 152 | #define PWM3_BUF1_BASE_ADDR (PWM_base+0x00A8) /* PWM3 Buffer1 Base Address */ |
| 153 | #define PWM3_BUF1_SIZE (PWM_base+0x00AC) /* PWM3 Buffer1 Size */ |
| 154 | #define PWM3_SEND_DATA0 (PWM_base+0x00B0) /* PWM3 Send Data0 */ |
| 155 | #define PWM3_SEND_DATA1 (PWM_base+0x00B4) /* PWM3 Send Data1 */ |
| 156 | #define PWM3_WAVE_NUM (PWM_base+0x00B8) /* PWM3 Wave Number */ |
| 157 | #define PWM3_DATA_WIDTH (PWM_base+0x00BC) /* PWM3 Data Width */ |
| 158 | #define PWM3_THRESH (PWM_base+0x00C0) /* PWM3 Threshold */ |
| 159 | #define PWM3_SEND_WAVENUM (PWM_base+0x00C4) /* PWM3 Send Wave Number */ |
| 160 | #define PWM3_VALID (PWM_base+0x00C8) /* PWM3 Valid */ |
| 161 | |
| 162 | #define PWM4_CON (PWM_base+0x00D0) /* PWM4 Control */ |
| 163 | #define PWM4_HDURATION (PWM_base+0x00D4) /* PWM4 High Duration */ |
| 164 | #define PWM4_LDURATION (PWM_base+0x00D8) /* PWM4 Low Duration */ |
| 165 | #define PWM4_GDURATION (PWM_base+0x00DC) /* PWM4 Guard Duration */ |
| 166 | #define PWM4_BUF0_BASE_ADDR (PWM_base+0x00E0) /* PWM4 Buffer0 Base Address */ |
| 167 | #define PWM4_BUF0_SIZE (PWM_base+0x00E4) /* PWM4 Buffer0 Size */ |
| 168 | #define PWM4_BUF1_BASE_ADDR (PWM_base+0x00E8) /* PWM4 Buffer1 Base Address */ |
| 169 | #define PWM4_BUF1_SIZE (PWM_base+0x00EC) /* PWM4 Buffer1 Size */ |
| 170 | #define PWM4_SEND_DATA0 (PWM_base+0x00F0) /* PWM4 Send Data0 */ |
| 171 | #define PWM4_SEND_DATA1 (PWM_base+0x00F4) /* PWM4 Send Data1 */ |
| 172 | #define PWM4_WAVE_NUM (PWM_base+0x00F8) /* PWM4 Wave Number */ |
| 173 | #define PWM4_SEND_WAVENUM (PWM_base+0x00FC) /* PWM4 Send Wave Number */ |
| 174 | #define PWM4_VALID (PWM_base+0x0100) /* PWM4 Valid */ |
| 175 | |
| 176 | #define PWM5_CON (PWM_base+0x0110) /* PWM5 Control */ |
| 177 | #define PWM5_HDURATION (PWM_base+0x0114) /* PWM5 High Duration */ |
| 178 | #define PWM5_LDURATION (PWM_base+0x0118) /* PWM5 Low Duration */ |
| 179 | #define PWM5_GDURATION (PWM_base+0x011C) /* PWM5 Guard Duration */ |
| 180 | #define PWM5_BUF0_BASE_ADDR (PWM_base+0x0120) /* PWM5 Buffer0 Base Address */ |
| 181 | #define PWM5_BUF0_SIZE (PWM_base+0x0124) /* PWM5 Buffer0 Size */ |
| 182 | #define PWM5_BUF1_BASE_ADDR (PWM_base+0x0128) /* PWM5 Buffer1 Base Address */ |
| 183 | #define PWM5_BUF1_SIZE (PWM_base+0x012C) /* PWM5 Buffer1 Size */ |
| 184 | #define PWM5_SEND_DATA0 (PWM_base+0x0130) /* PWM5 Send Data0 */ |
| 185 | #define PWM5_SEND_DATA1 (PWM_base+0x0134) /* PWM5 Send Data1 */ |
| 186 | #define PWM5_WAVE_NUM (PWM_base+0x0138) /* PWM5 Wave Number */ |
| 187 | #define PWM5_SEND_WAVENUM (PWM_base+0x013C) /* PWM5 Send Wave Number */ |
| 188 | #define PWM5_VALID (PWM_base+0x0140) /* PWM5 Valid */ |
| 189 | |
| 190 | #define PWM6_CON (PWM_base+0x0150) /* PWM6 Control */ |
| 191 | #define PWM6_HDURATION (PWM_base+0x0154) /* PWM6 High Duration */ |
| 192 | #define PWM6_LDURATION (PWM_base+0x0158) /* PWM6 Low Duration */ |
| 193 | #define PWM6_GDURATION (PWM_base+0x015C) /* PWM6 Guard Duration */ |
| 194 | #define PWM6_BUF0_BASE_ADDR (PWM_base+0x0160) /* PWM6 Buffer0 Base Address */ |
| 195 | #define PWM6_BUF0_SIZE (PWM_base+0x0164) /* PWM6 Buffer0 Size */ |
| 196 | #define PWM6_BUF1_BASE_ADDR (PWM_base+0x0168) /* PWM6 Buffer1 Base Address */ |
| 197 | #define PWM6_BUF1_SIZE (PWM_base+0x016C) /* PWM6 Buffer1 Size */ |
| 198 | #define PWM6_SEND_DATA0 (PWM_base+0x0170) /* PWM6 Send Data0 */ |
| 199 | #define PWM6_SEND_DATA1 (PWM_base+0x0174) /* PWM6 Send Data1 */ |
| 200 | #define PWM6_WAVE_NUM (PWM_base+0x0178) /* PWM6 Wave Number */ |
| 201 | #define PWM6_SEND_WAVENUM (PWM_base+0x017C) /* PWM6 Send Wave Number */ |
| 202 | #define PWM6_VALID (PWM_base+0x0180) /* PWM6 Valid */ |
| 203 | |
| 204 | #define PWM_INT_ENABLE (PWM_base+0x0190) /* PWM Interrupt Enable */ |
| 205 | #define PWM_INT_STATUS (PWM_base+0x0194) /* PWM Interrupt Status */ |
| 206 | #define PWM_INT_ACK (PWM_base+0x0198) /* PWM Interrupt Acknowledge */ |
| 207 | |
| 208 | /* PWM_ENABLE register */ |
| 209 | #define PWM_ENABLE_MASK 0x0000003F |
| 210 | #define PWM1_ENABLE_MASK 0x00000001 |
| 211 | #define PWM1_ENABLE 0x00000001 |
| 212 | #define PWM1_DISABLE 0x00000000 |
| 213 | #define PWM2_ENABLE_MASK 0x00000002 |
| 214 | #define PWM2_ENABLE 0x00000002 |
| 215 | #define PWM2_DISABLE 0x00000000 |
| 216 | #define PWM3_ENABLE_MASK 0x00000004 |
| 217 | #define PWM3_ENABLE 0x00000004 |
| 218 | #define PWM3_DISABLE 0x00000000 |
| 219 | #define PWM4_ENABLE_MASK 0x00000008 |
| 220 | #define PWM4_ENABLE 0x00000008 |
| 221 | #define PWM4_DISABLE 0x00000000 |
| 222 | #define PWM5_ENABLE_MASK 0x00000010 |
| 223 | #define PWM5_ENABLE 0x00000010 |
| 224 | #define PWM5_DISABLE 0x00000000 |
| 225 | #define PWM6_ENABLE_MASK 0x00000020 |
| 226 | #define PWM6_ENABLE 0x00000020 |
| 227 | #define PWM6_DISABLE 0x00000000 |
| 228 | #define PWM_SEQ_MODE_MASK 0x00000040 |
| 229 | #define PWM_SEQ_MODE_ON 0x00000040 |
| 230 | #define PWM_SEQ_MODE_OFF 0x00000000 |
| 231 | |
| 232 | /* PWM4, PWM5, PWM6 Delay Duration register */ |
| 233 | #define PWM_DELAY_DURATON_MASK 0x0000FFFF |
| 234 | #define PWM_DELAY_CLKSEL_MASK 0x00010000 |
| 235 | #define PWM_DELAY_CLKSEL_52M 0x00000000 |
| 236 | #define PWM_DELAY_CLKSEL_32K 0x00010000 |
| 237 | |
| 238 | /* PWM1~PWM6 Control registers */ |
| 239 | #define PWM_CON_CLKDIV_SHIFT 0 |
| 240 | #define PWM_CON_CLKDIV_MASK 0x00000007 |
| 241 | #define PWM_CON_CLKDIV_1 0x00000000 |
| 242 | #define PWM_CON_CLKDIV_2 0x00000001 |
| 243 | #define PWM_CON_CLKDIV_4 0x00000010 |
| 244 | #define PWM_CON_CLKDIV_8 0x00000011 |
| 245 | #define PWM_CON_CLKDIV_16 0x00000100 |
| 246 | #define PWM_CON_CLKDIV_32 0x00000101 |
| 247 | #define PWM_CON_CLKDIV_64 0x00000110 |
| 248 | #define PWM_CON_CLKDIV_128 0x00000111 |
| 249 | #define PWM_CON_CLKSEL_SHIFT 3 |
| 250 | #define PWM_CON_CLKSEL_MASK 0x00000008 |
| 251 | #define PWM_CON_CLKSEL_52M 0x00000000 |
| 252 | #define PWM_CON_CLKSEL_32K 0x00000008 |
| 253 | #define PWM_CON_FIXED_CLKMODE_SHIFT 4 |
| 254 | #define PWM_CON_FIXED_CLKMODE_MASK 0x00000010 |
| 255 | #define PWM_CON_FIXED_CLKMODE_0 0x00000000 |
| 256 | #define PWM_CON_FIXED_CLKMODE_1 0x00000010 |
| 257 | #define PWM_CON_SRCSEL_SHIFT 5 |
| 258 | #define PWM_CON_SRCSEL_MASK 0x00000020 |
| 259 | #define PWM_CON_SRCSEL_FIFO 0x00000000 |
| 260 | #define PWM_CON_SRCSEL_MEM 0x00000020 |
| 261 | #define PWM_CON_MODE_SHIFT 6 |
| 262 | #define PWM_CON_MODE_MASK 0x00000040 |
| 263 | #define PWM_CON_MODE_PERIODIC 0x00000000 |
| 264 | #define PWM_CON_MODE_RANDOM 0x00000040 |
| 265 | #define PWM_CON_IDLE_VALUE_SHIFT 7 |
| 266 | #define PWM_CON_IDLE_VALUE_MASK 0x00000080 |
| 267 | #define PWM_CON_IDLE_VALUE_0 0x00000000 |
| 268 | #define PWM_CON_IDLE_VALUE_1 0x00000080 |
| 269 | #define PWM_CON_GUARD_VALUE_SHIFT 8 |
| 270 | #define PWM_CON_GUARD_VALUE_MASK 0x00000100 |
| 271 | #define PWM_CON_GUARD_VALUE_0 0x00000000 |
| 272 | #define PWM_CON_GUARD_VALUE_1 0x00000100 |
| 273 | #define PWM_CON_STOP_BITPOS_SHIFT 9 |
| 274 | #define PWM_CON_STOP_BITPOS_MASK 0x00007E00 |
| 275 | #define PWM_CON_OLD_PWM_MODE_SHIFT 15 |
| 276 | #define PWM_CON_OLD_PWM_MODE_MASK 0x00008000 |
| 277 | #define PWM_CON_NEW_PWM_MODE 0x00000000 |
| 278 | #define PWM_CON_OLD_PWM_MODE 0x00008000 |
| 279 | |
| 280 | /* PWM1~PWM3 Data Width registers */ |
| 281 | #define PWM_DATA_WIDTH_MASK 0x00003FFF |
| 282 | |
| 283 | /* PWM1~PWM3 Threshold registers */ |
| 284 | #define PWM_THRESH_MASK 0x00003FFF |
| 285 | |
| 286 | /* PWM1~PWM6 Data Valid registers */ |
| 287 | #define PWM_DATA_VALID_MASK 0x0000000F |
| 288 | #define PWM_BUF0_VALID_MASK 0x00000001 |
| 289 | #define PWM_BUF0_INVALID 0x00000000 |
| 290 | #define PWM_BUF0_VALID 0x00000001 |
| 291 | #define PWM_BUF0_VALID_WEN_MASK 0x00000002 |
| 292 | #define PWM_BUF0_VALID_WDISABLE 0x00000000 |
| 293 | #define PWM_BUF0_VALID_WENABLE 0x00000002 |
| 294 | #define PWM_BUF1_VALID_MASK 0x00000004 |
| 295 | #define PWM_BUF1_INVALID 0x00000000 |
| 296 | #define PWM_BUF1_VALID 0x00000004 |
| 297 | #define PWM_BUF1_VALID_WEN_MASK 0x00000008 |
| 298 | #define PWM_BUF1_VALID_WDISABLE 0x00000000 |
| 299 | #define PWM_BUF1_VALID_WENABLE 0x00000008 |
| 300 | |
| 301 | /* PWM Interrupt Enable registers */ |
| 302 | #define PWM_INT_ENABLE_MASK 0x00000FFF |
| 303 | #define PWM1_INT_FINISH_EN_MASK 0x00000001 |
| 304 | #define PWM1_INT_FINISH_DISABLE 0x00000000 |
| 305 | #define PWM1_INT_FINISH_ENABLE 0x00000001 |
| 306 | #define PWM1_INT_UNDERFLOW_EN_MASK 0x00000002 |
| 307 | #define PWM1_INT_UNDERFLOW_DISABLE 0x00000000 |
| 308 | #define PWM1_INT_UNDERFLOW_ENABLE 0x00000002 |
| 309 | #define PWM2_INT_FINISH_EN_MASK 0x00000004 |
| 310 | #define PWM2_INT_FINISH_DISABLE 0x00000000 |
| 311 | #define PWM2_INT_FINISH_ENABLE 0x00000004 |
| 312 | #define PWM2_INT_UNDERFLOW_EN_MASK 0x00000008 |
| 313 | #define PWM2_INT_UNDERFLOW_DISABLE 0x00000000 |
| 314 | #define PWM2_INT_UNDERFLOW_ENABLE 0x00000008 |
| 315 | #define PWM3_INT_FINISH_EN_MASK 0x00000010 |
| 316 | #define PWM3_INT_FINISH_DISABLE 0x00000000 |
| 317 | #define PWM3_INT_FINISH_ENABLE 0x00000010 |
| 318 | #define PWM3_INT_UNDERFLOW_EN_MASK 0x00000020 |
| 319 | #define PWM3_INT_UNDERFLOW_DISABLE 0x00000000 |
| 320 | #define PWM3_INT_UNDERFLOW_ENABLE 0x00000020 |
| 321 | #define PWM4_INT_FINISH_EN_MASK 0x00000040 |
| 322 | #define PWM4_INT_FINISH_DISABLE 0x00000000 |
| 323 | #define PWM4_INT_FINISH_ENABLE 0x00000040 |
| 324 | #define PWM4_INT_UNDERFLOW_EN_MASK 0x00000080 |
| 325 | #define PWM4_INT_UNDERFLOW_DISABLE 0x00000000 |
| 326 | #define PWM4_INT_UNDERFLOW_ENABLE 0x00000080 |
| 327 | #define PWM5_INT_FINISH_EN_MASK 0x00000100 |
| 328 | #define PWM5_INT_FINISH_DISABLE 0x00000000 |
| 329 | #define PWM5_INT_FINISH_ENABLE 0x00000100 |
| 330 | #define PWM5_INT_UNDERFLOW_EN_MASK 0x00000200 |
| 331 | #define PWM5_INT_UNDERFLOW_DISABLE 0x00000000 |
| 332 | #define PWM5_INT_UNDERFLOW_ENABLE 0x00000200 |
| 333 | #define PWM6_INT_FINISH_EN_MASK 0x00000400 |
| 334 | #define PWM6_INT_FINISH_DISABLE 0x00000000 |
| 335 | #define PWM6_INT_FINISH_ENABLE 0x00000400 |
| 336 | #define PWM6_INT_UNDERFLOW_EN_MASK 0x00000800 |
| 337 | #define PWM6_INT_UNDERFLOW_DISABLE 0x00000000 |
| 338 | #define PWM6_INT_UNDERFLOW_ENABLE 0x00000800 |
| 339 | |
| 340 | /* PWM Interrupt Status registers */ |
| 341 | #define PWM_INT_STATUS_MASK 0x00000FFF |
| 342 | #define PWM1_INT_FINISH_EN_ST 0x00000001 |
| 343 | #define PWM1_INT_UNDERFLOW_EN_ST 0x00000002 |
| 344 | #define PWM2_INT_FINISH_EN_ST 0x00000004 |
| 345 | #define PWM2_INT_UNDERFLOW_EN_ST 0x00000008 |
| 346 | #define PWM3_INT_FINISH_EN_ST 0x00000010 |
| 347 | #define PWM3_INT_UNDERFLOW_EN_ST 0x00000020 |
| 348 | #define PWM4_INT_FINISH_EN_ST 0x00000040 |
| 349 | #define PWM4_INT_UNDERFLOW_EN_ST 0x00000080 |
| 350 | #define PWM5_INT_FINISH_EN_ST 0x00000100 |
| 351 | #define PWM5_INT_UNDERFLOW_EN_ST 0x00000200 |
| 352 | #define PWM6_INT_FINISH_EN_ST 0x00000400 |
| 353 | #define PWM6_INT_UNDERFLOW_EN_ST 0x00000800 |
| 354 | |
| 355 | /* PWM Interrupt ACK registers */ |
| 356 | #define PWM_INT_ACK_MASK 0x00000FFF |
| 357 | #define PWM1_INT_FINISH_ACK 0x00000001 |
| 358 | #define PWM1_INT_UNDERFLOW_ACK 0x00000002 |
| 359 | #define PWM2_INT_FINISH_ACK 0x00000004 |
| 360 | #define PWM2_INT_UNDERFLOW_ACK 0x00000008 |
| 361 | #define PWM3_INT_FINISH_ACK 0x00000010 |
| 362 | #define PWM3_INT_UNDERFLOW_ACK 0x00000020 |
| 363 | #define PWM4_INT_FINISH_ACK 0x00000040 |
| 364 | #define PWM4_INT_UNDERFLOW_ACK 0x00000080 |
| 365 | #define PWM5_INT_FINISH_ACK 0x00000100 |
| 366 | #define PWM5_INT_UNDERFLOW_ACK 0x00000200 |
| 367 | #define PWM6_INT_FINISH_ACK 0x00000400 |
| 368 | #define PWM6_INT_UNDERFLOW_ACK 0x00000800 |
| 369 | |
| 370 | #define PWM_TEST_SEL 0x100 |
| 371 | #endif // DRV_PWM_OFF |
| 372 | #endif /* defined(DRV_PWM_RWG) */ |
| 373 | |
| 374 | |
| 375 | #endif |
| 376 | |