Gitiles
Code Review Sign In
192.168.1.100 / T800_MD / 1eb8f53f94c145708b5ea2c6b9b96ea3d613f607 / . / mcu / driver / peripheral / inc / rwg_sw.h
blob: a8805712b1ba5754bc11e4d9c716a2a444722577 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * rwg_sw.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file is intended for Random Waveform Generator (Enhaced PWM) driver.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
59 * removed!
60 * removed!
61 *
62 * removed!
63 * removed!
64 * removed!
65 *
66 * removed!
67 * removed!
68 * removed!
69 *
70 * removed!
71 * removed!
72 * removed!
73 *
74 * removed!
75 * removed!
76 * removed!
77 *
78 * removed!
79 * removed!
80 * removed!
81 *
82 * removed!
83 * removed!
84 * removed!
85 *
86 * removed!
87 * removed!
88 * removed!
89 *
90 * removed!
91 * removed!
92 * removed!
93 *
94 * removed!
95 * removed!
96 * removed!
97 *
98 * removed!
99 * removed!
100 * removed!
101 *
102 * removed!
103 * removed!
104 * removed!
105 *
106 * removed!
107 * removed!
108 * removed!
109 *
110 * removed!
111 * removed!
112 * removed!
113 *
114 * removed!
115 * removed!
116 * removed!
117 *
118 * removed!
119 * removed!
120 * removed!
121 *
122 *------------------------------------------------------------------------------
123 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
124 *============================================================================
125 ****************************************************************************/
126#ifndef RWG_SW_H
127#define RWG_SW_H
128#include "kal_general_types.h"
129#include "drv_comm.h"
130#include "drv_features_pwm.h"
131#include "dcl.h"
132#if defined(DRV_PWM_RWG)
133/*PWM user mode ID*/
134typedef enum
135{
136 PWM_OWNER_UEM=0,
137 PWM_OWNER_AF,
138 PWM_OWNER_NONE=0xff
139}pwm_owner_e;
140
141/*Select PWM1 clock scale*/
142typedef enum
143{
144 PWM_CLK_DIV_NONE=0,
145 PWM_CLK_DIV_2=1,
146 PWM_CLK_DIV_4=2,
147 PWM_CLK_DIV_8=3,
148 PWM_CLK_DIV_16=4,
149 PWM_CLK_DIV_32=5,
150 PWM_CLK_DIV_64=6,
151 PWM_CLK_DIV_128=7
152}pwm_clk_div_e;
153
154/*Select PWMn clock*/
155typedef enum
156{
157 PWM_CLK_SEL_52M=0,
158 PWM_CLK_SEL_32K=1
159}pwm_clk_sel_e;
160
161/*PWM channel enumerate*/
162typedef enum
163{
164 PWM1=0,
165 PWM2,
166 PWM3,
167 PWM4,
168 PWM5,
169 PWM6,
170 PWM_COUNT
171}pwm_num_e;
172
173typedef enum
174{
175 PWM_SEQ_EN_PWM3=0x1,
176 PWM_SEQ_EN_PWM34=0x03,
177 PWM_SEQ_EN_PWM35=0x05,
178 PWM_SEQ_EN_PWM345=0x07,
179 PWM_SEQ_EN_PWM36=0x09,
180 PWM_SEQ_EN_PWM346=0x0b,
181 PWM_SEQ_EN_PWM356=0x0d,
182 PWM_SEQ_EN_PWM3456=0x0f
183} pwm_seq_en_cnt_e;
184
185typedef enum
186{
187 PWM_BUF_INVALID_NONE=0,
188 PWM_BUF_0_INVALID,
189 PWM_BUF_1_INVALID,
190 PWM_BUF_0_1_INVALID
191} pwm_buf_invalid_e;
192typedef void (*DCL_PWM_INIT)(void);
193typedef void (*DCL_PWM_CLK_INIT)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 clk_sel, kal_uint32 clk_div);
194typedef void (*DCL_PWM_START)(DCL_UINT8 owner, DCL_UINT32 pwm_num);
195typedef void (*DCL_PWM_STOP)(DCL_UINT8 owner, DCL_UINT32 pwm_num);
196typedef DCL_BOOL (*DCL_PWM_CONFIGURE)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 mode, void *para);
197typedef void (*DCL_PWM_SET_BUF_VALID)(kal_uint8 owner, kal_uint32 pwm_num,kal_uint32 *buf_addr, kal_uint16 buf_size, kal_bool is_buf0);
198typedef void (*DCL_PWM_SET_DELAY)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 clk_sel, kal_uint16 delay_cnt);
199typedef DCL_BOOL (*DCL_PWM_SEQ_OPEN)(kal_uint8 owner);
200typedef void (*DCL_PWM_SEQ_START)(kal_uint8 owner, kal_uint8 en_cnt);
201typedef void (*DCL_PWM_SEQ_STOP)(kal_uint8 owner);
202typedef DCL_BOOL (*DCL_PWM_SEQ_CLOSE)(kal_uint8 owner);
203typedef void (*DCL_PWM_CONFIG_OLD)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 freq, kal_uint8 duty);
204typedef DCL_UINT8 (*DCL_PWM_GETCURRENT_LEVEL)(DCL_UINT8 pwm_num);
205typedef DCL_UINT32(*DCL_PWM_GETCURRENT_FREQ)(DCL_UINT8 pwm_num);
206typedef DCL_UINT8 (*DCL_PWM_GETCURRENT_DUTY)(DCL_UINT8 pwm_num);
207typedef void (*DCL_PWM_TEST_SELECT)(DCL_BOOL sel);
208typedef kal_bool (*DCL_PWM_OPEN)(kal_uint8 owner, kal_uint32 pwm_num);
209typedef kal_bool (*DCL_PWM_CLOSE)(kal_uint8 owner, kal_uint32 pwm_num);
210typedef void (*DCL_PWM_CONFIG_FREQ_STEPS)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 freq, kal_uint16 steps);
211typedef void (*DCL_PWM_SET_DUTY)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint16 duty);
212typedef struct
213{
214 DCL_PWM_INIT pwmInit;
215 DCL_PWM_CLK_INIT pwmClkInit;
216 DCL_PWM_START pwmStart;
217 DCL_PWM_STOP pwmStop;
218 DCL_PWM_GETCURRENT_LEVEL pwmGetCurrent_level;
219 DCL_PWM_GETCURRENT_FREQ pwmGetCurrent_Freq;
220 DCL_PWM_GETCURRENT_DUTY pwmGetCurrent_Duty;
221 DCL_PWM_CONFIG_OLD pwmConfigOld;
222 DCL_PWM_TEST_SELECT pwmTestSelect;
223 DCL_PWM_CONFIGURE pwmConfigure;
224 DCL_PWM_OPEN pwmOpen;
225 DCL_PWM_CLOSE pwmClose;
226 DCL_PWM_SET_BUF_VALID pwmSetBufValid;
227 DCL_PWM_SET_DELAY pwmSetDelay;
228 DCL_PWM_SEQ_OPEN pwmSeqOpen;
229 DCL_PWM_SEQ_START pwmSeqStart;
230 DCL_PWM_SEQ_STOP pwmSeqStop;
231 DCL_PWM_SEQ_CLOSE pwmSeqClose;
232 DCL_PWM_CONFIG_FREQ_STEPS pwm_config_freq_steps;
233 DCL_PWM_SET_DUTY pwmSetDuty;
234}PWMDriver_t;
235
236extern void DCL_PWM_Start(kal_uint8 owner, kal_uint32 pwm_num);
237extern void DCL_PWM_Stop(kal_uint8 owner, kal_uint32 pwm_num);
238extern kal_uint8 DCL_PWM_GetCurrent_Level(kal_uint8 pwm_num);
239extern kal_uint8 DCL_PWM_GetCurrentDuty(kal_uint8 pwm_num);
240extern kal_uint32 DCL_PWM_GetCurrentFreq(kal_uint8 pwm_num);
241extern void DCL_PWM_ConfigOld(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 freq, kal_uint8 duty);
242
243extern void PWM_Init(void);
244extern kal_bool PWM_Open(kal_uint8 owner, kal_uint32 pwm_num);
245extern kal_bool PWM_Seq_Open(kal_uint8 owner);
246extern kal_bool PWM_Close(kal_uint8 owner, kal_uint32 pwm_num);
247extern kal_bool PWM_Seq_Close(kal_uint8 owner);
248extern void PWM_CLK_Init(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 clk_sel, kal_uint32 clk_div);
249extern kal_bool PWM_Configure(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 mode, void *para);
250extern void PWM_Start(kal_uint8 owner, kal_uint32 pwm_num);
251extern void PWM_Stop(kal_uint8 owner, kal_uint32 pwm_num);
252
253/* Below are for Sequence mode */
254extern void PMW_Set_Delay(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 clk_sel, kal_uint16 delay_cnt);
255extern void PWM_Seq_Start(kal_uint8 owner, kal_uint8 en_cnt);
256extern void PWM_Seq_Stop(kal_uint8 owner);
257//extern kal_uint32 PWM_Check_Buf_Valid(kal_uint32 pwm_num);
258extern void PWM_Set_Buf_Valid(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 *buf_addr, kal_uint16 buf_size, kal_bool is_buf0);
259
260/* Below are for OLD PWM backward compatibility. */
261// MoDIS parser skip start
262// The following APIs are implemented in other dummy API files
263extern void PWM1_Configure(kal_uint32 freq, kal_uint8 duty);
264extern void PWM2_Configure(kal_uint32 freq, kal_uint8 duty);
265// MoDIS parser skip end
266extern void PWM3_Configure(kal_uint32 freq, kal_uint8 duty);
267// MoDIS parser skip start
268// The following APIs are implemented in other dummy API files
269extern void PWM1_Start(void);
270extern void PWM2_Start(void);
271// MoDIS parser skip end
272extern void PWM3_Start(void);
273// MoDIS parser skip start
274// The following APIs are implemented in other dummy API files
275extern void PWM1_Stop(void);
276extern void PWM2_Stop(void);
277// MoDIS parser skip end
278extern void PWM3_Stop(void);
279
280// OLD PWM support for PWM port 4, 5, 6 begin
281extern void PWM4_Configure(kal_uint32 freq, kal_uint8 duty);
282extern void PWM5_Configure(kal_uint32 freq, kal_uint8 duty);
283extern void PWM6_Configure(kal_uint32 freq, kal_uint8 duty);
284extern void PWM4_Start(void);
285extern void PWM5_Start(void);
286extern void PWM6_Start(void);
287extern void PWM4_Stop(void);
288extern void PWM5_Stop(void);
289extern void PWM6_Stop(void);
290extern kal_uint8 PWM4_GetCurrentLevel(void);
291extern kal_uint8 PMW4_GetCurrentDuty(void);
292extern kal_uint32 PMW4_GetCurrentFreq(void);
293extern kal_uint8 PWM5_GetCurrentLevel(void);
294extern kal_uint8 PMW5_GetCurrentDuty(void);
295extern kal_uint32 PMW5_GetCurrentFreq(void);
296extern kal_uint8 PWM6_GetCurrentLevel(void);
297extern kal_uint8 PMW6_GetCurrentDuty(void);
298extern kal_uint32 PMW6_GetCurrentFreq(void);
299// OLD PWM support for PWM port 4, 5, 6 begin
300
301extern kal_uint8 PWM1_GetCurrentLevel(void);
302extern kal_uint8 PMW1_GetCurrentDuty(void);
303extern kal_uint32 PMW1_GetCurrentFreq(void);
304extern kal_uint8 PWM2_GetCurrentLevel(void);
305extern kal_uint8 PMW2_GetCurrentDuty(void);
306extern kal_uint32 PMW2_GetCurrentFreq(void);
307extern kal_uint8 PWM3_GetCurrentLevel(void);
308extern kal_uint32 PMW3_GetCurrentFreq(void);
309extern kal_uint8 PMW3_GetCurrentDuty(void);
310extern void PWM_Test_Select(kal_bool sel);
311#endif /* defined(DRV_PWM_RWG) */
312
313
314#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RWG_REG_DBG__)
315#define DRV_RWG_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
316#define DRV_RWG_Reg(addr) DRV_DBG_Reg(addr)
317#define DRV_RWG_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
318#define DRV_RWG_Reg32(addr) DRV_DBG_Reg32(addr)
319#define DRV_RWG_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
320#define DRV_RWG_Reg8(addr) DRV_DBG_Reg8(addr)
321#define DRV_RWG_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
322#define DRV_RWG_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
323#define DRV_RWG_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
324#define DRV_RWG_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
325#define DRV_RWG_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
326#define DRV_RWG_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
327#define DRV_RWG_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
328#define DRV_RWG_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
329#define DRV_RWG_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
330#else
331#define DRV_RWG_WriteReg(addr,data) DRV_WriteReg(addr,data)
332#define DRV_RWG_Reg(addr) DRV_Reg(addr)
333#define DRV_RWG_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
334#define DRV_RWG_Reg32(addr) DRV_Reg32(addr)
335#define DRV_RWG_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
336#define DRV_RWG_Reg8(addr) DRV_Reg8(addr)
337#define DRV_RWG_ClearBits(addr,data) DRV_ClearBits(addr,data)
338#define DRV_RWG_SetBits(addr,data) DRV_SetBits(addr,data)
339#define DRV_RWG_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
340#define DRV_RWG_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
341#define DRV_RWG_SetBits32(addr,data) DRV_SetBits32(addr,data)
342#define DRV_RWG_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
343#define DRV_RWG_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
344#define DRV_RWG_SetBits8(addr,data) DRV_SetBits8(addr,data)
345#define DRV_RWG_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
346#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RWG_REG_DBG__)
347#endif
348