mcu/interface/l1/cl1/common/cl1tstdpd.h

/*******************************************************************************
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/*******************************************************************************
*
* Filename:
* ---------
* cl1tstdpd.h
*
* Project:
* --------
*   MTXXXX Project
*
* Description:
* ------------
*   This file contains the log IQ functions.
*
* Author:
* -------
*
*
*==============================================================================
*             HISTORY
* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*------------------------------------------------------------------------------
 * removed!
 * removed!
 * removed!
*
 * removed!
 * removed!
*
*
*
*
*
*
*
*------------------------------------------------------------------------------
* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*==============================================================================
******************************************************************************/

#ifndef _CL1TST_DPD_H_
#define _CL1TST_DPD_H_

/*----------------------------------------------------------------------------
 Include Files
----------------------------------------------------------------------------*/
#include "kal_general_types.h"
#include "kal_public_defs.h"
#include "sysapi.h"

#define CL1TST_DPD_RETRY_LIMIT   	3
#define CL1TST_DPD_REF_TEMP_INDEX   4
#define CL1TST_DPD_FACTORY_DIFF  	12

/** define DPD state */
typedef enum
{
	CL1TST_DPD_FSM_IDLE = 0,
	CL1TST_DPD_FSM_TX_ON_TPC = 1,
	CL1TST_DPD_FSM_TPC = 2,
    CL1TST_DPD_FSM_TX_OFF = 3,
	CL1TST_DPD_FSM_GAIN_QUERY = 4,
	CL1TST_DPD_FSM_TX_OFF_WAIT = 5,
    CL1TST_DPD_FSM_NUM
} Cl1TstDpdStateE;

/* 8-level PA dc2dc for DPD calibration */
typedef enum
{
   CL1TST_DPD_PA_IDX0 = 0,
   CL1TST_DPD_PA_IDX1 = 1,
   CL1TST_DPD_PA_IDX2 = 2,
   CL1TST_DPD_PA_IDX3 = 3,
   CL1TST_DPD_PA_IDX4 = 4,
   CL1TST_DPD_PA_IDX5 = 5,
   CL1TST_DPD_PA_IDX6 = 6,
   CL1TST_DPD_PA_IDX7 = 7,
   CL1TST_DPD_PA_NULL = 0x7f	   
} Cl1TstDpdPaIdxE;

/* PA level-7 index */
typedef enum
{
   CL1TST_DPD_L7_IDX0 = 0,
   CL1TST_DPD_L7_IDX1 = 1,
   CL1TST_DPD_L7_NULL = 0x7f	   
} Cl1TstDpdL7IdxE;

/* define System time structure */
typedef struct Cl1DpdSysTimeTag
{
    /* Slot number */
    kal_uint8				Slot;

    /* half slot boundary system time */
    kal_uint32              Time;
} Cl1DpdSysTimeT;

/* define target time structure */
typedef struct Cl1DpdTargetTimeTag
{
    /* Slot number */
    kal_uint64				SupFram;

    /* system time */
    kal_uint32              SysTime;
} Cl1DpdTargetTimeT;

typedef struct
{
	kal_uint8				BandClass;
	kal_uint16				ChanNum;
} Cl1TstDpdFreqParaT;

/** This structure is updated by Algo driver */
typedef struct Cl1TstDpdAlgoUpdParaTag
{
	/** PA table index */
	kal_uint8  				PaTbIdx;

	/** 0: the first level 7
	    1: the second level level 7 */
	kal_uint8  				PaL7Idx;

	/** target power */
	kal_int16  				Peak;

	/** PA gain (include compensation) */
	kal_int16  				PaGain;

} Cl1TstDpdAlgoUpdParaT;

/** This structure is updated by RF driver */
typedef struct Cl1TstDpdRfdUpdParaTag
{
	/** target power */
	kal_int16  				Prf;

	/** PA gain (include compensation) */
	kal_int16  				PaGain;

	/** PA gain compensation */
	kal_int16  				PaGainComp;

	/** Coupler loss (include compensation) */
	kal_int16  				CouplerLoss;

} Cl1TstDpdRfdUpdParaT;

/** This structure is used to store UPC HW information in EVDO and 1xRTT mode. */
typedef struct Cl1TstDpdUpcInfoTag
{
	/** PGA gain */
	kal_int16  				PgaGain;

	/** DET path PGA gain */
	kal_int16  				DetGain;

    /** BB gain */
    kal_int16               BbGain;
} Cl1TstDpdUpcInfoT;

/** This structure is used to store Fail Info. */
typedef struct Cl1TstDpdFailInfoTag
{
	kal_uint8				Status; 

    /** Fail Rat */
	kal_uint8				CurRfMode;

    /** Fail band class */
	kal_uint8				CurBandClass;

    /** Fail channel number */
	kal_uint16				CurChanNum;
	
    /** Fail PA index */
	kal_uint16				CurPaIdx;

    /** Fail PA Gain */
	kal_int16				CurPaGain;
} Cl1TstDpdFailInfoT;

typedef struct
{
	CRfTestCmd_StartDpd_ReqInfo StartInfo;
	Cl1TstTxDpdStartPduT		StartPdu[CL1D_RF_BAND_CLASS_MAX];

	Cl1TstDpdStatusE      		DpdStatus;

	Cl1TstDpdStateE      		DpdState;

	Cl1DpdSysTimeT        		SysTime;

	SysSFrameTimeT              TarTime;

	Cl1TstDpdFreqParaT   		FreqPara;

	Cl1TstDpdAlgoUpdParaT 		AlgoUpdPara;

	Cl1TstDpdRfdUpdParaT 		RfdUpdPara;

	Cl1TstDpdUpcInfoT           UpcInfo;

	MMDPD_FAC_PGA_PARAM_T       *p_target_pga_table;

	/* The parameters for FXP and PA calibration result pointer */
	DPD_FXP_PARAM               FxpPara;

	/* To restore the calibrated PA gain result temperarily */
	kal_int16                   PaGain[CL1TST_DPD_FREQ_NUM][CL1TST_DPD_PA_NUM];      

	Cl1TstDpdFailInfoT          FailInfo;

	kal_int16                   TrValue;
	kal_uint8                   QueryCnt;
	kal_uint8                   TxOnFlag;
	kal_uint8                   TxOffCnt;

	kal_uint8                   query;

	kal_bool                    rf_tx_fec_wakeup_flag;

	kal_uint8                   fxp_retry_count;

    kal_uint16                  WaitSmples;
    kal_uint16                  DpdThUpper;
    kal_uint16                  TestMode;
    kal_uint16                  InitMode;
    kal_uint16                  TestCnt3;
    kal_uint32                  HSlotCnt;

} Cl1DpdDataT;

/*----------------------------------------------------------------------------
  global fucction
----------------------------------------------------------------------------*/
extern void Cl1TstDpdFacMain(void);

#endif /* _CL1TST_DPD_H_ */