| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
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| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
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| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * cl1_nvram_def.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * MAUI |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
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| 216 | * |
| 217 | *------------------------------------------------------------------------------ |
| 218 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 219 | *============================================================================ |
| 220 | ****************************************************************************/ |
| 221 | #ifndef __CL1_NVRAM_DEF_H__ |
| 222 | #define __CL1_NVRAM_DEF_H__ |
| 223 | |
| 224 | #if defined (__C2K_RAT__) || defined(__CL1_TASK_ENABLE__) |
| 225 | |
| 226 | #ifdef __cplusplus |
| 227 | extern "C" |
| 228 | { |
| 229 | #endif /* __cplusplus */ |
| 230 | |
| 231 | |
| 232 | #include "nvram_defs.h" |
| 233 | #include "nvram_enums.h" |
| 234 | |
| 235 | // LID Enums |
| 236 | #if defined(__MD93__) || defined(__MD95__) |
| 237 | typedef enum |
| 238 | { |
| 239 | NVRAM_EF_CL1_CUST_PARAM_LID = NVRAM_LID_GRP_CL1(0), |
| 240 | NVRAM_EF_CL1_CUST_BPI_CFG_LID = NVRAM_LID_GRP_CL1(1), |
| 241 | NVRAM_EF_CL1_MIPI_PARAM_LID = NVRAM_LID_GRP_CL1(2), |
| 242 | NVRAM_EF_CL1_MIPI_RX_EVENT_LID = NVRAM_LID_GRP_CL1(3), |
| 243 | NVRAM_EF_CL1_MIPI_RX_DATA_LID = NVRAM_LID_GRP_CL1(4), |
| 244 | NVRAM_EF_CL1_MIPI_TX_EVENT_LID = NVRAM_LID_GRP_CL1(5), |
| 245 | NVRAM_EF_CL1_MIPI_TX_DATA_LID = NVRAM_LID_GRP_CL1(6), |
| 246 | NVRAM_EF_CL1_MIPI_TPC_EVENT_LID = NVRAM_LID_GRP_CL1(7), |
| 247 | NVRAM_EF_CL1_MIPI_TPC_DATA_LID = NVRAM_LID_GRP_CL1(8), |
| 248 | NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_1XRTT_LID = NVRAM_LID_GRP_CL1(9), |
| 249 | NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_EVDO_LID = NVRAM_LID_GRP_CL1(10), |
| 250 | NVRAM_EF_CL1_MIPI_ETM_TX_EVENT_LID = NVRAM_LID_GRP_CL1(11), |
| 251 | NVRAM_EF_CL1_MIPI_ETM_TX_DATA_LID = NVRAM_LID_GRP_CL1(12), |
| 252 | NVRAM_EF_CL1_MIPI_ETM_TPC_EVENT_LID = NVRAM_LID_GRP_CL1(13), |
| 253 | NVRAM_EF_CL1_MIPI_ETM_TPC_DATA_LID = NVRAM_LID_GRP_CL1(14), |
| 254 | NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_1XRTT_LID = NVRAM_LID_GRP_CL1(15), |
| 255 | NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_EVDO_LID = NVRAM_LID_GRP_CL1(16), |
| 256 | |
| 257 | /*** TAS ***//*VAR*/ |
| 258 | NVRAM_EF_CL1_CUST_TAS_FEATURE_LID = NVRAM_LID_GRP_CL1(17), |
| 259 | NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_LID = NVRAM_LID_GRP_CL1(18), |
| 260 | NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_LID = NVRAM_LID_GRP_CL1(19), |
| 261 | NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_LID = NVRAM_LID_GRP_CL1(20), |
| 262 | NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_LID = NVRAM_LID_GRP_CL1(21), |
| 263 | NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_LID = NVRAM_LID_GRP_CL1(22), |
| 264 | NVRAM_EF_CL1_CUST_TUNER_LID = NVRAM_LID_GRP_CL1(23), |
| 265 | /*** TAS ***//*ARRAY*/ |
| 266 | NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_LID = NVRAM_LID_GRP_CL1(24), |
| 267 | NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_LID = NVRAM_LID_GRP_CL1(25), |
| 268 | NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_LID = NVRAM_LID_GRP_CL1(26), |
| 269 | NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_LID = NVRAM_LID_GRP_CL1(27), |
| 270 | NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_LID = NVRAM_LID_GRP_CL1(28), |
| 271 | NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_LID = NVRAM_LID_GRP_CL1(29), |
| 272 | NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_LID = NVRAM_LID_GRP_CL1(30), |
| 273 | NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_LID = NVRAM_LID_GRP_CL1(31), |
| 274 | |
| 275 | NVRAM_EF_CL1_CUST_TAS_CFG_LID = NVRAM_LID_GRP_CL1(32), |
| 276 | NVRAM_EF_CL1_CUST_ELNA_CFG_LID = NVRAM_LID_GRP_CL1(33), |
| 277 | NVRAM_EF_CL1_CUST_ELNA_EVENT_LID = NVRAM_LID_GRP_CL1(34), |
| 278 | NVRAM_EF_CL1_CUST_ELNA_DATA_LID = NVRAM_LID_GRP_CL1(35), |
| 279 | |
| 280 | NVRAM_EF_CL1_TX_POWER_BACK_OFF_LID = NVRAM_LID_GRP_CL1(36), |
| 281 | NVRAM_EF_CL1_TX_POWER_OFFSET_LID = NVRAM_LID_GRP_CL1(37), |
| 282 | |
| 283 | NVRAM_EF_CL1_TAS_TST_CONFIG_LID = NVRAM_LID_GRP_CL1(38), |
| 284 | NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_LID = NVRAM_LID_GRP_CL1(39), |
| 285 | NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_LID = NVRAM_LID_GRP_CL1(40), |
| 286 | NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_LID = NVRAM_LID_GRP_CL1(41), |
| 287 | |
| 288 | NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_LID = NVRAM_LID_GRP_CL1(42), |
| 289 | NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_LID = NVRAM_LID_GRP_CL1(43), |
| 290 | |
| 291 | NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_LID = NVRAM_LID_GRP_CL1(44), |
| 292 | NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_LID = NVRAM_LID_GRP_CL1(45), |
| 293 | NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_LID = NVRAM_LID_GRP_CL1(46), |
| 294 | NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_LID = NVRAM_LID_GRP_CL1(47), |
| 295 | |
| 296 | NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_1XRTT_LID = NVRAM_LID_GRP_CL1(48), |
| 297 | NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_EVDO_LID = NVRAM_LID_GRP_CL1(49), |
| 298 | |
| 299 | NVRAM_EF_CL1_DPD_COMMON_CTRL_LID = NVRAM_LID_GRP_CL1(50), |
| 300 | NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_LID = NVRAM_LID_GRP_CL1(51), |
| 301 | |
| 302 | NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_LID = NVRAM_LID_GRP_CL1(52), |
| 303 | NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_LID = NVRAM_LID_GRP_CL1(53), |
| 304 | |
| 305 | NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_LID = NVRAM_LID_GRP_CL1(54), |
| 306 | |
| 307 | /* WARNING: DO NOT modify the last LID */ |
| 308 | NVRAM_EF_CL1_LAST_LID = NVRAM_LID_GRP_CL1(255) |
| 309 | }nvram_lid_cl1_enum; |
| 310 | |
| 311 | // VERNO |
| 312 | |
| 313 | #define NVRAM_EF_CL1_CUST_PARAM_LID_VERNO "001" |
| 314 | #define NVRAM_EF_CL1_CUST_BPI_CFG_LID_VERNO "001" |
| 315 | #define NVRAM_EF_CL1_MIPI_PARAM_LID_VERNO "001" |
| 316 | #define NVRAM_EF_CL1_MIPI_RX_EVENT_LID_VERNO "001" |
| 317 | #define NVRAM_EF_CL1_MIPI_RX_DATA_LID_VERNO "001" |
| 318 | #define NVRAM_EF_CL1_MIPI_TX_EVENT_LID_VERNO "001" |
| 319 | #define NVRAM_EF_CL1_MIPI_TX_DATA_LID_VERNO "001" |
| 320 | #define NVRAM_EF_CL1_MIPI_TPC_EVENT_LID_VERNO "001" |
| 321 | #define NVRAM_EF_CL1_MIPI_TPC_DATA_LID_VERNO "001" |
| 322 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_1XRTT_LID_VERNO "001" |
| 323 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_EVDO_LID_VERNO "001" |
| 324 | #define NVRAM_EF_CL1_MIPI_ETM_TX_EVENT_LID_VERNO "001" |
| 325 | #define NVRAM_EF_CL1_MIPI_ETM_TX_DATA_LID_VERNO "001" |
| 326 | #define NVRAM_EF_CL1_MIPI_ETM_TPC_EVENT_LID_VERNO "001" |
| 327 | #define NVRAM_EF_CL1_MIPI_ETM_TPC_DATA_LID_VERNO "001" |
| 328 | #define NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_1XRTT_LID_VERNO "001" |
| 329 | #define NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_EVDO_LID_VERNO "001" |
| 330 | /*** TAS ***//*VAR*/ |
| 331 | #define NVRAM_EF_CL1_CUST_TAS_FEATURE_LID_VERNO "001" |
| 332 | #define NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_LID_VERNO "001" |
| 333 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_LID_VERNO "001" |
| 334 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_LID_VERNO "001" |
| 335 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_LID_VERNO "001" |
| 336 | #define NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_LID_VERNO "001" |
| 337 | #define NVRAM_EF_CL1_CUST_TUNER_LID_VERNO "001" |
| 338 | /*** TAS ***//*ARRAY*/ |
| 339 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_LID_VERNO "001" |
| 340 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_LID_VERNO "001" |
| 341 | |
| 342 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_LID_VERNO "001" |
| 343 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_LID_VERNO "001" |
| 344 | |
| 345 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_LID_VERNO "001" |
| 346 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_LID_VERNO "001" |
| 347 | |
| 348 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_LID_VERNO "001" |
| 349 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_LID_VERNO "001" |
| 350 | |
| 351 | /*ELNA*/ |
| 352 | #define NVRAM_EF_CL1_CUST_ELNA_CFG_LID_VERNO "002" |
| 353 | |
| 354 | #define NVRAM_EF_CL1_TX_POWER_BACK_OFF_LID_VERNO "001" |
| 355 | #define NVRAM_EF_CL1_TX_POWER_OFFSET_LID_VERNO "002" |
| 356 | #define NVRAM_EF_CL1_TAS_TST_CONFIG_LID_VERNO "001" |
| 357 | /*DAT*/ |
| 358 | #define NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_LID_VERNO "001" |
| 359 | #define NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_LID_VERNO "001" |
| 360 | #define NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_LID_VERNO "001" |
| 361 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_LID_VERNO "001" |
| 362 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_LID_VERNO "001" |
| 363 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_LID_VERNO "001" |
| 364 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_LID_VERNO "001" |
| 365 | |
| 366 | #define NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_LID_VERNO "001" |
| 367 | #define NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_LID_VERNO "000" |
| 368 | |
| 369 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_1XRTT_LID_VERNO "001" |
| 370 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_EVDO_LID_VERNO "001" |
| 371 | /*DPD*/ |
| 372 | #define NVRAM_EF_CL1_DPD_COMMON_CTRL_LID_VERNO "001" |
| 373 | #define NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_LID_VERNO "001" |
| 374 | #define NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_LID_VERNO "001" |
| 375 | #define NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_LID_VERNO "001" |
| 376 | |
| 377 | #define NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_LID_VERNO "001" |
| 378 | |
| 379 | |
| 380 | // HASH Key |
| 381 | #define NVRAM_EF_CL1_CUST_PARAM_LID_HASH 0xF475E6A9 |
| 382 | #define NVRAM_EF_CL1_CUST_BPI_CFG_LID_HASH 0xB2C516ED |
| 383 | #define NVRAM_EF_CL1_MIPI_PARAM_LID_HASH 0x3091DE51 |
| 384 | #define NVRAM_EF_CL1_MIPI_RX_EVENT_LID_HASH 0xAB5A1B37 |
| 385 | #define NVRAM_EF_CL1_MIPI_RX_DATA_LID_HASH 0xFE01DAA0 |
| 386 | #define NVRAM_EF_CL1_MIPI_TX_EVENT_LID_HASH 0x05B8A148 |
| 387 | #define NVRAM_EF_CL1_MIPI_TX_DATA_LID_HASH 0xD452BEB2 |
| 388 | #define NVRAM_EF_CL1_MIPI_TPC_EVENT_LID_HASH 0x8C014C59 |
| 389 | #define NVRAM_EF_CL1_MIPI_TPC_DATA_LID_HASH 0xD5544B68 |
| 390 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_1XRTT_LID_HASH 0x1FFCCAC7 |
| 391 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_EVDO_LID_HASH 0x526FBA87 |
| 392 | #define NVRAM_EF_CL1_MIPI_ETM_TX_EVENT_LID_HASH 0x48B34501 |
| 393 | #define NVRAM_EF_CL1_MIPI_ETM_TX_DATA_LID_HASH 0x2C2829DA |
| 394 | #define NVRAM_EF_CL1_MIPI_ETM_TPC_EVENT_LID_HASH 0x57EEAEFF |
| 395 | #define NVRAM_EF_CL1_MIPI_ETM_TPC_DATA_LID_HASH 0xDAEAF52B |
| 396 | #define NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_1XRTT_LID_HASH 0x4A8B4F11 |
| 397 | #define NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_EVDO_LID_HASH 0x8E8A6003 |
| 398 | #define NVRAM_EF_CL1_CUST_TAS_FEATURE_LID_HASH 0x6545A7B7 |
| 399 | #define NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_LID_HASH 0x0C0D41AE |
| 400 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_LID_HASH 0xD1F8B014 |
| 401 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_LID_HASH 0x02E56E41 |
| 402 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_LID_HASH 0x89B819D5 |
| 403 | #define NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_LID_HASH 0xF7B23627 |
| 404 | #define NVRAM_EF_CL1_CUST_TUNER_LID_HASH 0xF7643065 |
| 405 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_LID_HASH 0xF482A4A7 |
| 406 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_LID_HASH 0xC606AB82 |
| 407 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_LID_HASH 0xC67DE834 |
| 408 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_LID_HASH 0xD2EF7F2A |
| 409 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_LID_HASH 0x9A77EAD6 |
| 410 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_LID_HASH 0x800464BD |
| 411 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_LID_HASH 0xF281DF2A |
| 412 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_LID_HASH 0x96DB1104 |
| 413 | #define NVRAM_EF_CL1_CUST_TAS_CFG_LID_HASH 0xFDB89A5F |
| 414 | #define NVRAM_EF_CL1_CUST_ELNA_CFG_LID_HASH 0x37F8C00D |
| 415 | #define NVRAM_EF_CL1_TX_POWER_BACK_OFF_LID_HASH 0x46469AA7 |
| 416 | #define NVRAM_EF_CL1_TX_POWER_OFFSET_LID_HASH 0x5C1CCAC6 |
| 417 | #define NVRAM_EF_CL1_TAS_TST_CONFIG_LID_HASH 0x21DDFFEE |
| 418 | #define NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_LID_HASH 0x352F8E5B |
| 419 | #define NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_LID_HASH 0xF5F9E9AB |
| 420 | #define NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_LID_HASH 0xD8F049DF |
| 421 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_LID_HASH 0x2A65CC8E |
| 422 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_LID_HASH 0x6B15CB8C |
| 423 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_LID_HASH 0x533CBF0F |
| 424 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_LID_HASH 0xCBBFD5CE |
| 425 | #define NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_LID_HASH 0xEC582023 |
| 426 | #define NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_LID_HASH 0xE776D29E |
| 427 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_1XRTT_LID_HASH 0x0DCDD37B |
| 428 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_EVDO_LID_HASH 0x3C69190B |
| 429 | #define NVRAM_EF_CL1_DPD_COMMON_CTRL_LID_HASH 0xB8B7A6FD |
| 430 | #define NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_LID_HASH 0x17CEFFA5 |
| 431 | #define NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_LID_HASH 0xC2F0E2D8 |
| 432 | #define NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_LID_HASH 0x5A919B54 |
| 433 | #define NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_LID_HASH 0xF4C1D4BD |
| 434 | |
| 435 | /*this tx power offset adjustment is set for verizon case*/ |
| 436 | #include "cl1_rf_public.h" |
| 437 | typedef struct |
| 438 | { |
| 439 | kal_uint16 accTxPwrOffset[SYS_BAND_CLASS_MAX];/*tx power offset in dB of band0-20, access tx power += accTxPwrOffset[band], default 0*/ |
| 440 | kal_uint16 maxPwrbackoff[SYS_BAND_CLASS_MAX];/*access max power backoff of band0-20, max power -= maxPwrbackoff[band], default 0*/ |
| 441 | }CL1_L1D_TX_POWER_OFFSET_T; |
| 442 | // Size and Total |
| 443 | |
| 444 | #define NVRAM_EF_CL1_CUST_PARAM_SIZE sizeof(CL1D_RF_CUST_PARAM_T) |
| 445 | #define NVRAM_EF_CL1_CUST_BPI_CFG_SIZE sizeof(CL1D_RF_CUST_BPI_CFG_T) |
| 446 | #define NVRAM_EF_CL1_MIPI_PARAM_SIZE sizeof(CL1D_RF_MIPI_PARAM_T) |
| 447 | #define NVRAM_EF_CL1_MIPI_RX_EVENT_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_RX_EVENT_MAX_NUM |
| 448 | #define NVRAM_EF_CL1_MIPI_RX_DATA_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T) * MIPI_RX_DATA_MAX_NUM |
| 449 | #define NVRAM_EF_CL1_MIPI_TX_EVENT_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_TX_EVENT_MAX_NUM |
| 450 | #define NVRAM_EF_CL1_MIPI_TX_DATA_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T) * MIPI_TX_DATA_MAX_NUM |
| 451 | #define NVRAM_EF_CL1_MIPI_TPC_EVENT_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_TPC_EVENT_MAX_NUM |
| 452 | #define NVRAM_EF_CL1_MIPI_TPC_DATA_SIZE sizeof(CL1D_RF_MIPI_DATA_TABLE_T) * MIPI_TPC_DATA_MAX_NUM |
| 453 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_1XRTT_SIZE sizeof(CL1D_RF_TPC_SECTION_TABLE_T) * MIPI_PA_SECTION_DATA_MAX_NUM |
| 454 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_EVDO_SIZE sizeof(CL1D_RF_TPC_SECTION_TABLE_T) * MIPI_PA_SECTION_DATA_MAX_NUM |
| 455 | #define NVRAM_EF_CL1_MIPI_ETM_TX_EVENT_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_ETM_TX_EVENT_MAX_NUM |
| 456 | #define NVRAM_EF_CL1_MIPI_ETM_TX_DATA_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T) * MIPI_ETM_TX_DATA_MAX_NUM |
| 457 | #define NVRAM_EF_CL1_MIPI_ETM_TPC_EVENT_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_ETM_TPC_EVENT_MAX_NUM |
| 458 | #define NVRAM_EF_CL1_MIPI_ETM_TPC_DATA_SIZE sizeof(CL1D_RF_MIPI_DATA_TABLE_T) * MIPI_ETM_TPC_DATA_MAX_NUM |
| 459 | #define NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_1XRTT_SIZE sizeof(CL1D_RF_TPC_SECTION_TABLE_T) * MIPI_ETM_PA_SECTION_DATA_MAX_NUM |
| 460 | #define NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_EVDO_SIZE sizeof(CL1D_RF_TPC_SECTION_TABLE_T) * MIPI_ETM_PA_SECTION_DATA_MAX_NUM |
| 461 | |
| 462 | /*** TAS ***//*VAR*/ |
| 463 | #define NVRAM_EF_CL1_CUST_TAS_FEATURE_SIZE sizeof(C2K_CUSTOM_TAS_FEATURE_BY_RAT_T) |
| 464 | #define NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_SIZE sizeof(C2K_CUSTOM_TAS_FE_ROUTE_DATABASE_T) |
| 465 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_SIZE sizeof(C2K_CUSTOM_TAS_FE_CAT_A_T) |
| 466 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_SIZE sizeof(C2K_CUSTOM_TAS_FE_CAT_B_T) |
| 467 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_SIZE sizeof(C2K_CUSTOM_TAS_FE_CAT_C_T) |
| 468 | #define NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_SIZE sizeof(C2K_CUSTOM_TUNER_FE_ROUTE_TABLE) |
| 469 | #define NVRAM_EF_CL1_CUST_TUNER_SIZE sizeof(C2K_CUSTOM_TUNER_BAND_T) |
| 470 | #define NVRAM_EF_CL1_TAS_TST_CONFIG_SZIE sizeof(CL1D_RF_TAS_TST_CONFIG_T) |
| 471 | #define NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_SIZE sizeof(CL1_L1D_TX_POWER_OFFSET_T) |
| 472 | /*** TAS ***//*ARRAY*/ |
| 473 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_TAS_EVENT_MAX_NUM |
| 474 | |
| 475 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T) * MIPI_TAS_DATA_MAX_NUM |
| 476 | |
| 477 | |
| 478 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_TAS_EVENT_MAX_NUM |
| 479 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T) * MIPI_TAS_DATA_MAX_NUM |
| 480 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_TAS_EVENT_MAX_NUM |
| 481 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T) * MIPI_TAS_DATA_MAX_NUM |
| 482 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_TAS_EVENT_MAX_NUM |
| 483 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T) * MIPI_TAS_DATA_MAX_NUM |
| 484 | |
| 485 | /*ELNA*/ |
| 486 | #define NVRAM_EF_CL1_CUST_ELNA_CFG_SIZE sizeof(CL1D_RF_CUST_ELNA_CFG_T) |
| 487 | /*TX POWER*/ |
| 488 | #define NVRAM_EF_CL1_TX_POWER_BACK_OFF_SIZE sizeof(CL1D_RF_TX_POWER_BACK_OFF_T) |
| 489 | #define NVRAM_EF_CL1_TX_POWER_OFFSET_SIZE sizeof(CL1D_RF_SAR_TX_POWER_OFFSET_T) |
| 490 | #if IS_C2K_DAT_RFD_CTRL_EN |
| 491 | /*DAT*/ |
| 492 | #define NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_SIZE sizeof(CL1D_RF_DAT_FE_ROUTE_DATABASE_T) |
| 493 | #define NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_SIZE sizeof(CL1D_RF_DAT_FE_CAT_A_T) |
| 494 | #define NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_SIZE sizeof(CL1D_RF_DAT_FE_CAT_B_T) |
| 495 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T)*MIPI_DAT_EVENT_MAX_NUM |
| 496 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T)*MIPI_DAT_DATA_MAX_NUM |
| 497 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T)*MIPI_DAT_EVENT_MAX_NUM |
| 498 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T)*MIPI_DAT_DATA_MAX_NUM |
| 499 | #endif |
| 500 | #define NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_SIZE sizeof(CL1D_RF_SAR_TX_POWER_OFFSET_T) |
| 501 | /*TX PA Section DPD*/ |
| 502 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_1XRTT_SIZE sizeof(CL1D_RF_TPC_SECTION_TABLE_T) * MIPI_PA_SECTION_DATA_MAX_NUM |
| 503 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_EVDO_SIZE sizeof(CL1D_RF_TPC_SECTION_TABLE_T) * MIPI_PA_SECTION_DATA_MAX_NUM |
| 504 | |
| 505 | #define NVRAM_EF_CL1_DPD_COMMON_CTRL_SIZE sizeof(CL1D_RF_DPD_COMMON_CTRL_T) |
| 506 | #define NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_SIZE sizeof(CL1D_RF_PCFE_DPD_OTFC_CUSTOM_PARA_T) |
| 507 | #define NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_SIZE sizeof(C2K_CUSTOM_ANT_FE_ROUTE_DATABASE_T) |
| 508 | #define NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_SIZE sizeof(C2K_CUSTOM_UTAS_ALGORITHM_PARAMETER_T) |
| 509 | #define NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_SIZE sizeof(C2K_CUSTOM_DAT_ANT_TUNER_ROUTE_DATABASE_T) |
| 510 | |
| 511 | #define NVRAM_EF_CL1_CUST_PARAM_TOTAL 1 |
| 512 | #define NVRAM_EF_CL1_CUST_BPI_CFG_TOTAL MAX_BAND_NUM |
| 513 | #define NVRAM_EF_CL1_MIPI_PARAM_TOTAL 1 |
| 514 | #define NVRAM_EF_CL1_MIPI_RX_EVENT_TOTAL MAX_BAND_NUM |
| 515 | #define NVRAM_EF_CL1_MIPI_RX_DATA_TOTAL MAX_BAND_NUM |
| 516 | #define NVRAM_EF_CL1_MIPI_TX_EVENT_TOTAL MAX_BAND_NUM |
| 517 | #define NVRAM_EF_CL1_MIPI_TX_DATA_TOTAL MAX_BAND_NUM |
| 518 | #define NVRAM_EF_CL1_MIPI_TPC_EVENT_TOTAL MAX_BAND_NUM |
| 519 | #define NVRAM_EF_CL1_MIPI_TPC_DATA_TOTAL MAX_BAND_NUM |
| 520 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_1XRTT_TOTAL MAX_BAND_NUM |
| 521 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_EVDO_TOTAL MAX_BAND_NUM |
| 522 | #define NVRAM_EF_CL1_MIPI_ETM_TX_EVENT_TOTAL MAX_BAND_NUM |
| 523 | #define NVRAM_EF_CL1_MIPI_ETM_TX_DATA_TOTAL MAX_BAND_NUM |
| 524 | #define NVRAM_EF_CL1_MIPI_ETM_TPC_EVENT_TOTAL MAX_BAND_NUM |
| 525 | #define NVRAM_EF_CL1_MIPI_ETM_TPC_DATA_TOTAL MAX_BAND_NUM |
| 526 | #define NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_1XRTT_TOTAL MAX_BAND_NUM |
| 527 | #define NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_EVDO_TOTAL MAX_BAND_NUM |
| 528 | |
| 529 | /*** TAS ***//*VAR*/ |
| 530 | #define NVRAM_EF_CL1_CUST_TAS_FEATURE_TOTAL 1 |
| 531 | #define NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_TOTAL 1 |
| 532 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_TOTAL 1 |
| 533 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_TOTAL 1 |
| 534 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_TOTAL 1 |
| 535 | #define NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_TOTAL 1 |
| 536 | #define NVRAM_EF_CL1_CUST_TUNER_TOTAL MAX_BAND_NUM |
| 537 | |
| 538 | /*** TAS ***//*ARRAY*/ |
| 539 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_TOTAL MAX_BAND_NUM |
| 540 | |
| 541 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_TOTAL MAX_BAND_NUM |
| 542 | |
| 543 | #define NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_TOTAL 1 |
| 544 | |
| 545 | |
| 546 | |
| 547 | |
| 548 | |
| 549 | |
| 550 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_TOTAL MAX_Route_NUM |
| 551 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_TOTAL MAX_Route_NUM |
| 552 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_TOTAL MAX_Route_NUM |
| 553 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_TOTAL MAX_Route_NUM |
| 554 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_TOTAL MAX_Route_NUM |
| 555 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_TOTAL MAX_Route_NUM |
| 556 | |
| 557 | /*ELNA*/ |
| 558 | #define NVRAM_EF_CL1_CUST_ELNA_CFG_TOTAL 1 |
| 559 | |
| 560 | /*TX POWER*/ |
| 561 | #define NVRAM_EF_CL1_TX_POWER_BACK_OFF_TOTAL MAX_BAND_NUM |
| 562 | #define NVRAM_EF_CL1_TX_POWER_OFFSET_TOTAL MAX_BAND_NUM |
| 563 | #define NVRAM_EF_CL1_TAS_TST_CFG_TOTAL 1 |
| 564 | /*DAT*/ |
| 565 | #define NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_TOTAL 1 |
| 566 | #define NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_TOTAL 1 |
| 567 | #define NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_TOTAL 1 |
| 568 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_TOTAL MAX_DAT_CAT_A_Route_NUM |
| 569 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_TOTAL MAX_DAT_CAT_A_Route_NUM |
| 570 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_TOTAL MAX_DAT_CAT_B_Route_NUM |
| 571 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_TOTAL MAX_DAT_CAT_B_Route_NUM |
| 572 | |
| 573 | #define NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_TOTAL MAX_BAND_NUM |
| 574 | #define NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_TOTAL 1 |
| 575 | /*TX DPD PA Section*/ |
| 576 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_1XRTT_TOTAL MAX_BAND_NUM |
| 577 | #define NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_EVDO_TOTAL MAX_BAND_NUM |
| 578 | #define NVRAM_EF_CL1_DPD_COMMON_CTRL_TOTAL MAX_BAND_NUM |
| 579 | #define NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_TOTAL 1 |
| 580 | #define NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_TOTAL 1 |
| 581 | #define NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_TOTAL 1 |
| 582 | |
| 583 | #undef NVRAM_ITEM_RF_CUST |
| 584 | #undef NVRAM_ITEM_MIPI |
| 585 | #undef NVRAM_ITEM_RF_CAL |
| 586 | #undef NVRAM_ITEM_RF_POC |
| 587 | #undef NVRAM_ITEM_RF_TAS_VAR |
| 588 | #undef NVRAM_ITEM_RF_TAS_ARRAY |
| 589 | #undef NVRAM_ITEM_ELNA_VAR |
| 590 | #undef NVRAM_ITEM_TX_POWER_VAR |
| 591 | #undef NVRAM_ITEM_RF_TAS_TST |
| 592 | #define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 593 | #define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 594 | #define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 595 | #define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 596 | /*** TAS LID REC SIZE ***/ |
| 597 | #define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 598 | #define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 599 | /*ELNA*/ |
| 600 | #define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 601 | /*TX POWER*/ |
| 602 | #define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 603 | #define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 604 | |
| 605 | #include "cl1_nvram_id.h" |
| 606 | |
| 607 | #endif |
| 608 | |
| 609 | #if (defined(__MD97__) || defined(__MD97P__)) |
| 610 | typedef enum |
| 611 | { |
| 612 | NVRAM_EF_CL1_CUST_PARAM_LID = NVRAM_LID_GRP_CL1(0), |
| 613 | NVRAM_EF_CL1_MIPI_PARAM_LID = NVRAM_LID_GRP_CL1(2), |
| 614 | NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_1XRTT_LID = NVRAM_LID_GRP_CL1(9), |
| 615 | NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_EVDO_LID = NVRAM_LID_GRP_CL1(10), |
| 616 | NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_1XRTT_LID = NVRAM_LID_GRP_CL1(15), |
| 617 | NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_EVDO_LID = NVRAM_LID_GRP_CL1(16), |
| 618 | |
| 619 | /*** TAS ***//*VAR*/ |
| 620 | NVRAM_EF_CL1_CUST_TAS_FEATURE_LID = NVRAM_LID_GRP_CL1(17), |
| 621 | NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_LID = NVRAM_LID_GRP_CL1(18), |
| 622 | NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_LID = NVRAM_LID_GRP_CL1(19), |
| 623 | NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_LID = NVRAM_LID_GRP_CL1(20), |
| 624 | NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_LID = NVRAM_LID_GRP_CL1(21), |
| 625 | NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_LID = NVRAM_LID_GRP_CL1(22), |
| 626 | NVRAM_EF_CL1_CUST_TUNER_LID = NVRAM_LID_GRP_CL1(23), |
| 627 | /*** TAS ***//*ARRAY*/ |
| 628 | NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_LID = NVRAM_LID_GRP_CL1(24), |
| 629 | NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_LID = NVRAM_LID_GRP_CL1(25), |
| 630 | NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_LID = NVRAM_LID_GRP_CL1(26), |
| 631 | NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_LID = NVRAM_LID_GRP_CL1(27), |
| 632 | NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_LID = NVRAM_LID_GRP_CL1(28), |
| 633 | NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_LID = NVRAM_LID_GRP_CL1(29), |
| 634 | NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_LID = NVRAM_LID_GRP_CL1(30), |
| 635 | NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_LID = NVRAM_LID_GRP_CL1(31), |
| 636 | |
| 637 | NVRAM_EF_CL1_CUST_TAS_CFG_LID = NVRAM_LID_GRP_CL1(32), |
| 638 | NVRAM_EF_CL1_CUST_ELNA_CFG_LID = NVRAM_LID_GRP_CL1(33), |
| 639 | NVRAM_EF_CL1_CUST_ELNA_EVENT_LID = NVRAM_LID_GRP_CL1(34), |
| 640 | NVRAM_EF_CL1_CUST_ELNA_DATA_LID = NVRAM_LID_GRP_CL1(35), |
| 641 | |
| 642 | NVRAM_EF_CL1_TX_POWER_BACK_OFF_LID = NVRAM_LID_GRP_CL1(36), |
| 643 | NVRAM_EF_CL1_TX_POWER_OFFSET_LID = NVRAM_LID_GRP_CL1(37), |
| 644 | |
| 645 | NVRAM_EF_CL1_TAS_TST_CONFIG_LID = NVRAM_LID_GRP_CL1(38), |
| 646 | NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_LID = NVRAM_LID_GRP_CL1(39), |
| 647 | NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_LID = NVRAM_LID_GRP_CL1(40), |
| 648 | NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_LID = NVRAM_LID_GRP_CL1(41), |
| 649 | |
| 650 | NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_LID = NVRAM_LID_GRP_CL1(42), |
| 651 | NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_LID = NVRAM_LID_GRP_CL1(43), |
| 652 | |
| 653 | NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_LID = NVRAM_LID_GRP_CL1(44), |
| 654 | NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_LID = NVRAM_LID_GRP_CL1(45), |
| 655 | NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_LID = NVRAM_LID_GRP_CL1(46), |
| 656 | NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_LID = NVRAM_LID_GRP_CL1(47), |
| 657 | NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_1XRTT_LID = NVRAM_LID_GRP_CL1(48), |
| 658 | NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_EVDO_LID = NVRAM_LID_GRP_CL1(49), |
| 659 | |
| 660 | NVRAM_EF_CL1_DPD_COMMON_CTRL_LID = NVRAM_LID_GRP_CL1(50), |
| 661 | NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_LID = NVRAM_LID_GRP_CL1(51), |
| 662 | |
| 663 | NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_LID = NVRAM_LID_GRP_CL1(52), |
| 664 | NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_LID = NVRAM_LID_GRP_CL1(53), |
| 665 | |
| 666 | NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_LID = NVRAM_LID_GRP_CL1(54), |
| 667 | |
| 668 | NVRAM_EF_CL1_CUST_RF_HOPPING_LID = NVRAM_LID_GRP_CL1(55), |
| 669 | |
| 670 | /* WARNING: DO NOT modify the last LID */ |
| 671 | NVRAM_EF_CL1_LAST_LID = NVRAM_LID_GRP_CL1(255) |
| 672 | }nvram_lid_cl1_enum; |
| 673 | |
| 674 | // VERNO |
| 675 | |
| 676 | #define NVRAM_EF_CL1_CUST_PARAM_LID_VERNO "001" |
| 677 | #define NVRAM_EF_CL1_MIPI_PARAM_LID_VERNO "001" |
| 678 | |
| 679 | /*** TAS ***//*VAR*/ |
| 680 | #define NVRAM_EF_CL1_CUST_TAS_FEATURE_LID_VERNO "001" |
| 681 | #define NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_LID_VERNO "001" |
| 682 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_LID_VERNO "001" |
| 683 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_LID_VERNO "001" |
| 684 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_LID_VERNO "001" |
| 685 | #define NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_LID_VERNO "001" |
| 686 | #define NVRAM_EF_CL1_CUST_TUNER_LID_VERNO "001" |
| 687 | /*** TAS ***//*ARRAY*/ |
| 688 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_LID_VERNO "001" |
| 689 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_LID_VERNO "001" |
| 690 | |
| 691 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_LID_VERNO "001" |
| 692 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_LID_VERNO "001" |
| 693 | |
| 694 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_LID_VERNO "001" |
| 695 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_LID_VERNO "001" |
| 696 | |
| 697 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_LID_VERNO "001" |
| 698 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_LID_VERNO "001" |
| 699 | |
| 700 | /*ELNA*/ |
| 701 | #define NVRAM_EF_CL1_CUST_ELNA_CFG_LID_VERNO "002" |
| 702 | |
| 703 | #define NVRAM_EF_CL1_TX_POWER_BACK_OFF_LID_VERNO "001" |
| 704 | #define NVRAM_EF_CL1_TX_POWER_OFFSET_LID_VERNO "002" |
| 705 | #define NVRAM_EF_CL1_TAS_TST_CONFIG_LID_VERNO "001" |
| 706 | /*DAT*/ |
| 707 | #define NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_LID_VERNO "001" |
| 708 | #define NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_LID_VERNO "001" |
| 709 | #define NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_LID_VERNO "001" |
| 710 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_LID_VERNO "001" |
| 711 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_LID_VERNO "001" |
| 712 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_LID_VERNO "001" |
| 713 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_LID_VERNO "001" |
| 714 | |
| 715 | #define NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_LID_VERNO "001" |
| 716 | #define NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_LID_VERNO "000" |
| 717 | |
| 718 | /*DPD*/ |
| 719 | #define NVRAM_EF_CL1_DPD_COMMON_CTRL_LID_VERNO "001" |
| 720 | #define NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_LID_VERNO "001" |
| 721 | #define NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_LID_VERNO "001" |
| 722 | #define NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_LID_VERNO "001" |
| 723 | |
| 724 | #define NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_LID_VERNO "001" |
| 725 | |
| 726 | #define NVRAM_EF_CL1_CUST_RF_HOPPING_LID_VERNO "000" |
| 727 | |
| 728 | // HASH Key |
| 729 | #define NVRAM_EF_CL1_CUST_PARAM_LID_HASH 0xF475E6A9 |
| 730 | #define NVRAM_EF_CL1_MIPI_PARAM_LID_HASH 0x3091DE51 |
| 731 | #define NVRAM_EF_CL1_CUST_TAS_FEATURE_LID_HASH 0x6545A7B7 |
| 732 | #define NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_LID_HASH 0x0C0D41AE |
| 733 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_LID_HASH 0xD1F8B014 |
| 734 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_LID_HASH 0x02E56E41 |
| 735 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_LID_HASH 0x89B819D5 |
| 736 | #define NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_LID_HASH 0xF7B23627 |
| 737 | #define NVRAM_EF_CL1_CUST_TUNER_LID_HASH 0xF7643065 |
| 738 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_LID_HASH 0xF482A4A7 |
| 739 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_LID_HASH 0xC606AB82 |
| 740 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_LID_HASH 0xC67DE834 |
| 741 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_LID_HASH 0xD2EF7F2A |
| 742 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_LID_HASH 0x9A77EAD6 |
| 743 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_LID_HASH 0x800464BD |
| 744 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_LID_HASH 0xF281DF2A |
| 745 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_LID_HASH 0x96DB1104 |
| 746 | #define NVRAM_EF_CL1_CUST_TAS_CFG_LID_HASH 0xFDB89A5F |
| 747 | #define NVRAM_EF_CL1_CUST_ELNA_CFG_LID_HASH 0x37F8C00D |
| 748 | #define NVRAM_EF_CL1_TX_POWER_BACK_OFF_LID_HASH 0x46469AA7 |
| 749 | #define NVRAM_EF_CL1_TX_POWER_OFFSET_LID_HASH 0x5C1CCAC6 |
| 750 | #define NVRAM_EF_CL1_TAS_TST_CONFIG_LID_HASH 0x21DDFFEE |
| 751 | #define NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_LID_HASH 0x352F8E5B |
| 752 | #define NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_LID_HASH 0xF5F9E9AB |
| 753 | #define NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_LID_HASH 0xD8F049DF |
| 754 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_LID_HASH 0x2A65CC8E |
| 755 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_LID_HASH 0x6B15CB8C |
| 756 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_LID_HASH 0x533CBF0F |
| 757 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_LID_HASH 0xCBBFD5CE |
| 758 | #define NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_LID_HASH 0xEC582023 |
| 759 | #define NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_LID_HASH 0xE776D29E |
| 760 | #define NVRAM_EF_CL1_DPD_COMMON_CTRL_LID_HASH 0xB8B7A6FD |
| 761 | #define NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_LID_HASH 0x17CEFFA5 |
| 762 | #define NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_LID_HASH 0xC2F0E2D8 |
| 763 | #define NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_LID_HASH 0x5A919B54 |
| 764 | #define NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_LID_HASH 0xF4C1D4BD |
| 765 | |
| 766 | #define NVRAM_EF_CL1_CUST_RF_HOPPING_LID_HASH 0xAD109761 |
| 767 | |
| 768 | |
| 769 | /*this tx power offset adjustment is set for verizon case*/ |
| 770 | #include "cl1_rf_public.h" |
| 771 | typedef struct |
| 772 | { |
| 773 | kal_uint16 accTxPwrOffset[SYS_BAND_CLASS_MAX];/*tx power offset in dB of band0-20, access tx power += accTxPwrOffset[band], default 0*/ |
| 774 | kal_uint16 maxPwrbackoff[SYS_BAND_CLASS_MAX];/*access max power backoff of band0-20, max power -= maxPwrbackoff[band], default 0*/ |
| 775 | }CL1_L1D_TX_POWER_OFFSET_T; |
| 776 | // Size and Total |
| 777 | |
| 778 | #define NVRAM_EF_CL1_CUST_PARAM_SIZE sizeof(CL1D_RF_CUST_PARAM_T) |
| 779 | #define NVRAM_EF_CL1_MIPI_PARAM_SIZE sizeof(CL1D_RF_MIPI_PARAM_T) |
| 780 | |
| 781 | /*** TAS ***//*VAR*/ |
| 782 | #define NVRAM_EF_CL1_CUST_TAS_FEATURE_SIZE sizeof(C2K_CUSTOM_TAS_FEATURE_T) |
| 783 | #define NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_SIZE sizeof(C2K_CUSTOM_TAS_FE_ROUTE_DATABASE_T) |
| 784 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_SIZE sizeof(C2K_CUSTOM_TAS_FE_CAT_A_T) |
| 785 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_SIZE sizeof(C2K_CUSTOM_TAS_FE_CAT_B_T) |
| 786 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_SIZE sizeof(C2K_CUSTOM_TAS_FE_CAT_C_T) |
| 787 | #define NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_SIZE sizeof(C2K_CUSTOM_TUNER_FE_ROUTE_TABLE) |
| 788 | #define NVRAM_EF_CL1_CUST_TUNER_SIZE sizeof(C2K_CUSTOM_TUNER_BAND_T) |
| 789 | #define NVRAM_EF_CL1_TAS_TST_CONFIG_SZIE sizeof(CL1D_RF_TAS_TST_CONFIG_T) |
| 790 | #define NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_SIZE sizeof(CL1_L1D_TX_POWER_OFFSET_T) |
| 791 | /*** TAS ***//*ARRAY*/ |
| 792 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_TAS_EVENT_MAX_NUM |
| 793 | |
| 794 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T) * MIPI_TAS_DATA_MAX_NUM |
| 795 | |
| 796 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_TAS_EVENT_MAX_NUM |
| 797 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T) * MIPI_TAS_DATA_MAX_NUM |
| 798 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_TAS_EVENT_MAX_NUM |
| 799 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T) * MIPI_TAS_DATA_MAX_NUM |
| 800 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T) * MIPI_TAS_EVENT_MAX_NUM |
| 801 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T) * MIPI_TAS_DATA_MAX_NUM |
| 802 | |
| 803 | /*ELNA*/ |
| 804 | #define NVRAM_EF_CL1_CUST_ELNA_CFG_SIZE sizeof(CL1D_RF_CUST_ELNA_CFG_T) |
| 805 | /*TX POWER*/ |
| 806 | #define NVRAM_EF_CL1_TX_POWER_BACK_OFF_SIZE sizeof(CL1D_RF_TX_POWER_BACK_OFF_T) |
| 807 | #define NVRAM_EF_CL1_TX_POWER_OFFSET_SIZE sizeof(CL1D_RF_SWTP_TX_POWER_OFFSET_T) |
| 808 | #if IS_C2K_DAT_RFD_CTRL_EN |
| 809 | /*DAT*/ |
| 810 | #define NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_SIZE sizeof(CL1D_RF_DAT_FE_ROUTE_DATABASE_T) |
| 811 | #define NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_SIZE sizeof(CL1D_RF_DAT_FE_CAT_A_T) |
| 812 | #define NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_SIZE sizeof(CL1D_RF_DAT_FE_CAT_B_T) |
| 813 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T)*MIPI_DAT_EVENT_MAX_NUM |
| 814 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T)*MIPI_DAT_DATA_MAX_NUM |
| 815 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_SIZE sizeof(CL1D_RF_MIPI_EVENT_TABLE_T)*MIPI_DAT_EVENT_MAX_NUM |
| 816 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_SIZE sizeof(CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T)*MIPI_DAT_DATA_MAX_NUM |
| 817 | #endif |
| 818 | #define NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_SIZE sizeof(CL1D_RF_SAR_TX_POWER_OFFSET_T) |
| 819 | |
| 820 | #define NVRAM_EF_CL1_DPD_COMMON_CTRL_SIZE sizeof(CL1D_RF_DPD_COMMON_CTRL_T) |
| 821 | #define NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_SIZE sizeof(CL1D_RF_PCFE_DPD_OTFC_CUSTOM_PARA_T) |
| 822 | #define NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_SIZE sizeof(C2K_CUSTOM_ANT_FE_ROUTE_DATABASE_T) |
| 823 | #define NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_SIZE sizeof(C2K_CUSTOM_UTAS_ALGORITHM_PARAMETER_T) |
| 824 | #define NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_SIZE sizeof(C2K_CUSTOM_DAT_ANT_TUNER_ROUTE_DATABASE_T) |
| 825 | #if IS_C2K_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT |
| 826 | #define NVRAM_EF_CL1_CUST_RF_HOPPING_DATABASE_SIZE sizeof(CL1D_RF_HOPPING_DATA_BASE_T) |
| 827 | #endif |
| 828 | #define NVRAM_EF_CL1_CUST_PARAM_TOTAL 1 |
| 829 | #define NVRAM_EF_CL1_MIPI_PARAM_TOTAL 1 |
| 830 | |
| 831 | /*** TAS ***//*VAR*/ |
| 832 | #define NVRAM_EF_CL1_CUST_TAS_FEATURE_TOTAL 1 |
| 833 | #define NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_TOTAL 1 |
| 834 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_TOTAL 1 |
| 835 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_TOTAL 1 |
| 836 | #define NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_TOTAL 1 |
| 837 | #define NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_TOTAL 1 |
| 838 | #define NVRAM_EF_CL1_CUST_TUNER_TOTAL MAX_BAND_NUM |
| 839 | |
| 840 | /*** TAS ***//*ARRAY*/ |
| 841 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_TOTAL MAX_BAND_NUM |
| 842 | |
| 843 | #define NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_TOTAL MAX_BAND_NUM |
| 844 | |
| 845 | #define NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_TOTAL 1 |
| 846 | |
| 847 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_TOTAL MAX_Route_NUM |
| 848 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_TOTAL MAX_Route_NUM |
| 849 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_TOTAL MAX_Route_NUM |
| 850 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_TOTAL MAX_Route_NUM |
| 851 | #define NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_TOTAL MAX_Route_NUM |
| 852 | #define NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_TOTAL MAX_Route_NUM |
| 853 | |
| 854 | /*ELNA*/ |
| 855 | #define NVRAM_EF_CL1_CUST_ELNA_CFG_TOTAL 1 |
| 856 | |
| 857 | /*TX POWER*/ |
| 858 | #define NVRAM_EF_CL1_TX_POWER_BACK_OFF_TOTAL MAX_BAND_NUM |
| 859 | #define NVRAM_EF_CL1_TX_POWER_OFFSET_TOTAL MAX_BAND_NUM |
| 860 | #define NVRAM_EF_CL1_TAS_TST_CFG_TOTAL 1 |
| 861 | /*DAT*/ |
| 862 | #define NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_TOTAL 1 |
| 863 | #define NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_TOTAL 1 |
| 864 | #define NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_TOTAL 1 |
| 865 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_TOTAL MAX_DAT_CAT_A_Route_NUM |
| 866 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_TOTAL MAX_DAT_CAT_A_Route_NUM |
| 867 | #define NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_TOTAL MAX_DAT_CAT_B_Route_NUM |
| 868 | #define NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_TOTAL MAX_DAT_CAT_B_Route_NUM |
| 869 | |
| 870 | #define NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_TOTAL MAX_BAND_NUM |
| 871 | #define NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_TOTAL 1 |
| 872 | |
| 873 | #define NVRAM_EF_CL1_DPD_COMMON_CTRL_TOTAL MAX_BAND_NUM |
| 874 | #define NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_TOTAL 1 |
| 875 | #define NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_TOTAL 1 |
| 876 | #define NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_TOTAL 1 |
| 877 | #define NVRAM_EF_CL1_CUST_RF_HOPPING_DATABASE_TOTAL 1 |
| 878 | |
| 879 | #undef NVRAM_ITEM_RF_CUST |
| 880 | #undef NVRAM_ITEM_MIPI |
| 881 | #undef NVRAM_ITEM_RF_CAL |
| 882 | #undef NVRAM_ITEM_RF_POC |
| 883 | #undef NVRAM_ITEM_RF_TAS_VAR |
| 884 | #undef NVRAM_ITEM_RF_TAS_ARRAY |
| 885 | #undef NVRAM_ITEM_ELNA_VAR |
| 886 | #undef NVRAM_ITEM_TX_POWER_VAR |
| 887 | #undef NVRAM_ITEM_RF_TAS_TST |
| 888 | #define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 889 | #define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 890 | #define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 891 | #define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 892 | /*** TAS LID REC SIZE ***/ |
| 893 | #define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 894 | #define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 895 | /*ELNA*/ |
| 896 | #define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 897 | /*TX POWER*/ |
| 898 | #define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 899 | #define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) |
| 900 | |
| 901 | #include "cl1_nvram_id.h" |
| 902 | |
| 903 | #endif |
| 904 | |
| 905 | |
| 906 | #ifdef __cplusplus |
| 907 | } |
| 908 | #endif |
| 909 | |
| 910 | #endif /*__C2K_RAT__ */ |
| 911 | #endif /* __CL1_NVRAM_DEF_H__ */ |
| 912 | |