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192.168.1.100 / T800_MD / 1eb8f53f94c145708b5ea2c6b9b96ea3d613f607 / . / mcu / l1 / interface / mml1 / l1d_mmrf_interface.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
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14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
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21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
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24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
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31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * l1d_mmrf_interface.h
41 *
42 * Project:
43 * --------
44 * TK6291
45 *
46 * Description:
47 * ------------
48 * L1D interface to Multi-Mode Multi-RAT RF Central Control
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *----------------------------------------------------------------------------
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274 *----------------------------------------------------------------------------
275 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
276 *============================================================================
277 ****************************************************************************/
278
279#ifndef _L1D_MMRF_INTERFACE_H_
280#define _L1D_MMRF_INTERFACE_H_
281
282/*===============================================================================*/
283
284#include "kal_general_types.h"
285
286#include "mml1_rf_interface.h"
287#include "mml1_rf_cal_interface.h"
288#include "mml1_rf_calpocif.h"
289
290#include "l1cal.h"
291#include "l1d_cid.h"
292#if IS_CHIP_MT6297_AND_LATTER_VERSION
293#include "mml1_rxdfe_api.h"
294#endif
295#if IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || defined(L1_SIM)
296#include "mml1_rf_dfe.h"
297#endif
298
299/*===============================================================================*/
300
301#if IS_2G_Gen97_UTAS_SUPPORT
302extern MMRF_COMMON_BAND_IDX_E GL1D_FREQUENCYBAND_2_UNIBAND_TABLE[FrequencyBandCount];
303#endif
304
305#define GSM_MAX_MIPI_PAON_CW_NUMBER_PER_BAND (48) //24*2
306#define GSM_MAX_MIPI_PAOFF_CW_NUMBER_PER_BAND (24) //12*2
307#if (defined(MT6177M_2G_RF) || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T)
308/*MT6173*/ /* RF CW table type for the action to turn on TX PA in low gain mode */
309/*MT6173*/ typedef struct
310/*MT6173*/ {
311/*MT6173*/ kal_uint32 data1[GSM_MAX_MIPI_PAON_CW_NUMBER_PER_BAND];
312/*MT6173*/
313/*MT6173*/ }GL1D_RF_CAL_TXPA_ON_LOWGAIN_BUFFER_T;
314/*MT6173*/
315/*MT6173*/ /* RF CW table type for the action to turn on TX PA in low gain mode */
316/*MT6173*/ typedef struct
317/*MT6173*/ {
318/*MT6173*/ kal_uint32 data1[GSM_MAX_MIPI_PAOFF_CW_NUMBER_PER_BAND];
319/*MT6173*/
320/*MT6173*/ }GL1D_RF_CAL_TXPA_OFF_BUFFER_T;
321/*MT6173*/
322/*MT6173*/ /** RF CW table type for the BPI ctrl to turn on TX PA */
323/*MT6173*/ typedef struct
324/*MT6173*/ {
325/*MT6173*/ kal_uint32 pt0_data_l; ///< bpi[31:0]
326/*MT6173*/ kal_uint32 pt0_data_h; ///< bpi[47:32]
327/*MT6173*/ kal_uint32 pt1_data_l; ///< bpi[31:0]
328/*MT6173*/ kal_uint32 pt1_data_h; ///< bpi[47:32]
329/*MT6173*/ kal_uint32 pt2_data_l; ///< bpi[31:0]
330/*MT6173*/ kal_uint32 pt2_data_h; ///< bpi[47:32]
331/*MT6173*/
332/*MT6173*/ }GL1D_RF_CAL_TX_ON_BPI_CTRL_BUFFER_T;
333/*MT6173*/
334/*MT6173*/ /** RF CW table type for the BPI ctrl to turn off TX PA */
335/*MT6173*/ typedef struct
336/*MT6173*/ {
337/*MT6173*/ kal_uint32 pt3_data_l; ///< bpi[31:0]
338/*MT6173*/ kal_uint32 pt3_data_h; ///< bpi[47:32]
339/*MT6173*/
340/*MT6173*/ }GL1D_RF_CAL_TX_OFF_BPI_CTRL_BUFFER_T;
341/*MT6173*/ #if defined(MT6177M_2G_RF)
342/*MT6173*/ /* MMRFC Related Setting */
343/*MT6173*/ /* RF CW table type for the action to set RF STX settings, including DCO/NMMD */
344/*MT6173*/ typedef struct
345/*MT6173*/ {
346/*MT6173*/ RF_CW_T stxCw511; /* CW511: STX Band */
347/*MT6173*/ RF_CW_T stxCw529; /* CW529: STX Codetype */
348/*MT6173*/ RF_CW_T stxCw549; /* CW549: STX_NMMD */
349/*MT6173*/ RF_CW_T stxCw550; /* CW550: STX_NMMD */
350/*MT6173*/ RF_CW_T stxCw551; /* CW551: STX_NMMD1 */
351/*MT6173*/ RF_CW_T stxCw552; /* CW552: STX_NMMD1 */
352/*MT6173*/ RF_CW_T stxCw582; /* CW582: STX NFRAC offset */
353/*MT6173*/ }GL1D_RF_CAL_RF_STX_CONFIG_BUFFER_T;
354/*MT6173*/
355/*MT6173*/ /* RF CW table type for the action to set RF TX output modulator mode (HRM, NHRM), */
356/*MT6173*/ /* TX o/p port, TX balun cap., TX PGA driver */
357/*MT6173*/ typedef struct
358/*MT6173*/ {
359/*MT6173*/ RF_CW_T txCw707; /* CW707: TX Port */
360/*MT6173*/ RF_CW_T txCw786; /* CW786: Set TX LO FE Comp. */
361/*MT6173*/ RF_CW_T txCw794; /* CW794: Set TX Balun Result, from PGA Cap Tuning */
362/*MT6173*/ RF_CW_T txCw795; /* CW795: Set TX Balun Cap 1, from PGA Cap Tuning */
363/*MT6173*/ RF_CW_T txCw796; /* CW796: Set TX Balun Cap 2, from PGA Cap Tuning */
364/*MT6173*/ RF_CW_T txCw814; /* CW814: Set LO supply settings */
365/*MT6173*/ RF_CW_T txCw712; /* CW712: Set Modulator bias setting */
366/*MT6173*/ RF_CW_T txCw802; /* CW802: Set LO cal inputs */
367/*MT6173*/ RF_CW_T txCw803; /* CW803: Set LO cal inputs */
368/*MT6173*/ RF_CW_T txCw816; /* CW816: Set TTG buffer gain*/
369/*MT6173*/ RF_CW_T txCw818; /* CW818: Set Detector setting */
370/*MT6173*/ }GL1D_RF_CAL_RF_TX_CONFIG_BUFFER_T;
371/*MT6173*/
372/*MT6173*/ /* RF CW table type for the action to set RF TX PGA driver bias current for Linear mode */
373/*MT6173*/ typedef struct
374/*MT6173*/ {
375/*MT6173*/ RF_CW_T txGainCw797; /* CW797: Set TX Drv bias for Linear Mode */
376/*MT6173*/ RF_CW_T txGainCw798; /* CW798: Set TX DRV bias temp coefficient*/
377/*MT6173*/
378/*MT6173*/ }GL1D_RF_CAL_RF_TX_DRV_BIAS_LIN_CONFIG_BUFFER_T;
379/*MT6173*/
380/*MT6173*/ /** RF CW table type for the action to set RF TX PGA driver bias current for DPD mode */
381/*MT6173*/ typedef struct
382/*MT6173*/ {
383/*MT6173*/ RF_CW_T txGainCw799;
384/*MT6173*/
385/*MT6173*/ }GL1D_RF_CAL_RF_TX_DRV_BIAS_DPD_CONFIG_BUFFER_T;
386/*MT6173*/ #endif
387#elif defined(MT6177L_2G_RF)
388/*MT6177L*/ /* RF CW table type for the action to set RF TX output modulator mode (HRM, NHRM), */
389/*MT6177L*/ /* TX o/p port, TX balun cap., TX PGA driver */
390/*MT6177L*/ typedef struct
391/*MT6177L*/ {
392/*MT6177L*/ RF_CW_T txCw707; /* CW707: TX Port */
393/*MT6177L*/ RF_CW_T txCw786; /* CW786: Set TX LO FE Comp. */
394/*MT6177L*/ RF_CW_T txCw794; /* CW794: Set TX Balun Result, from PGA Cap Tuning */
395/*MT6177L*/ RF_CW_T txCw795; /* CW795: Set TX Balun Cap 1, from PGA Cap Tuning */
396/*MT6177L*/ RF_CW_T txCw796; /* CW796: Set TX Balun Cap 2, from PGA Cap Tuning */
397/*MT6177L*/ RF_CW_T txCw814; /* CW814: Set LO supply settings */
398/*MT6177L*/ RF_CW_T txCw712; /* CW712: Set Modulator bias setting */
399/*MT6177L*/ RF_CW_T txCw802; /* CW802: Set LO cal inputs */
400/*MT6177L*/ RF_CW_T txCw803; /* CW803: Set LO cal inputs */
401/*MT6177L*/ RF_CW_T txCw714; /* CW714: Set LO */
402/*MT6177L*/ // RF_CW_T txCw787; /* CW787: Write LPF CSEL value */
403/*MT6177L*/ // RF_CW_T txCw793; /* CW793: Write RCF CEL & RSEL for desired BW */
404/*MT6177L*/ // RF_CW_T txCw710; /* CW710: Set BW3_EN & LPF_RSEL */
405/*MT6177L*/ RF_CW_T txCw816; /* CW816: Set TTG buffer gain*/
406/*MT6177L*/ RF_CW_T txCw818; /* CW818: Set Detector setting */
407/*MT6177L*/ RF_CW_T txCw819; /* CW819: Set LPF VCM controls setting(High Power UE) */
408/*MT6177L*/ }GL1D_RF_CAL_RF_TX_CONFIG_BUFFER_T;
409/*MT6177L*/
410
411#endif
412void L1D_MMRF_PowerOnCalibration(void);
413void L1D_MMRF_L1CoreSHMDataInit(void);
414void L1D_MMRF_L1coreSHMUpdate2Local(void);
415kal_uint32 L1D_MMRF_UpdateRuntimeHandler(kal_uint32 nvram_lid, kal_uint32 record_idx, kal_uint8 *data, kal_uint16 nvram_size);
416
417#if defined(__F32_XOSC_REMOVAL_SUPPORT__)
418/* Update CloadFreqOffset before share this value to MMRF */
419int L1D_RF_UpdateCLoadFreqOffset( int freq_offset );
420#endif
421
422/* SHM reset function*/
423void L1_MULTI_RESET_AFC_SHM(void);
424
425//API for 2G MMRFC
426#if defined(MT6176_2G_RF)
427kal_uint16 L1D_RF_Get_RFC_State(void);
428kal_bool L1D_RF_DET_Path_Query(MMRFC_XL1_BAND_NUM_E band, MMRF_DET_IO_E tx_det_io);
429void L1D_RF_GET_TX_DET_ANT(MMRFC_XL1_BAND_NUM_E band, kal_uint32 route_idx, kal_bool is_fw_path);
430void L1D_RF_POC_CDCOC_Result_WB( kal_uint8 TX_WB_port, MMRFC_XL1_BAND_NUM_E band, kal_uint32* det_coarse_dcoc_cw807, kal_uint32* det_coarse_dcoc_cw808 );
431#endif
432kal_uint16 L1D_RF_Cal_Poc_NVRAM_Lid_Total_Num_InUse( void );
433kal_uint16 L1D_RF_Get_Rf_Self_Cal_Result_Size(kal_uint16 lid_index);
434kal_uint16 L1D_RF_Get_Rf_Self_Cal_Result(kal_uint16 lid_index, kal_uint16 lid_size, kal_uint8 *dst);
435kal_uint16 L1D_RF_Set_Rf_Self_Cal_Result(kal_uint16 lid_index, kal_uint16 lid_size, kal_uint8 *src);
436kal_uint16 L1D_RF_Get_Rf_Self_Cal_String( kal_uint16 lid_index, kal_char *string_dst );
437void L1D_RF_UpdatePocResultToSHM(MMRFC_XL1_BAND_NUM_E band, kal_uint8 band_idx, kal_uint8 subband_idx, kal_uint8 cal_type, MMRFC_GSM_RESULT_PER_BAND_T* cal_result);
438 #if defined(__MD92__)
439kal_uint32 L1D_RF_DATA_BUFFER_LENGTH_RETURN(MMPOC_BUFFER_IDX_E buf_type);
440kal_uint32* L1D_RF_DATA_BUFFER_PTR_RETURN(MMPOC_BUFFER_IDX_E buf_type);
441kal_uint32 L1D_RF_DATA_BUFFER_MIPI_LENGTH_RETURN(kal_bool is_mipi_on, kal_uint8 curr_band_idx);
442MML1_RF_BSIMM_PORT_T L1D_RF_BUF_DATA_PORT_TABLE_RETURN(MMPOC_BUFFER_IDX_E bufId);
443 #endif
444#if IS_CHIP_MT6297_AND_LATTER_VERSION
445#else
446#if IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T
447void gsm_rfc_pa_on_ctrl(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, MMRF_PMIC_VPA_NUM_E vpaIdx, kal_uint8 is_txcca);
448void gsm_rfc_pa_off_ctrl(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, MMRF_PMIC_VPA_NUM_E vpaIdx, kal_uint8 is_txcca);
449
450/*MIPI DATA ON OFF */
451void L1D_MMRF_RFCAL_TX_PA_ON_LOWGAIN_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
452 kal_uint8* length,
453 GL1D_RF_CAL_TXPA_ON_LOWGAIN_BUFFER_T* buffer,
454 kal_uint8 buffer_length,
455 MML1_RF_BSIMM_PORT_T* port_sel);
456void L1D_MMRF_RFCAL_TX_PA_OFF_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
457 kal_uint8* length,
458 GL1D_RF_CAL_TXPA_OFF_BUFFER_T* buffer,
459 kal_uint8 buffer_length,
460 MML1_RF_BSIMM_PORT_T* port_sel);
461/*BPI DATA ON OFF */
462void L1D_MMRF_RFCAL_TX_ON_BPI_CTRL_BUFFER_TYPE(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
463 kal_uint8* length,
464 GL1D_RF_CAL_TX_ON_BPI_CTRL_BUFFER_T* buffer,
465 kal_uint8 buffer_length,
466 MML1_RF_BSIMM_PORT_T* port_sel);
467
468void L1D_MMRF_RFCAL_TX_OFF_BPI_CTRL_BUFFER_TYPE(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
469 kal_uint8* length,
470 GL1D_RF_CAL_TX_OFF_BPI_CTRL_BUFFER_T* buffer,
471 kal_uint8 buffer_length,
472 MML1_RF_BSIMM_PORT_T* port_sel);
473void gl1d_rfc_set_vpa (kal_bool vpa_en, MMRF_PMIC_VPA_NUM_E vpaIdx);
474
475void L1D_RFC_Get_TxConfigTable_PerBand( MMRFC_XL1_BAND_NUM_E mmrfc_band,MMRFC_TX_CAL_ROUTE_PER_BAND_CFG_T *tx_route_cfg);
476// Detector items
477void GL1D_RFC_DET_CDCOC_RESULT_HANDLING(kal_uint32 route_idx,
478 MMRFC_DET_G_IDX det_gain_idx,
479 MMRFC_POC_MRX_COARSE_DC_T* det_cdcoc_result,
480 bool emiRead_emiWrite
481 #if IS_MRX_DC_LOOP_ID_SUPPORT
482 ,MMRFC_MRX_LOOP_ID_E loop_id
483 #endif
484
485 );
486void GL1D_RFC_DET_DC_RESULT_HANDLING(kal_uint32 route_idx,
487 MMRFC_DET_G_IDX gain_idx,
488 kal_uint32 recal,
489 MMRFC_DET_DC_RESULT_T* tx_det_dc_calgo_result,
490 bool emiRead_emiWrite
491 #if IS_MRX_DC_LOOP_ID_SUPPORT
492 ,MMRFC_MRX_LOOP_ID_E loop_id
493 #endif
494 );
495
496void GL1D_RFC_DET_FIIQ_RESULT_HANDLING(kal_uint32 route_idx,
497 MMRFC_DET_G_IDX det_gain_idx,
498 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
499 kal_uint32 recal,
500 MMRFC_DET_IQAD_RESULT_T* tx_det_iqad_calgo_result,
501 bool emiRead_emiWrite);
502
503void GL1D_RFC_DET_FDPCB_RESULT_HANDLING(kal_uint32 route_idx,
504 MMRFC_DET_TIA_COMP_INDEX_E fe_gain_idx,
505 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
506 kal_uint32 recal,
507 MMRFC_DET_EQLPF_CFG_T* tx_det_pcb_calgo_result,
508 bool emiRead_emiWrite);
509
510// TX items
511void GL1D_RFC_TX_LPF_RESULT_HANDLING(kal_uint32 route_idx,
512 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
513 kal_int16 *rsel_val,
514 kal_int16 *csel_val1,
515 kal_int16 *csel_val2,
516 bool emiRead_emiWrite);
517
518void GL1D_RFC_TX_RCF_RESULT_HANDLING(kal_uint32 route_idx,
519 kal_int16 *rsel_val,
520 kal_int16 *csel_4a_val,
521 kal_int16 *csel_1b_val,
522 kal_int16 *csel_2a_val,
523 bool emiRead_emiWrite);
524
525void GL1D_RFC_TX_DC_RESULT_HANDLING(kal_uint32 route_idx,
526 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
527 kal_uint32 pwr_mode,
528 kal_uint32 tx_pga_slice,
529 kal_uint32 recal,
530 MMRFC_TX_IQDC_RESULT_T* tx_iqdc_calgo_result,
531 bool emiRead_emiWrite);
532
533void GL1D_RFC_TX_FIIQ_RESULT_HANDLING(kal_uint32 route_idx,
534 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
535 kal_uint32 pwr_mode,
536 kal_uint32 tx_pga_slice,
537 kal_uint32 recal,
538 MMRFC_TX_IQDC_RESULT_T* tx_iqdc_calgo_result,
539 bool emiRead_emiWrite);
540
541void GL1D_RFC_TX_CAP_RESULT_HANDLING(kal_uint32 route_idx,
542 kal_uint8 pga_ab,
543 kal_bool is_pre_cap_tuning,
544 kal_uint8* CAP_OPT_A,
545 bool emiRead_emiWrite);
546
547void GL1D_RFC_TX_MOD_RESULT_HANDLING( kal_uint32 route_idx,
548 kal_uint32 rfc_rt_idx,
549 kal_uint32 subband_idx,
550 kal_uint32 *tx_drv_ctunemod,
551 bool emiRead_emiWrite);
552
553void GL1D_RFC_TX_DNL_RESULT_HANDLING(kal_bool is_tx_dnl_valid,
554 kal_uint32 route_idx,
555 kal_int16* dnl_cal_result,
556 bool emiRead_emiWrite);
557
558void GL1D_RFC_TX_PGA_BIAS_RESULT_HANDLING(kal_uint32 route_idx,
559 MMRFC_POC_PGA_BIAS_T *tx_pga_bias_data,
560 kal_bool emiRead_emiWrite);
561void GL1D_RFC_GET_DEFAULT_TX_PGA_BIAS(kal_uint32 route_idx,
562 MMRFC_POC_PGA_BIAS_T* p_nominal_val);
563void GL1D_RFC_TX_CoarseDC_RESULT_HANDLING(kal_uint32 route_idx,
564 kal_uint32 tx_pga_slice,
565 kal_uint32 recal,
566 kal_int32 *tx_coarsedc_i,
567 kal_int32 *tx_coarsedc_q,
568 bool emiRead_emiWrite);
569void GL1D_RFC_GET_DEFAULT_TX_LPF(kal_uint32 route_idx,
570 kal_int16* nominal_value);
571
572
573void GL1D_RFC_MRX_PGA_TZA_RESULT_HANDLING(kal_uint32 route_idx,
574 MMRFC_MRX_PGA_TZA_BW_E bw_idx,
575 kal_int16 *mrx_pga_ctune,
576 kal_int16 *mrx_tza_ctune,
577 bool emiRead_emiWrite);
578
579
580
581/*TX DFE Compensation API for the Trinity L RF*/
582//TX DFE FIIQ Compensation
583void Gl1d_Rf_Tx_Param_Comp_Fiiq(kal_bool tx_fiiq_comp_en,
584 kal_uint32 tx_route_idx,
585 MMRFC_TX_RAT_CBW_CFG_E cbw_cfg,
586 MML1_TXDFE_TX_IQ_COMP_TAB_T* tx_iq);
587//TX DFE DC Compensation
588void Gl1d_Rf_Tx_Param_Comp_Dc(kal_bool tx_dc_comp_en,
589 kal_bool tx_coarse_dc_comp_en,
590 kal_uint32 tx_route_idx,
591 MMRFC_TX_RAT_CBW_CFG_E cbw_cfg,
592 MML1_TXDFE_TX_DC_COMP_TAB_T* tx_dc,
593 MML1_TXDFE_TX_COARSE_DC_COMP_TAB_T* tx_coarse_dc);
594//TX DFE FDIQ Compensation
595void Gl1d_Rf_Tx_Param_Comp_Fdiq(kal_bool tx_fdiq_comp_en,
596 kal_uint32 tx_route_idx,
597 MMRFC_TX_RAT_CBW_CFG_E cbw_cfg,
598 MML1_TXDFE_FDAD_TAP_E* freq_dep_tap,
599 kal_bool* tx_fdid_bypass,
600 MML1_TXDFE_FDAD_COMP_COEFF_TAB_T* tx_fdiq);
601//TX DFE GA Compensation
602void Gl1d_Rf_Tx_Param_Comp_Ga(kal_bool tx_asym_comp_en,
603 kal_uint32 tx_route_idx,
604 MMRFC_TX_RAT_CBW_CFG_E cbw_cfg,
605 MML1_TXDFE_ASYM_TAP_E* asymm_comp_tap,
606 kal_bool* tx_asym_bypass,
607 MML1_TXDFE_ASYMM_COMP_COEFF_TAB_T* tx_asym);
608
609/*DET DFE Compensation API for the Trinity L RF*/
610//DET DFE FIIQ Compensation
611void Gl1d_Rf_Det_Param_Comp_Fiiq(kal_bool det_fiiq_comp_en,
612 kal_uint32 route_idx,
613 MML1_DETDFE_TIA_GAIN_IDX_E fe_gain,
614 MML1_DET_FIIQ_COMP_T* det_fiiq_comp_params);
615//DET DFE DC Compensation
616void Gl1d_Rf_Det_Param_Comp_Dc(kal_bool det_dc_comp_en,
617 kal_uint32 route_idx,
618 kal_uint32 det_gain_step,
619 RF_COMP_INDEX_E comp_idx,
620 MML1_DET_DC_COMP_T* det_dc_comp_params);
621
622//DET DFE eqlpf Compensation
623void Gl1d_Rf_Det_Param_Comp_eqlpf(kal_bool det_eqlpf_comp_en,
624 kal_uint32 route_idx,
625 MML1_DETDFE_TIA_GAIN_IDX_E fe_gain,
626 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
627 MML1_DET_EQLPF_CFG_T* det_eqlpf_comp_params);
628
629
630
631#elif (defined(MT6177L_2G_RF) || defined(MT6177M_2G_RF))
632void L1D_RF_TX_PARAM_COMP(RF_COMP_INDEX_E comp_idx,
633 kal_uint32 tx_route_idx,
634 MMRFC_TX_RAT_CBW_CFG_E cbw_cfg,
635 MMRFC_XL1_BAND_NUM_E band,
636 kal_uint32 subband_idx);
637void L1D_RF_GetDetBwConfig(MMRFC_DET_CAL_ITEM_CFG_E detk_item, MMRFC_TX_RAT_CBW_CFG_E* start_cbw, MMRFC_TX_RAT_CBW_CFG_E* end_cbw, kal_uint8* tone_num);
638void L1D_RF_GetTxBwConfig(MMRFC_TX_CAL_ITEM_CFG_E txk_item, MMRFC_TX_RAT_CBW_CFG_E* start_cbw, MMRFC_TX_RAT_CBW_CFG_E* end_cbw);
639 #if defined(MT6177M_2G_RF)
640void L1D_MMRF_RFCAL_STX_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
641 kal_uint8* length,
642 GL1D_RF_CAL_RF_STX_CONFIG_BUFFER_T* buffer,kal_uint8 buffer_length);
643void L1D_MMRF_RFCAL_TX_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
644 kal_uint8* length,
645 GL1D_RF_CAL_RF_TX_CONFIG_BUFFER_T* buffer,kal_uint8 buffer_length);
646void L1D_MMRF_RFCAL_LIN_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
647 kal_uint8* length,
648 GL1D_RF_CAL_RF_TX_DRV_BIAS_LIN_CONFIG_BUFFER_T* buffer,kal_uint8 buffer_length);
649void L1D_MMRF_RFCAL_DPD_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
650 kal_uint8* length,
651 GL1D_RF_CAL_RF_TX_DRV_BIAS_DPD_CONFIG_BUFFER_T* buffer,kal_uint8 buffer_length);
652/*MIPI DATA ON OFF */
653void L1D_MMRF_RFCAL_TX_PA_ON_LOWGAIN_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
654 kal_uint8* length,
655 GL1D_RF_CAL_TXPA_ON_LOWGAIN_BUFFER_T* buffer,
656 kal_uint8 buffer_length,
657 MML1_RF_BSIMM_PORT_T* port_sel);
658void L1D_MMRF_RFCAL_TX_PA_OFF_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
659 kal_uint8* length,
660 GL1D_RF_CAL_TXPA_OFF_BUFFER_T* buffer,
661 kal_uint8 buffer_length,
662 MML1_RF_BSIMM_PORT_T* port_sel);
663/*BPI DATA ON OFF */
664void L1D_MMRF_RFCAL_TX_ON_BPI_CTRL_BUFFER_TYPE(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
665 kal_uint8* length,
666 GL1D_RF_CAL_TX_ON_BPI_CTRL_BUFFER_T* buffer,
667 kal_uint8 buffer_length,
668 MML1_RF_BSIMM_PORT_T* port_sel);
669
670void L1D_MMRF_RFCAL_TX_OFF_BPI_CTRL_BUFFER_TYPE(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
671 kal_uint8* length,
672 GL1D_RF_CAL_TX_OFF_BPI_CTRL_BUFFER_T* buffer,
673 kal_uint8 buffer_length,
674 MML1_RF_BSIMM_PORT_T* port_sel);
675 #elif defined(MT6177L_2G_RF)
676void L1D_MMRF_RFCAL_STX_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
677 kal_uint8* length,
678 MMRFC_STX_CONFIG_BUFFER_T* buffer);
679void L1D_MMRF_RFCAL_TX_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
680 kal_uint8* length,
681 GL1D_RF_CAL_RF_TX_CONFIG_BUFFER_T* buffer);
682void L1D_MMRF_RFCAL_LIN_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
683 kal_uint8* length,
684 MMRFC_TX_DRV_BIAS_LIN_CONFIG_BUFFER_T* buffer);
685void L1D_MMRF_RFCAL_DPD_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
686 kal_uint8* length,
687 MMRFC_TX_DRV_BIAS_DPD_CONFIG_BUFFER_T* buffer);
688
689/*MIPI DATA ON OFF */
690void L1D_MMRF_RFCAL_TX_PA_ON_LOWGAIN_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
691 kal_uint8* length,
692 MMRFC_TXPA_ON_LOWGAIN_BUFFER_T* buffer,
693 MML1_RF_BSIMM_PORT_T* port_sel);
694void L1D_MMRF_RFCAL_TX_PA_OFF_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
695 kal_uint8* length,
696 MMRFC_TXPA_OFF_BUFFER_T* buffer,
697 MML1_RF_BSIMM_PORT_T* port_sel);
698/*BPI DATA ON OFF */
699void L1D_MMRF_RFCAL_TX_ON_BPI_CTRL_BUFFER_TYPE(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
700 kal_uint8* length,
701 MMRFC_TX_ON_BPI_CTRL_BUFFER_T* buffer,
702 MML1_RF_BSIMM_PORT_T* port_sel);
703
704void L1D_MMRF_RFCAL_TX_OFF_BPI_CTRL_BUFFER_TYPE(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
705 kal_uint8* length,
706 MMRFC_TX_OFF_BPI_CTRL_BUFFER_T* buffer,
707 MML1_RF_BSIMM_PORT_T* port_sel);
708kal_uint32 L1D_RF_GET_LPF_CSEL_VALUE(kal_uint32 tx_self_comp_index);
709
710kal_int32 L1D_RF_GET_RCF_CSEL_VALUE(kal_uint32 route_index);
711 #if ( (defined(MT6293)|| defined(__MD93__)) && defined(L1_SIM) ) || ( (defined(MT6295M)|| defined(__MD95__)) && defined(L1_SIM) )
712void GL1D_RFC_DET_CDCOC_RESULT_HANDLING(kal_uint32 route_idx,
713 MMRFC_DET_G_IDX det_gain_idx,
714 MMRFC_POC_MRX_COARSE_DC_T* det_cdcoc_result,
715 bool emiRead_emiWrite
716 #if IS_MRX_DC_LOOP_ID_SUPPORT
717 ,MMRFC_MRX_LOOP_ID_E loop_id
718 #endif
719 );
720void GL1D_RFC_DET_DC_RESULT_HANDLING(kal_uint32 route_idx,
721 MMRFC_DET_G_IDX gain_idx,
722 kal_uint32 recal,
723 MMRFC_DET_DC_RESULT_T* tx_det_dc_calgo_result,
724 bool emiRead_emiWrite
725 #if IS_MRX_DC_LOOP_ID_SUPPORT
726 ,MMRFC_MRX_LOOP_ID_E loop_id
727 #endif
728 );
729
730void GL1D_RFC_DET_FIIQ_RESULT_HANDLING(kal_uint32 route_idx,
731 MMRFC_DET_G_IDX det_gain_idx,
732 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
733 kal_uint32 recal,
734 MMRFC_DET_IQAD_RESULT_T* tx_det_iqdnl_calgo_result,
735 bool emiRead_emiWrite);
736
737void GL1D_RFC_DET_FDPCB_RESULT_HANDLING(kal_uint32 route_idx,
738 MMRFC_DET_TIA_COMP_INDEX_E fe_gain_idx,
739 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
740 kal_uint32 recal,
741 MMRFC_DET_EQLPF_CFG_T* tx_det_pcb_calgo_result,
742 bool emiRead_emiWrite);
743
744// TX items
745void GL1D_RFC_TX_LPF_RESULT_HANDLING(kal_uint32 route_idx,
746 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
747 kal_int16 *rsel_val,
748 kal_int16 *csel_val1,
749 kal_int16 *csel_val2,
750 bool emiRead_emiWrite);
751
752void GL1D_RFC_TX_RCF_RESULT_HANDLING(kal_uint32 route_idx,
753 kal_int16 *rsel_val,
754 kal_int16 *csel_4a_val,
755 kal_int16 *csel_1b_val,
756 kal_int16 *csel_2a_val,
757 bool emiRead_emiWrite);
758
759void GL1D_RFC_TX_DC_RESULT_HANDLING(kal_uint32 route_idx,
760 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
761 kal_uint32 pwr_mode,
762 kal_uint32 tx_pga_slice,
763 kal_uint32 recal,
764 MMRFC_TX_IQDC_RESULT_T* tx_iqdc_calgo_result,
765 bool emiRead_emiWrite);
766
767void GL1D_RFC_TX_FIIQ_RESULT_HANDLING(kal_uint32 route_idx,
768 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
769 kal_uint32 pwr_mode,
770 kal_uint32 tx_pga_slice,
771 kal_uint32 recal,
772 MMRFC_TX_IQDC_RESULT_T* tx_iqdc_calgo_result,
773 bool emiRead_emiWrite);
774
775void GL1D_RFC_TX_CAP_RESULT_HANDLING(kal_uint32 route_idx,
776 kal_uint8 pga_ab,
777 kal_bool is_pre_cap_tuning,
778 kal_uint8* CAP_OPT_A,
779 bool emiRead_emiWrite);
780
781void GL1D_RFC_TX_MOD_RESULT_HANDLING( kal_uint32 route_idx,
782 kal_uint32 rfc_rt_idx,
783 kal_uint32 subband_idx,
784 kal_uint32 *tx_drv_ctunemod,
785 bool emiRead_emiWrite);
786
787void GL1D_RFC_TX_DNL_RESULT_HANDLING(kal_bool is_tx_dnl_valid,
788 kal_uint32 route_idx,
789 kal_int16* dnl_cal_result,
790 bool emiRead_emiWrite);
791
792void GL1D_RFC_TX_PGA_BIAS_RESULT_HANDLING(kal_uint32 route_idx,
793 MMRFC_POC_PGA_BIAS_T *tx_pga_bias_data,
794 kal_bool emiRead_emiWrite);
795void GL1D_RFC_GET_DEFAULT_TX_PGA_BIAS(kal_uint32 route_idx,
796 MMRFC_POC_PGA_BIAS_T* p_nominal_val);
797void GL1D_RFC_TX_CoarseDC_RESULT_HANDLING(kal_uint32 route_idx,
798 kal_uint32 tx_pga_slice,
799 kal_uint32 recal,
800 kal_int32 *tx_coarsedc_i,
801 kal_int32 *tx_coarsedc_q,
802 bool emiRead_emiWrite);
803void GL1D_RFC_GET_DEFAULT_TX_LPF(kal_uint32 route_idx,
804 kal_int16* nominal_value);
805
806
807void GL1D_RFC_MRX_PGA_TZA_RESULT_HANDLING(kal_uint32 route_idx,
808 MMRFC_MRX_PGA_TZA_BW_E bw_idx,
809 kal_int16 *mrx_pga_ctune,
810 kal_int16 *mrx_tza_ctune,
811 bool emiRead_emiWrite);
812#if (defined(__MD95__) && defined(L1_SIM) )
813/*TX DFE Compensation API for the Trinity L RF*/
814//TX DFE FIIQ Compensation
815void Gl1d_Rf_Tx_Param_Comp_Fiiq(kal_bool tx_fiiq_comp_en,
816 kal_uint32 tx_route_idx,
817 MMRFC_TX_RAT_CBW_CFG_E cbw_cfg,
818 MML1_TXDFE_TX_IQ_COMP_TAB_T* tx_iq);
819//TX DFE DC Compensation
820void Gl1d_Rf_Tx_Param_Comp_Dc(kal_bool tx_dc_comp_en,
821 kal_bool tx_coarse_dc_comp_en,
822 kal_uint32 tx_route_idx,
823 MMRFC_TX_RAT_CBW_CFG_E cbw_cfg,
824 MML1_TXDFE_TX_DC_COMP_TAB_T* tx_dc,
825 MML1_TXDFE_TX_COARSE_DC_COMP_TAB_T* tx_coarse_dc);
826//TX DFE FDIQ Compensation
827void Gl1d_Rf_Tx_Param_Comp_Fdiq(kal_bool tx_fdiq_comp_en,
828 kal_uint32 tx_route_idx,
829 MMRFC_TX_RAT_CBW_CFG_E cbw_cfg,
830 MML1_TXDFE_FDAD_TAP_E* freq_dep_tap,
831 kal_bool* tx_fdid_bypass,
832 MML1_TXDFE_FDAD_COMP_COEFF_TAB_T* tx_fdiq);
833//TX DFE GA Compensation
834void Gl1d_Rf_Tx_Param_Comp_Ga(kal_bool tx_asym_comp_en,
835 kal_uint32 tx_route_idx,
836 MMRFC_TX_RAT_CBW_CFG_E cbw_cfg,
837 MML1_TXDFE_ASYM_TAP_E* asymm_comp_tap,
838 kal_bool* tx_asym_bypass,
839 MML1_TXDFE_ASYMM_COMP_COEFF_TAB_T* tx_asym);
840
841/*DET DFE Compensation API for the Trinity L RF*/
842//DET DFE FIIQ Compensation
843void Gl1d_Rf_Det_Param_Comp_Fiiq(kal_bool det_fiiq_comp_en,
844 kal_uint32 route_idx,
845 MML1_DETDFE_TIA_GAIN_IDX_E fe_gain,
846 MML1_DET_FIIQ_COMP_T* det_fiiq_comp_params);
847//DET DFE DC Compensation
848void Gl1d_Rf_Det_Param_Comp_Dc(kal_bool det_dc_comp_en,
849 kal_uint32 route_idx,
850 kal_uint32 det_gain_step,
851 RF_COMP_INDEX_E comp_idx,
852 MML1_DET_DC_COMP_T* det_dc_comp_params);
853
854//DET DFE eqlpf Compensation
855void Gl1d_Rf_Det_Param_Comp_eqlpf(kal_bool det_eqlpf_comp_en,
856 kal_uint32 route_idx,
857 MML1_DETDFE_TIA_GAIN_IDX_E fe_gain,
858 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
859 MML1_DET_EQLPF_CFG_T* det_eqlpf_comp_params);
860
861#endif
862void L1D_RFC_Get_TxConfigTable_PerBand( MMRFC_XL1_BAND_NUM_E mmrfc_band,MMRFC_TX_CAL_ROUTE_PER_BAND_CFG_T *tx_route_cfg);
863
864void gsm_rfc_pa_on_ctrl(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, MMRF_PMIC_VPA_NUM_E vpaIdx, kal_uint8 is_txcca);
865void gsm_rfc_pa_off_ctrl(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, MMRF_PMIC_VPA_NUM_E vpaIdx, kal_uint8 is_txcca);
866 #endif
867 #endif
868void L1D_RF_MMPOC_GetTxCfg(MMRFC_XL1_BAND_NUM_E band, MMRFC_TX_ROUTE_CFG_T* tx_cfg);
869/*Write Back result for CDOC */
870void GL1D_RF_CAL_DETCDCOC_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band,
871 kal_uint32 det_coarse_dcoc_cw807,
872 kal_uint32 det_coarse_dcoc_cw808);
873/*Write Back result for LO */
874void GL1D_RF_CAL_TXLO_RESULT_WRITE_BACK(kal_uint32 route_idx,
875 MMRFC_XL1_BAND_NUM_E band,
876 kal_uint32 subband_idx,
877 kal_uint8 ind_sw,
878 kal_uint8 capcal_peak_cap,
879 kal_uint8 in_bias_lpm,
880 kal_uint8 in_bias_hpm);
881/*Write Back result for LPF and RCF */
882void GL1D_RF_CAL_TXRC_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band,
883 MMRFC_LPF_RCF_CAL_TYPE_E lpf_rcf_select,
884 kal_int16 tx_rc_calgo_result);
885
886/*Write Back result for DET DC */
887void GL1D_RF_CAL_DETDC_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band,
888 MMRFC_DET_G_IDX gain_idx,
889 kal_uint32 recal,
890 MMRFC_DET_DC_RESULT_T* tx_det_dc_calgo_result);
891/*Write Back result for Pre-Cap and cap tunning */
892void GL1D_RF_CAL_TXCAP_RESULT_WRITE_BACK(kal_uint32 route_idx,
893 MMRFC_XL1_BAND_NUM_E band,
894 kal_uint32 subband_idx,
895 kal_uint8 pga_ab,
896 kal_bool is_pre_cap_tuning,
897 kal_uint8 CAP_OPT_A,
898 kal_uint8 CAP_OPT_B);
899
900/* Write back results after calibration of TX DC */
901void GL1D_RF_CAL_TXDC_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band,
902 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
903 kal_uint32 pwr_mode,
904 kal_uint32 tx_pga_slice,
905 kal_uint32 recal,
906 MMRFC_TX_IQDC_RESULT_T* tx_iqdc_calgo_result);
907
908void GL1D_RF_CAL_TXFIIQ_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band,
909 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
910 kal_uint32 pwr_mode,
911 kal_uint32 tx_pga_slice,
912 kal_uint32 recal,
913 MMRFC_TX_IQDC_RESULT_T* tx_iqdc_calgo_result);
914
915void GL1D_RF_CAL_TXDNL_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band,
916 kal_uint32 tx_gain_idx,
917 kal_uint8 tx_21a_index,
918 kal_int32 tx_dnl_calgo_result0,
919 kal_int32 tx_dnl_calgo_result1);
920
921void GL1D_RF_CAL_DETIQDNL_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band,
922 MMRFC_DET_TIA_COMP_INDEX_E fe_gain_idx,
923 MMRFC_DET_G_IDX gain_idx,
924 kal_uint32 recal,
925 MMRFC_DET_IQDNL_RESULT_T* tx_det_iqdnl_calgo_result);
926void GL1D_RF_CAL_DETFDPCB_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band,
927 MMRFC_DET_TIA_COMP_INDEX_E fe_gain_idx,
928 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
929 kal_uint32 recal,
930 MMRFC_DET_EQLPF_CFG_T* tx_det_pcb_calgo_result);
931
932
933//DET COMP
934void GL1D_RFC_DET_FIIQ_COMP(kal_uint32 route_idx,
935 MMRFC_DETDFE_TIA_GAIN_IDX_E fe_gain,
936 MMRFC_DET_FIIQ_COMP_T* p);
937
938void GL1D_RFC_DET_DC_COMP(kal_uint32 route_idx, kal_uint32 det_gain_step, MMRFC_DET_DC_COMP_T* p);
939
940void GL1D_RFC_DET_FDPCB_COMP(kal_uint32 route_idx,
941 MMRFC_DETDFE_TIA_GAIN_IDX_E fe_gain,
942 MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx,
943 MMRFC_DET_EQLPF_CFG_T* p);
944
945
946#else/*legacy chips 6176,MT6179*/
947void L1D_RF_TX_PARAM_COMP(RF_COMP_INDEX_E comp_idx, MMRFC_TX_RAT_CBW_CFG_E cbw_cfg, kal_uint8 curr_band_idx, MMRFC_GSM_RESULT_PER_BAND_T* gsm_result_per_band);
948void L1D_RF_GetDetBwConfig(MMRFC_DET_CAL_ITEM_CFG_E detk_item, MMRFC_TX_RAT_CBW_CFG_E* start_cbw, MMRFC_TX_RAT_CBW_CFG_E* end_cbw, kal_uint8* tone_num);
949void L1D_RF_GetTxBwConfig(MMRFC_TX_CAL_ITEM_CFG_E txk_item, MMRFC_TX_RAT_CBW_CFG_E* start_cbw, MMRFC_TX_RAT_CBW_CFG_E* end_cbw);
950void L1D_MMRF_RFCAL_STX_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
951 kal_uint8 band_index,
952 kal_uint8* length,
953 MMRFC_STX_CONFIG_BUFFER_T* buffer);
954void L1D_MMRF_RFCAL_TX_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
955 kal_uint8 band_index,
956 kal_uint8* length,
957 MMRFC_TX_CONFIG_BUFFER_T* buffer);
958void L1D_MMRF_RFCAL_LIN_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
959 kal_uint8 band_index,
960 kal_uint8* length,
961 MMRFC_TX_DRV_BIAS_LIN_CONFIG_BUFFER_T* buffer);
962void L1D_MMRF_RFCAL_DPD_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
963 kal_uint8 band_index,
964 kal_uint8* length,
965 MMRFC_TX_DRV_BIAS_DPD_CONFIG_BUFFER_T* buffer);
966void L1D_MMRF_RFCAL_TX_PA_ON_LOWGAIN_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
967 kal_uint8 band_index,
968 kal_uint8* length,
969 MMRFC_TXPA_ON_LOWGAIN_BUFFER_T* buffer,
970 MML1_RF_BSIMM_PORT_T* port_sel);
971void L1D_MMRF_RFCAL_TX_PA_OFF_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p,
972 kal_uint8 band_index,
973 kal_uint8* length,
974 MMRFC_TXPA_OFF_BUFFER_T* buffer,
975 MML1_RF_BSIMM_PORT_T* port_sel);
976void L1D_RF_MMPOC_GetTxCfg(MMRFC_XL1_BAND_NUM_E band, MMRFC_TX_ROUTE_CFG_T* tx_cfg);
977#endif
978#endif
979#ifdef __TAS_SUPPORT__
980 #if IS_2G_Gen97_UTAS_SUPPORT
981 void L1TST_RF_Force_TAS(kal_bool force_tas_enable, MMRFD_CUSTOM_TAS_STATE_E tas_tx_idx, MMRFD_CUSTOM_TAS_STATE_E tas_rx_idx);
982 void GL1D_Get_META_Default_TAS_State(MMRF_COMMON_BAND_IDX_E band, MML1_COMMON_CAL_ANT_STATE_INFO_T* cal_default_state_pair);
983 kal_uint16 GL1D_Supported_Band_Query(MMRF_COMMON_BAND_IDX_E* band_list);
984 void L1D_Get_TAS_State_From_Custom_NVRAM(FrequencyBand index, MML1_COMMON_CAL_ANT_STATE_INFO_T* cal_default_state_pair); /*This API is based on the request from yungshian*/
985 #elif IS_2G_Gen95_UTAS_SUPPORT
986 kal_bool L1D_RF_TAS_Support(void);
987 void L1D_RF_Force_TAS(kal_bool force_tas_enable, kal_uint8 tas_idx);
988 kal_uint16 L1D_IsQueryingTasStateInfoSupported( void );
989 void L1TST_RF_Force_TAS(kal_bool force_tas_enable, kal_uint8 tas_idx);
990 kal_uint16 L1D_GetTasStateConfigBandList( kal_uint16* band_list );
991 void L1D_GetTasStateConfigByBand(kal_uint16 band, kal_uint16* cal_default_state, kal_uint16* toggled_state_num, kal_uint16* toggled_state_list );
992 kal_uint16 GL1D_Get_Ant_FE_Layout_Group(kal_uint16 band);
993 kal_uint16 GL1D_Get_META_Default_TAS_State(kal_uint16 band);
994 #elif IS_2G_TAS_SUPPORT
995 kal_bool L1D_RF_TAS_Support(void);
996 void L1D_RF_Force_TAS(kal_bool force_tas_enable, kal_uint8 tas_idx);
997 kal_uint16 L1D_IsQueryingTasStateInfoSupported( void );
998 kal_uint16 L1D_QueryTasVersion( void );
999 kal_uint16 L1D_GetTasStateConfigBandNum( void );
1000 void L1D_GetTasStateConfig(kal_uint16 buf_length, kal_uint16* band_list, kal_uint16* state_limit, kal_uint16* tas_state );
1001 #endif
1002#else
1003#define L1D_RF_TAS_Support NULL
1004#define L1D_RF_Force_TAS NULL
1005#define L1TST_RF_Force_TAS NULL
1006#define L1D_IsQueryingTasStateInfoSupported NULL
1007#define L1D_QueryTasVersion NULL
1008#define L1D_GetTasStateConfigBandNum NULL
1009#define L1D_GetTasStateConfig NULL
1010#define L1D_GetTasStateConfigBandList NULL
1011#define L1D_GetTasStateConfigByBand NULL
1012#define GL1D_Get_Ant_FE_Layout_Group NULL
1013#define GL1D_Get_META_Default_TAS_State NULL
1014#define GL1D_Supported_Band_Query NULL
1015#define L1D_Get_TAS_State_From_Custom_NVRAM NULL
1016#endif
1017typedef enum
1018{
1019 GL1D_LTE_DET_CAL = 0,
1020 GL1D_GSM_TX_CAL = 1
1021} GL1D_POC_STATE_E;
1022
1023typedef struct
1024{
1025 kal_uint16 mipi_data_start;
1026 kal_uint16 mipi_data_number;
1027}GL1D_RF_CAL_MIPI_DATA_T;
1028
1029#if IS_RF_MT6176 || IS_RF_MT6179
1030extern kal_uint32* grfcalPocBufferTable [/*MMPOC_BUFFER_TYPE_NUM_OF*/];
1031extern kal_uint32 grfcalPocBufferSizeTable [/*MMPOC_BUFFER_TYPE_NUM_OF*/];
1032extern MML1_RF_BSIMM_PORT_T grfcalPocBufferDataPortSelTable [/*MMPOC_BUFFER_TYPE_NUM_OF*/];
1033extern MML1_MIPI_REG_RW_T grfcalPocBufferDataMipiCwTypeTable[/*MMPOC_BUFFER_TYPE_NUM_OF*/];
1034#endif
1035extern GL1D_RF_CAL_MIPI_DATA_T GSM_MIPI_PA_ON_DATA [/*MMPOC_BUFFER_TYPE_NUM_OF*/];
1036extern GL1D_RF_CAL_MIPI_DATA_T GSM_MIPI_PA_OFF_DATA [/*MMPOC_BUFFER_TYPE_NUM_OF*/];
1037
1038/* provide this API to MMRF, use for calibration download check */
1039kal_uint32 L1D_Return_AFC_DAC_SW_Default_value(void);
1040
1041
1042/*Update 2G TX/RX POC result to 2G global variable */
1043#if IS_CHIP_MT6297_AND_LATTER_VERSION
1044void GL1D_RX_RFCW_COMP_Init(void);
1045void GL1D_TX_RFCW_COMP_Init(void);
1046#else
1047#define GL1D_RX_RFCW_COMP_Init NULL
1048#define GL1D_TX_RFCW_COMP_Init NULL
1049#endif
1050
1051#if IS_CHIP_MT6297_AND_LATTER_VERSION
1052void GL1D_TXDFE_Serdes_Assert(void);
1053#endif
1054
1055
1056// Provide RXDFE cntrl API for MMRFC recal flow
1057#if IS_CHIP_MT6297_AND_LATTER_VERSION
1058void GL1D_RXDFE_Comp_Update(MMRF_COMMON_BAND_IDX_E band, MML1_RXDFE_SW_DC_T *p_sw_dc_val, MMRFC_RX_IRR_COMP_T *p_irr_comp);
1059void GL1D_RXDFE_WIN_ON(kal_uint32 Ontime,MMRF_COMMON_BAND_IDX_E band);
1060void GL1D_RXDFE_WIN_OFF(kal_uint32 Offtime);
1061
1062// Provide to CDF for NVRAM run-time activate
1063void GL1D_CDF_META_RUN_TIME_NVRAM_ACTIVIATE(void);
1064#endif
1065#endif /* End of #ifndef _L1D_MMRF_INTERFACE_H_ */