| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * mmrf_common_cid.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * MT6293 |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * Multi-Mode RF & BB Chip ID & Compile Option |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
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| 295 | *---------------------------------------------------------------------------- |
| 296 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 297 | *============================================================================ |
| 298 | ****************************************************************************/ |
| 299 | |
| 300 | #ifndef _MMRF_COMMON_CID_H_ |
| 301 | #define _MMRF_COMMON_CID_H_ |
| 302 | |
| 303 | /******************************************************************************* |
| 304 | ** Define BB chip in use |
| 305 | *******************************************************************************/ |
| 306 | |
| 307 | /* Divide chips into Series+Number */ |
| 308 | #define MML1_CHIP_SER(ID) (0xFFFFF000&ID) |
| 309 | #define MML1_CHIP_NUM(ID) (0x00000FFF&ID) |
| 310 | |
| 311 | /*---------------------------------------------------*/ |
| 312 | /* Before MML1 RF Central Control : */ |
| 313 | /*---------------------------------------------------*/ |
| 314 | /* After MML1 RF Central Control : */ |
| 315 | /* (1) IS_MML1_CHIP_MT6290 : LTE R9 Modem */ |
| 316 | /* (2) IS_MML1_CHIP_MT6595 : */ |
| 317 | /* (3) IS_MML1_CHIP_MT6752_MD1 : */ |
| 318 | /* (4) IS_MML1_CHIP_MT6752_MD2 : */ |
| 319 | /* (5) IS_MML1_CHIP_TK6291 : LTE-A R10 Modem */ |
| 320 | /* (6) IS_MML1_CHIP_MT6755 : LTE-A Smart Phone */ |
| 321 | /* (7) IS_MML1_CHIP_MT6797 : LTE-A Smart Phone */ |
| 322 | /*---------------------------------------------------*/ |
| 323 | |
| 324 | /*---------------------------------------------*/ |
| 325 | /* For Dual Mode Project (2G/3G) */ |
| 326 | /*---------------------------------------------*/ |
| 327 | |
| 328 | /*---------------------------------------------*/ |
| 329 | /* For MultiMode MultiRAT Project (2G/3G/LTE) */ |
| 330 | /*---------------------------------------------*/ |
| 331 | #define _MML1_CHIP_ID_MT6290 0x00001001 // MT6290 LTE Modem |
| 332 | #define _MML1_CHIP_ID_MT6595 0x00001002 // ROME LTE Smart Phone |
| 333 | #define _MML1_CHIP_ID_MT6752_MD1 0x00001003 // K2 MD1 LTE Smart Phone |
| 334 | #define _MML1_CHIP_ID_MT6752_MD2 0x00001004 // K2 MD2 LTE Smart Phone |
| 335 | #define _MML1_FPGA_ID_TK6291 0x00002000 // TK6291 LTE-A FPGA |
| 336 | #define _MML1_CHIP_ID_TK6291 0x00002001 // TK6291 LTE-A Test Chip |
| 337 | #define _MML1_CHIP_ID_MT6755 0x00002002 // Jade LTE-A Smart Phone |
| 338 | #define _MML1_CHIP_ID_MT6750 0x00002003 // Jade- LTE-A Smart Phone |
| 339 | #define _MML1_CHIP_ID_MT6750S 0x00002004 // Rosa LTE-A Smart Phone |
| 340 | #define _MML1_CHIP_ID_MT6797 0x00002005 // Everest LTE-A Smart Phone |
| 341 | #define _MML1_CHIP_ID_MT6757 0x00002006 // Olympus LTE-A Smart Phone |
| 342 | #define _MML1_CHIP_ID_MT6757P 0x00002007 // Kibo+ LTE-A Smart Phone |
| 343 | #define _MML1_FPGA_ID_MT6292 0x00003000 // Elbrus LTE-A FPGA |
| 344 | #define _MML1_CHIP_ID_MT6292 0x00003001 // Elbrus LTE-A Modem |
| 345 | #define _MML1_CHIP_ID_MT6799 0x00003002 // Whitney LTE-A Smart |
| 346 | #define _MML1_CHIP_ID_MT6799E2 0x00003003 // Whitney E2 LTE-A Smart |
| 347 | #define _MML1_CHIP_ID_MT6759 0x00003004 // Alaska LTE-A Smart |
| 348 | #define _MML1_CHIP_ID_MT6758 0x00003005 // Vinson LTE-A Smart |
| 349 | #define _MML1_FPGA_ID_MT6293 0x00004000 // Bianco LTE-A FPGA |
| 350 | #define _MML1_CHIP_ID_MT6293 0x00004001 // Bianco LTE-A Modem |
| 351 | #define _MML1_CHIP_ID_MT6739 0x00004002 // Zion LTE-A Modem |
| 352 | #define _MML1_CHIP_ID_MT6771 0x00004003 // Sylvia LTE-A Modem |
| 353 | #define _MML1_CHIP_ID_MT6765 0x00004004 // Cervino LTE-A Modem |
| 354 | #define _MML1_CHIP_ID_MT6761 0x00004005 // Merlot LTE-A Modem |
| 355 | #define _MML1_CHIP_ID_MT6295 0x00005000 |
| 356 | #define _MML1_FPGA_ID_MT6295M 0x00005001 // MT6295M LTE-A FPGA |
| 357 | #define _MML1_CHIP_ID_MT6295M 0x00005002 |
| 358 | #define _MML1_CHIP_ID_MT3967 0x00005003 // Eiger LTE-A Modem |
| 359 | #define _MML1_CHIP_ID_MT6779 0x00005004 // Lafite LTE-A Modem |
| 360 | #define _MML1_FPGA_ID_MT6297 0x00006000 // MT6297 LTE-A FPGA |
| 361 | #define _MML1_CHIP_ID_MT6297 0x00006001 // MT6297 LTE-A Modem |
| 362 | #define _MML1_FPGA_ID_MT6885 0x00006002 // MT6885 LTE-A FPGA |
| 363 | #define _MML1_CHIP_ID_MT6885 0x00006003 // MT6885 LTE-A Modem |
| 364 | #define _MML1_CHIP_ID_MT6893 0x00006004 // MT6893 LTE-A Modem |
| 365 | #define _MML1_CHIP_ID_MT6873 0x00006005 // MARGUAX LTE-A Modem |
| 366 | #define _MML1_CHIP_ID_MT6853 0x00006006 // MT6853 LTE-A Modem |
| 367 | #define _MML1_CHIP_ID_MT6880 0x00006007 // MT6880 LTE-A Modem |
| 368 | #define _MML1_CHIP_ID_MT6890 0x00006008 // MT6890 LTE-A Modem |
| 369 | #define _MML1_CHIP_ID_MT2735 0x00006009 // MT2735 LTE-A Modem |
| 370 | #define _MML1_CHIP_ID_MT6833 0x0000600A // MT6833 LTE-A Modem |
| 371 | #define _MML1_CHIP_ID_MT6877 0x0000600B // MT6877 LTE-A Modem |
| 372 | #define _MML1_CHIP_ID_MERCURY 0x00007000 // MERCURY LTE-A Modem |
| 373 | |
| 374 | |
| 375 | /*.......................................................*/ |
| 376 | |
| 377 | #define IS_MML1_CHIP_SER(ID) ( MML1_CHIP_SER(_MML1_CHIP_ID)==MML1_CHIP_SER(ID) ) |
| 378 | #define IS_MML1_CHIP_SER_AND_LATTER(ID) ( MML1_CHIP_NUM(_MML1_CHIP_ID)>=MML1_CHIP_NUM(ID) && IS_MML1_CHIP_SER(ID) ) |
| 379 | #define IS_MML1_CHIP_SER_AND_BEFORE(ID) ( MML1_CHIP_NUM(_MML1_CHIP_ID)<=MML1_CHIP_NUM(ID) && IS_MML1_CHIP_SER(ID) ) |
| 380 | |
| 381 | /*.......................................................*/ |
| 382 | |
| 383 | #define IS_MML1_CHIP_MT6290_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6290) ) |
| 384 | #define IS_MML1_CHIP_TK6291_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_FPGA_ID_TK6291) ) |
| 385 | #define IS_MML1_CHIP_MT6755_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6755) ) |
| 386 | #define IS_MML1_CHIP_MT6797_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6797) ) |
| 387 | #define IS_MML1_CHIP_MT6750_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6750) ) |
| 388 | #define IS_MML1_CHIP_MT6750S_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6750S) ) |
| 389 | #define IS_MML1_CHIP_MT6757_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6757) ) |
| 390 | #define IS_MML1_CHIP_MT6757P_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6757P) ) |
| 391 | #define IS_MML1_CHIP_MT6292_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_FPGA_ID_MT6292) ) |
| 392 | #define IS_MML1_CHIP_MT6799_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6799) ) |
| 393 | #define IS_MML1_CHIP_MT6799E2_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6799E2)) |
| 394 | #define IS_MML1_CHIP_MT6759_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6759) ) |
| 395 | #define IS_MML1_CHIP_MT6758_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6758) ) |
| 396 | #define IS_MML1_CHIP_MT6293_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_FPGA_ID_MT6293) ) |
| 397 | #define IS_MML1_CHIP_MT6739_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6739) ) |
| 398 | #define IS_MML1_CHIP_MT6771_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6771) ) |
| 399 | #define IS_MML1_CHIP_MT6765_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6765) ) |
| 400 | #define IS_MML1_CHIP_MT6761_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6761) ) |
| 401 | #define IS_MML1_CHIP_MT6295_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6295) ) |
| 402 | #define IS_MML1_CHIP_MT3967_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT3967) ) |
| 403 | #define IS_MML1_CHIP_MT6779_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6779) ) |
| 404 | #define IS_MML1_CHIP_MT6297_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_FPGA_ID_MT6297) ) |
| 405 | #define IS_MML1_CHIP_MT6885_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_FPGA_ID_MT6885) ) |
| 406 | #define IS_MML1_CHIP_MT6893_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6893) ) |
| 407 | #define IS_MML1_CHIP_MT6873_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6873) ) |
| 408 | #define IS_MML1_CHIP_MT6853_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6853) ) |
| 409 | #define IS_MML1_CHIP_MT6880_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6880) ) |
| 410 | #define IS_MML1_CHIP_MT6833_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6833) ) |
| 411 | #define IS_MML1_CHIP_MT6877_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6877) ) |
| 412 | #define IS_MML1_CHIP_MERCURY_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MERCURY) ) |
| 413 | |
| 414 | |
| 415 | #define IS_MML1_CHIP_MT6290 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6290 ) |
| 416 | #define IS_MML1_CHIP_MT6595 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6595 ) |
| 417 | #define IS_MML1_CHIP_MT6752_MD1 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6752_MD1 ) |
| 418 | #define IS_MML1_CHIP_MT6752_MD2 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6752_MD2 ) |
| 419 | #define IS_MML1_FPGA_TK6291 ( _MML1_CHIP_ID==_MML1_FPGA_ID_TK6291 ) |
| 420 | #define IS_MML1_CHIP_TK6291 ( ( _MML1_CHIP_ID==_MML1_CHIP_ID_TK6291 )||( _MML1_CHIP_ID==_MML1_FPGA_ID_TK6291 ) ) |
| 421 | #define IS_MML1_CHIP_MT6755 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6755 ) |
| 422 | #define IS_MML1_CHIP_MT6797 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6797 ) |
| 423 | #define IS_MML1_CHIP_MT6750 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6750 ) |
| 424 | #define IS_MML1_CHIP_MT6750S ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6750S ) |
| 425 | #define IS_MML1_CHIP_MT6757 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6757 ) |
| 426 | #define IS_MML1_CHIP_MT6757P ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6757P ) |
| 427 | #define IS_MML1_FPGA_MT6292 ( _MML1_CHIP_ID==_MML1_FPGA_ID_MT6292 ) |
| 428 | #define IS_MML1_CHIP_MT6292 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6292 ) |
| 429 | #define IS_MML1_CHIP_MT6799 ( ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6799 )||( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6799E2 ) ) |
| 430 | #define IS_MML1_CHIP_MT6799E2 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6799E2 ) |
| 431 | #define IS_MML1_CHIP_MT6759 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6759 ) |
| 432 | #define IS_MML1_CHIP_MT6758 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6758 ) |
| 433 | #define IS_MML1_FPGA_MT6293 ( _MML1_CHIP_ID==_MML1_FPGA_ID_MT6293 ) |
| 434 | #define IS_MML1_CHIP_MT6293 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6293 ) |
| 435 | #define IS_MML1_CHIP_MT6739 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6739 ) |
| 436 | #define IS_MML1_CHIP_MT6771 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6771 ) |
| 437 | #define IS_MML1_CHIP_MT6765 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6765 ) |
| 438 | #define IS_MML1_CHIP_MT6761 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6761 ) |
| 439 | #define IS_MML1_CHIP_MT6295 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6295 ) |
| 440 | #define IS_MML1_FPGA_MT6295M ( _MML1_CHIP_ID==_MML1_FPGA_ID_MT6295M ) |
| 441 | #define IS_MML1_CHIP_MT6295M ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6295M ) |
| 442 | #define IS_MML1_CHIP_MT3967 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT3967 ) |
| 443 | #define IS_MML1_CHIP_MT6779 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6779 ) |
| 444 | #define IS_MML1_FPGA_MT6297 ( _MML1_CHIP_ID==_MML1_FPGA_ID_MT6297 ) |
| 445 | #define IS_MML1_CHIP_MT6297 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6297 ) |
| 446 | #define IS_MML1_FPGA_MT6885 ( _MML1_CHIP_ID==_MML1_FPGA_ID_MT6885 ) |
| 447 | #define IS_MML1_CHIP_MT6885 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6885 ) || ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6893 ) |
| 448 | #define IS_MML1_CHIP_MT6893 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6893 ) |
| 449 | #define IS_MML1_CHIP_MERCURY ( _MML1_CHIP_ID==_MML1_CHIP_ID_MERCURY ) |
| 450 | #define IS_MML1_CHIP_MT6873 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6873 ) |
| 451 | #define IS_MML1_CHIP_MT6853 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6853 ) |
| 452 | #define IS_MML1_CHIP_CHIP10992 ( ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6880 )||( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6890 )||( _MML1_CHIP_ID==_MML1_CHIP_ID_MT2735 ) ) |
| 453 | #define IS_MML1_CHIP_MT6880 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6880 ) |
| 454 | #define IS_MML1_CHIP_MT6890 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6890 ) |
| 455 | #define IS_MML1_CHIP_MT2735 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT2735 ) |
| 456 | #define IS_MML1_CHIP_MT6833 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6833 ) |
| 457 | #define IS_MML1_CHIP_MT6877 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6877 ) |
| 458 | |
| 459 | |
| 460 | |
| 461 | |
| 462 | |
| 463 | /*.......................................................*/ |
| 464 | |
| 465 | /* real chip use */ |
| 466 | #ifndef _MML1_CHIP_ID |
| 467 | #if defined(MT6763) |
| 468 | #if defined(__FPGA__) |
| 469 | #define _MML1_CHIP_ID _MML1_FPGA_ID_MT6293 |
| 470 | #elif defined(MT6763_S00) |
| 471 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6293 |
| 472 | #else |
| 473 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6293 |
| 474 | #endif |
| 475 | #elif defined(MT6739) |
| 476 | #if defined(MT6739_S00) |
| 477 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6739 |
| 478 | #else |
| 479 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6739 |
| 480 | #endif |
| 481 | #elif defined(MT6771) |
| 482 | #if defined(MT6771_S00) |
| 483 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6771 |
| 484 | #else |
| 485 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6771 |
| 486 | #endif |
| 487 | #elif defined(MT6765) |
| 488 | #if defined(MT6765_S00) |
| 489 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6765 |
| 490 | #else |
| 491 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6765 |
| 492 | #endif |
| 493 | #elif defined(MT6761) |
| 494 | #if defined(MT6761_S00) |
| 495 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6761 |
| 496 | #else |
| 497 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6761 |
| 498 | #endif |
| 499 | #elif defined(MT6295M) |
| 500 | #if defined(__FPGA__) |
| 501 | #define _MML1_CHIP_ID _MML1_FPGA_ID_MT6295M |
| 502 | #else |
| 503 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6295M |
| 504 | #endif |
| 505 | #elif defined(MT3967) |
| 506 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT3967 |
| 507 | #elif defined(MT6779) |
| 508 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6779 |
| 509 | #elif defined(MT6297) |
| 510 | #if defined(__FPGA__) |
| 511 | #define _MML1_CHIP_ID _MML1_FPGA_ID_MT6297 |
| 512 | #else |
| 513 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6297 |
| 514 | #endif |
| 515 | #elif defined(MT6893) |
| 516 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6893 |
| 517 | #elif defined(MT6885) |
| 518 | #if defined(__FPGA__) |
| 519 | #define _MML1_CHIP_ID _MML1_FPGA_ID_MT6885 |
| 520 | #else |
| 521 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6885 |
| 522 | #endif |
| 523 | #elif defined(MERCURY) |
| 524 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MERCURY |
| 525 | #elif defined(MT6873) |
| 526 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6873 |
| 527 | #elif defined(MT6853) |
| 528 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6853 |
| 529 | #elif defined(MT6880) |
| 530 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6880 |
| 531 | #elif defined(MT6890) |
| 532 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6890 |
| 533 | #elif defined(MT2735) |
| 534 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT2735 |
| 535 | #elif defined(MT6833) |
| 536 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6833 |
| 537 | #elif defined(MT6877) |
| 538 | #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6877 |
| 539 | #else |
| 540 | #define _MML1_CHIP_ID 0 |
| 541 | //#error "please check chip version" |
| 542 | #endif |
| 543 | #else |
| 544 | #error "Unexpected BB Chip was defined" |
| 545 | #endif |
| 546 | /*.......................................................*/ |
| 547 | |
| 548 | /******************************************************************************* |
| 549 | ** Define RF chip in use |
| 550 | *******************************************************************************/ |
| 551 | |
| 552 | #if (defined(COLUMBUS_RF)||defined(MT6190T_RF)) |
| 553 | #define IS_MML1_RF_COLUMBUS (1) |
| 554 | #endif |
| 555 | |
| 556 | #if (defined(COLUMBUSE2_RF)||defined(MT6190_RF)) |
| 557 | #define IS_MML1_RF_COLUMBUSE2 (1) |
| 558 | #endif |
| 559 | |
| 560 | #if defined(MT6190M_RF) |
| 561 | #define IS_MML1_RF_MT6190M (1) |
| 562 | #endif |
| 563 | |
| 564 | #if defined(MT6195_RF) |
| 565 | #define IS_MML1_RF_MT6195 (1) |
| 566 | #endif |
| 567 | |
| 568 | /*.......................................................*/ |
| 569 | |
| 570 | /******************************************************************************* |
| 571 | ** Define PMIC chip in use |
| 572 | *******************************************************************************/ |
| 573 | |
| 574 | /*------------------------------------------*/ |
| 575 | /* Use in MML1 : */ |
| 576 | /* ( 1) MML1_PMIC_ID_MT6325 */ |
| 577 | /* ( 2) MML1_PMIC_ID_MT6351 */ |
| 578 | /* (FF) MML1_PMIC_ID_NONE */ |
| 579 | /*------------------------------------------*/ |
| 580 | |
| 581 | #define MML1_PMIC_ID_MT6325 0x00000001 |
| 582 | #define MML1_PMIC_ID_MT6351 0x00000002 |
| 583 | #define MML1_PMIC_ID_MT6353 0x00000003 |
| 584 | #define MML1_PMIC_ID_MT6335 0x00000004 |
| 585 | #define MML1_PMIC_ID_MT6356 0x00000005 |
| 586 | #define MML1_PMIC_ID_MT6357 0x00000006 |
| 587 | #define MML1_PMIC_ID_MT6358 0x00000007 |
| 588 | #define MML1_PMIC_ID_MT6359 0x00000008 |
| 589 | #define MML1_PMIC_ID_MT6359P 0x00000009 |
| 590 | #define MML1_PMIC_ID_MT6330 0x0000000A |
| 591 | #define MML1_PMIC_ID_NONE 0xFFFFFFFF //for non-MM RF |
| 592 | |
| 593 | /*.......................................................*/ |
| 594 | |
| 595 | #define IS_MML1_PMIC_MT6325 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6325 ) |
| 596 | #define IS_MML1_PMIC_MT6351 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6351 ) |
| 597 | #define IS_MML1_PMIC_MT6353 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6353 ) |
| 598 | #define IS_MML1_PMIC_MT6335 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6335 ) |
| 599 | #define IS_MML1_PMIC_MT6356 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6356 ) |
| 600 | #define IS_MML1_PMIC_MT6357 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6357 ) |
| 601 | #define IS_MML1_PMIC_MT6358 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6358 ) |
| 602 | #define IS_MML1_PMIC_MT6359 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6359 ) |
| 603 | #define IS_MML1_PMIC_MT6359P ( MML1_PMIC_ID==MML1_PMIC_ID_MT6359P ) |
| 604 | #define IS_MML1_PMIC_MT6330 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6330 ) |
| 605 | #define IS_MML1_PMIC_NONE ( MML1_PMIC_ID==MML1_PMIC_ID_NONE ) |
| 606 | |
| 607 | #ifndef MML1_PMIC_ID |
| 608 | #if defined(MT6351) |
| 609 | #define MML1_PMIC_ID MML1_PMIC_ID_MT6351 |
| 610 | #elif defined(MT6325) |
| 611 | #define MML1_PMIC_ID MML1_PMIC_ID_MT6325 |
| 612 | #elif defined(MT6353) |
| 613 | #define MML1_PMIC_ID MML1_PMIC_ID_MT6353 |
| 614 | #elif defined(MT6335) |
| 615 | #define MML1_PMIC_ID MML1_PMIC_ID_MT6335 |
| 616 | #elif defined(MT6356) |
| 617 | #define MML1_PMIC_ID MML1_PMIC_ID_MT6356 |
| 618 | #elif defined(MT6357) |
| 619 | #define MML1_PMIC_ID MML1_PMIC_ID_MT6357 |
| 620 | #elif defined(MT6358) |
| 621 | #define MML1_PMIC_ID MML1_PMIC_ID_MT6358 |
| 622 | #elif defined(MT6359) |
| 623 | #define MML1_PMIC_ID MML1_PMIC_ID_MT6359 |
| 624 | #elif defined(MT6359P) |
| 625 | #define MML1_PMIC_ID MML1_PMIC_ID_MT6359P |
| 626 | #elif defined(MT6330) |
| 627 | #define MML1_PMIC_ID MML1_PMIC_ID_MT6330 |
| 628 | #else |
| 629 | #define MML1_PMIC_ID MML1_PMIC_ID_NONE |
| 630 | #endif |
| 631 | #else |
| 632 | #error "Unexpected PMIC Chip was defined" |
| 633 | #endif //MML1_PMIC_ID |
| 634 | |
| 635 | #define IS_MML1_AMSC_CAL_ENABLE (0) |
| 636 | |
| 637 | #endif /* End of #ifndef _MMRF_COMMON_CID_H_ */ |
| 638 | |