| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | #ifndef KAL_CPUINFO_H |
| 2 | #define KAL_CPUINFO_H |
| 3 | |
| 4 | /******************************************************************************* |
| 5 | * Defines for TC_PRIORITY |
| 6 | *******************************************************************************/ |
| 7 | #if defined(__MD93__) |
| 8 | #define HW_ITC_GRP 3 /* Context takes HW ITC */ |
| 9 | #define HRT_CONTEXT_GRP 2 /* HRT LISR or HISR/task DI on HRT domain */ |
| 10 | #define NORMAL_CONTEXT_GRP 0 /* HISR/task */ |
| 11 | #define IDLE_WAIT_GRP 0 /* Idle task enters WAIT state */ |
| 12 | |
| 13 | #elif defined(__MD95__) |
| 14 | |
| 15 | #define HW_ITC_GRP 3 /* Context takes HW ITC */ |
| 16 | #define HRT_CONTEXT_GRP 2 /* HRT LISR or HISR/task DI on HRT domain */ |
| 17 | #define NORMAL_CONTEXT_GRP 1 /* HISR/task */ |
| 18 | #define IDLE_WAIT_GRP 0 /* Idle task enters WAIT state */ |
| 19 | |
| 20 | #elif defined(__MD97__) || defined(__MD97P__) |
| 21 | /* this setting for MD97P is the same with MD97 */ |
| 22 | #define HRT_RESERVED_GRP 3 /* HRT Issues */ |
| 23 | #define HW_ITC_GRP 2 /* Context takes HW ITC, or Critical HRT LISR */ |
| 24 | #define HRT_CONTEXT_GRP 1 /* HRT LISR, or HISR/task DI on HRT domain */ |
| 25 | #define NORMAL_CONTEXT_GRP 0 /* HISR/task */ |
| 26 | |
| 27 | #else |
| 28 | #warning "unknown MDMCU version" |
| 29 | #endif |
| 30 | |
| 31 | /*user must include "mips_ia_utils.h"*/ |
| 32 | #if defined(__MD95__) || defined(MT6297_IA) |
| 33 | #define KAL_CURRENT_PRIO(current_prio) \ |
| 34 | do{ \ |
| 35 | current_prio = (miu_mfc0(MIU_C0_TCSCHEDULE) & 0x3); \ |
| 36 | }while(0); |
| 37 | #elif defined(__MD97__) || defined(__MD97P__) |
| 38 | #define KAL_CURRENT_PRIO(current_prio) \ |
| 39 | do{ \ |
| 40 | current_prio = ((miu_mfc0(MIU_C0_TCSCHEDULE)>>MIU_C0_TCSCHEDULE_PRIO_BITFIELD_BEG) & 0x3); \ |
| 41 | }while(0); |
| 42 | #endif |
| 43 | |
| 44 | #define KAL_HRT_RAISE_PRIO() \ |
| 45 | do { \ |
| 46 | miu_save_and_set_c0_tcschedule_grp(HRT_CONTEXT_GRP); \ |
| 47 | } while (0); |
| 48 | |
| 49 | |
| 50 | #define KAL_ITC_RAISE_PRIO(old_prio) \ |
| 51 | do { \ |
| 52 | old_prio = miu_save_and_set_c0_tcschedule_grp(HW_ITC_GRP); \ |
| 53 | } while (0); |
| 54 | |
| 55 | |
| 56 | /* TCschedule trottle setting is binding with Task/HISR, independent with VPE it running */ |
| 57 | #define KAL_RESTORE_PRIO(prio) \ |
| 58 | do { \ |
| 59 | miu_save_and_set_c0_tcschedule_grp(prio); \ |
| 60 | } while (0); |
| 61 | |
| 62 | /*user must include "intrCtrl.h"*/ |
| 63 | #define LISR_RAISE_TC_PRIO(IRQ_prio) \ |
| 64 | do { \ |
| 65 | if (IRQ_prio < IRQ_NORMAL_DOMAIN_HRT_PRIORITY_THRESHOLD) { \ |
| 66 | miu_set_c0_tcschedule2(MIU_DEF_HRT_DOM_THROT_VAL, HRT_CONTEXT_GRP); \ |
| 67 | } \ |
| 68 | } while (0); |
| 69 | |
| 70 | /* Set TC's priority according to current VPE's domain */ |
| 71 | #if (defined __MD97__ || defined __MD97P__) && !defined MT6297_IA |
| 72 | #define KAL_SET_DEFAULT_TC_PRIO() \ |
| 73 | do { \ |
| 74 | register miu_reg32_t tc_priority; \ |
| 75 | tc_priority = miu_mfc0("$31,5"); \ |
| 76 | miu_mtc0(MIU_C0_TCSCHEDULE, \ |
| 77 | tc_priority << MIU_C0_TCSCHEDULE_PRIO_BITFIELD_BEG); \ |
| 78 | } while (0); |
| 79 | #else |
| 80 | #define KAL_SET_DEFAULT_TC_PRIO() |
| 81 | #endif /* defined __MD97__ && !defined MT6297_IA */ |
| 82 | |
| 83 | #endif |