mcu/service/mertos/include/mer_kernel.h

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/*****************************************************************************
*
* Filename:
* ---------
*   mer_kernel.h
*
* Project:
* --------
*   MERTOS
*
* Description:
* ------------
*   Declare kernel related structure and API.
*
* Author:
* -------
 * -------
*
*****************************************************************************/
#ifndef _MER_KERNEL_H_
#define _MER_KERNEL_H_

#include "mer_kernel_config_public.h"
#include "mer_service_types.h"
#include "mer_config_public.h"

#include "mips_ia_utils_public.h"

///////////////////////////////////////////////////////////////////////////////
// Macro
///////////////////////////////////////////////////////////////////////////////
#define MER_KERNEL_SYSTEM_STACK_SIZE   (8192)
#define MER_KERNEL_ORIGIN_JOB           0x0
#define MER_KERNEL_JOB_SWITCHED         0x1
#define MER_KERNEL_OS_INTERRUPT         0x2

/* For iA, according to ABI, stack should at least align 8 byte */
/* For shaolin, according to ABI, stack should at least align 16 byte */
/* For watchpoint, the minimal protection interval should be at least 32 byte */
/* So we use the L.C.M: 32 */
#define MER_KERNEL_STACK_ALIGN          32

#if !defined(__MER_CONFIG_ENABLE__)
#error "must include mer_config_public.h"
#endif /* __MER_CONFIG_ENABLE__ */

#if defined(__MER_CONFIG_USE_SYSTEM_STACK_IN_INIT__)
#define mer_kernel_system_stack_vpe0    SYS_Stack_Pool_CORE0_VPE0_TC0 
#define mer_kernel_system_stack_vpe1    SYS_Stack_Pool_CORE0_VPE1_TC2
#define mer_kernel_system_stack_vpe2    SYS_Stack_Pool_CORE0_VPE2_TC4
#define mer_kernel_system_stack_vpe3    SYS_Stack_Pool_CORE1_VPE0_TC0
#define mer_kernel_system_stack_vpe4    SYS_Stack_Pool_CORE1_VPE1_TC2
#define mer_kernel_system_stack_vpe5    SYS_Stack_Pool_CORE1_VPE2_TC4
#define mer_kernel_system_stack_vpe6    SYS_Stack_Pool_CORE2_VPE0_TC0
#define mer_kernel_system_stack_vpe7    SYS_Stack_Pool_CORE2_VPE1_TC2
#define mer_kernel_system_stack_vpe8    SYS_Stack_Pool_CORE2_VPE2_TC4
#define mer_kernel_system_stack_vpe9    SYS_Stack_Pool_CORE3_VPE0_TC0
#define mer_kernel_system_stack_vpe10   SYS_Stack_Pool_CORE3_VPE1_TC2
#define mer_kernel_system_stack_vpe11   SYS_Stack_Pool_CORE3_VPE2_TC4
#endif



/* The threshold (in micro second) that a preempted task or dpc being migrated to other VPE */
//#define MER_KERNEL_JOB_MIGRATION_THRESHOLD  200
#define MER_KERNEL_JOB_MIGRATION_THRESHOLD 0xFFFFFFFF

#if defined(__MER_KERNEL_USE_MIPS_CP0_CONTEXT_REG__)

    #define MER_KERNEL_GET_INTERRUPT_COUNT_ASM(reg) \
        mfc0    reg, $4, 2
    
    #define MER_KERNEL_GET_INTERRUPT_COUNT() \
        (miu_mfc0(MIU_C0_USERLOCAL))
    
    #define MER_KERNEL_SET_INTERRUPT_COUNT(value) \
        do {\
            miu_mtc0(MIU_C0_USERLOCAL, (value));\
        }while(0)
    
    #define MER_KERNEL_GET_CURRENT_CONTROL_BLOCK() \
        (miu_mfc0(MIU_C0_TCCONTEXT))

    #define MER_KERNEL_SET_CURRENT_CONTROL_BLOCK(value) \
        miu_mtc0(MIU_C0_TCCONTEXT, (value))

#endif

#if !MER_KERNEL_IS_ASSEMBLY
///////////////////////////////////////////////////////////////////////////////
// Macro
///////////////////////////////////////////////////////////////////////////////
#if defined(__MD97__) || defined(__MD97P__)
    #define MER_KERNEL_OS_INTERRUPT_SW_CODE_BASE SW_TRIGGER_CODE53
#else
    #error "Unsupport platform"
#endif


///////////////////////////////////////////////////////////////////////////////
// Porting variable
///////////////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////////////
// Enum
/////////////////////////////////////////////////////////////////////////////// 


///////////////////////////////////////////////////////////////////////////////
// Structure
///////////////////////////////////////////////////////////////////////////////

typedef struct isr_info {
    mer_uint32 start_time;
    mer_uint32 preempted_time;
    struct isr_info *previous_ptr;
} mer_kernel_isr_info;

///////////////////////////////////////////////////////////////////////////////
// External variable
///////////////////////////////////////////////////////////////////////////////
extern mer_uint32 mer_kernel_initialize_flag;
extern volatile mer_uint32 mer_kernel_os_interrupt_pending_mask;
extern mer_uint32 mer_kernel_interrupt_count[MIPS_HW_VPE_NUM];

extern mer_uint32 mer_kernel_system_stack_vpe0[]; 
extern mer_uint32 mer_kernel_system_stack_vpe1[];
extern mer_uint32 mer_kernel_system_stack_vpe2[];
extern mer_uint32 mer_kernel_system_stack_vpe3[];
extern mer_uint32 mer_kernel_system_stack_vpe4[]; 
extern mer_uint32 mer_kernel_system_stack_vpe5[];
extern mer_uint32 mer_kernel_system_stack_vpe6[]; 
extern mer_uint32 mer_kernel_system_stack_vpe7[]; 
extern mer_uint32 mer_kernel_system_stack_vpe8[]; 
extern mer_uint32 mer_kernel_system_stack_vpe9[]; 
extern mer_uint32 mer_kernel_system_stack_vpe10[];
extern mer_uint32 mer_kernel_system_stack_vpe11[];
///////////////////////////////////////////////////////////////////////////////
// External functions
///////////////////////////////////////////////////////////////////////////////
extern void mer_kernel_initialization();
extern void mer_kernel_isr_job_management(mer_uint32 isr_index, mer_uint32 vpe_id);
extern void mer_kernel_isr_job_management_end(mer_uint32 isr_index, mer_uint32 vpe_id);
extern void mer_kernel_enter_scheduling();
extern void mer_kernel_initialization_phase0();
extern void mer_kernel_osipi_handler();
///////////////////////////////////////////////////////////////////////////////
// static inline functions
///////////////////////////////////////////////////////////////////////////////
static inline mer_uint32 mer_kernel_is_initialized(){
    return mer_kernel_initialize_flag;
}

#include "kal_hrt_api.h"
#include "ex_public.h"
static inline mer_uint32 mer_kernel_is_interrupt_enabled()
{
    mer_uint32 ibit;
    mer_bool is_in_mt = kal_hrt_if_lisr_mt();
    mer_bool is_in_init = kal_query_systemInit();
    mer_bool is_in_exception = INT_QueryExceptionStatus();
    
    do { 
        __asm__ __volatile__("" : 
                                : 
                                : "memory");
    }while(0);

    __asm__ __volatile__("mfc0 %0, $12\n\t"
                         "andi %0, 0x1\n\t"
                         : "=d"(ibit));

    return is_in_mt || is_in_init || is_in_exception || ibit;
}

#if !defined(__MER_KERNEL_USE_MIPS_CP0_CONTEXT_REG__)
mer_uint32 mer_kernel_interrupt_count[MIPS_HW_VPE_NUM];
#endif

static inline mer_uint32 mer_kernel_get_interrupt_count()
{
#if defined(__MER_KERNEL_USE_MIPS_CP0_CONTEXT_REG__)
    mer_uint32 irq_count = MER_KERNEL_GET_INTERRUPT_COUNT();
#else
    mer_uint32 irq_count = mer_kernel_interrupt_count[mer_kernel_utility_get_current_vpe_id()];
#endif

    return irq_count;
}

static inline void mer_kernel_set_interrupt_count(mer_uint32 irq_count)
{
#if defined(__MER_KERNEL_USE_MIPS_CP0_CONTEXT_REG__)
    MER_KERNEL_SET_INTERRUPT_COUNT(irq_count);
#else
    mer_kernel_interrupt_count[mer_kernel_utility_get_current_vpe_id()] = irq_count;
#endif /* __MER_KERNEL_USE_MIPS_CP0_CONTEXT_REG__ */
}

#endif /* MER_KERNEL_IS_ASSEMBLY */
#endif /* _MER_KERNEL_H_ */