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192.168.1.100 / T800_MD / 1eb8f53f94c145708b5ea2c6b9b96ea3d613f607 / . / mcu / service / mertos / include / mer_kernel_dpc.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
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34*****************************************************************************/
35
36/*****************************************************************************
37*
38* Filename:
39* ---------
40* mer_kernel_dpc.h
41*
42* Project:
43* --------
44* MERTOS
45*
46* Description:
47* ------------
48* The DPC header
49*
50* Author:
51* -------
52 * -------
53*
54*****************************************************************************/
55#ifndef _MER_KERNEL_DPC_H_
56#define _MER_KERNEL_DPC_H_
57
58#include "mer_service_types.h"
59#include "mer_service_task.h"
60#include "mer_kernel_utility.h"
61#include "mer_kernel_config_public.h"
62#include "mer_kernel_scheduler.h"
63#include "mer_kernel_switch_target.h"
64#include "mer_config_public.h"
65#include <stddef.h>
66
67
68///////////////////////////////////////////////////////////////////////////////
69// Porting variable
70///////////////////////////////////////////////////////////////////////////////
71typedef mer_service_dpc_cb mer_kernel_dpc_cb;
72
73extern mer_kernel_dpc_cb mer_kernel_dpc_info_table[];
74
75extern const mer_uint32 mer_kernel_dpc_num;
76extern const mer_uint32 mer_kernel_dpc_priority_num;
77extern const mer_uint32 mer_kernel_dpc_priority_mask_num;
78///////////////////////////////////////////////////////////////////////////////
79// Compile time assertion check
80///////////////////////////////////////////////////////////////////////////////
81
82/* Make sure the sp is the first element in the control block */
83MER_CASSERT(offsetof(mer_kernel_dpc_cb, stack_ptr) == 0);
84
85#if defined(__MD97__) || defined(__MD97P__)
86#include "mer_kernel_switch_target_shaolin.inc"
87MER_CASSERT(offsetof(mer_kernel_dpc_cb, last_execution_vpe) == MER_KERNEL_SWITCH_LAST_EXE_VPE_OFFSET);
88#endif /* defined(__MD97__) || defined(__MD97P__) */
89
90
91///////////////////////////////////////////////////////////////////////////////
92// Macro
93///////////////////////////////////////////////////////////////////////////////
94#define MER_KERNEL_DPC_LEVEL_BIT (30)
95#define MER_KERNEL_DPC_LEVEL_MASK (1 << MER_KERNEL_DPC_LEVEL_BIT)
96#define MER_KERNEL_DPC_NUM (mer_kernel_dpc_num)
97//#define MER_KERNEL_DPC_MASK_NUM ((MER_KERNEL_DPC_NUM / 32) + (MER_KERNEL_DPC_NUM % 32 != 0))
98#define MER_KERNEL_DPC_PRIORITY_NUM (mer_kernel_dpc_priority_num)
99#define MER_KERNEL_DPC_PRIORITY_MASK_NUM (mer_kernel_dpc_priority_mask_num)
100#define MER_KERNEL_DPC_APPEND_PRIORITY(dpc_id) ((1 << MER_KERNEL_DPC_LEVEL_BIT) | (dpc_id))
101
102///////////////////////////////////////////////////////////////////////////////
103// Typedef
104///////////////////////////////////////////////////////////////////////////////
105typedef struct {
106 mer_uint32 *mask;
107} mer_kernel_dpc_mask;
108
109typedef struct {
110 mer_uint8 head;
111 mer_uint8 tail;
112} mer_kernel_dpc_list;
113
114typedef mer_uint8 mer_kernel_dpc_id;
115
116///////////////////////////////////////////////////////////////////////////////
117// Enum
118///////////////////////////////////////////////////////////////////////////////
119
120///////////////////////////////////////////////////////////////////////////////
121// Structure
122///////////////////////////////////////////////////////////////////////////////
123
124extern mer_kernel_dpc_mask mer_kernel_dpc_pending_mask[];
125extern mer_kernel_dpc_list mer_kernel_dpc_priority_list[][MIPS_HW_VPE_NUM];
126
127extern mer_uint32 mer_kernel_dpc_info_table_begin;
128extern mer_uint32 mer_kernel_dpc_info_table_end;
129
130///////////////////////////////////////////////////////////////////////////////
131// External Function
132///////////////////////////////////////////////////////////////////////////////
133void mer_kernel_dpc_remove(mer_uint32 dpc_id);
134void mer_kernel_dpc_insert(mer_uint32 dpc_id);
135void mer_kernel_dpc_insert_to_head(mer_uint32 dpc_id);
136void mer_kernel_dpc_set_running_state(mer_uint32 dpc_id);
137void mer_kernel_dpc_initialization();
138void mer_kernel_dpc_invoke(mer_uint32 dpc_id);
139void mer_kernel_dpc_invoke_in_hrt_isr(mer_uint32 dpc_id);
140void mer_kernel_dpc_change_current_affinity(mer_uint32 affinity_mask);
141void mer_kernel_dpc_set_affinity_to_current_vpe();
142
143#if defined(__MER_CONFIG_USE_DYNAMIC_ALLOCATION__)
144void mer_kernel_dpc_stack_allocation();
145#endif /* __MER_CONFIG_USE_DYNAMIC_ALLOCATION__ */
146
147/**
148 * Return the dpc index with cb pointer
149 *
150 *
151 * Time complexity O(1)
152 *
153 * @param[out] Index of input cb pointer
154 * @param[in] The dpc pointer
155 *
156 */
157static inline mer_uint32 mer_kernel_dpc_get_index(mer_kernel_dpc_cb *cb){
158
159 //return (mer_uint32)(cb - mer_kernel_dpc_info_table);
160 return (mer_uint32)cb->job_index;
161}
162
163/**
164 * Return the current running dpc index
165 * Note that this function assume the schedule lock is taken
166 *
167 * Unless __MER_KERNEL_USE_MIPS_CP0_CONTEXT_REG__ is defined
168 *
169 * Time complexity O(1)
170 *
171 * @param[out] The current dpc id
172 * @param[in] vpe_id
173 *
174 */
175__attribute__((always_inline)) static inline mer_uint32 mer_kernel_dpc_get_current_index(){
176
177#if defined(__MER_KERNEL_USE_MIPS_CP0_CONTEXT_REG__)
178 mer_kernel_dpc_cb *cb = (mer_kernel_dpc_cb *)(MER_KERNEL_GET_CURRENT_CONTROL_BLOCK());
179 return mer_kernel_dpc_get_index(cb);
180#else
181 mer_uint32 current_vpe = mer_kernel_utility_get_current_vpe_id();
182 return mer_kernel_scheduler_running_job[current_vpe].job_index;
183#endif /* __MER_KERNEL_USE_MIPS_CP0_CONTEXT_REG__ */
184}
185
186
187
188#endif /* _MER_KERNEL_DPC_H_ */
189