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rjw6c1fd8f2022-11-30 14:33:01 +08001#ifndef DSP_CIPHER_H
2#define DSP_CIPHER_H
3
4#include "kal_public_api.h"
5#include "sync_data.h"
6#include "reg_base.h"
7#define DSP_CIPHER_REG(ptr) (*(volatile kal_uint32*)(ptr))
8#define CIPHER_MAGIC 0xABCDABCD
9
10#if defined(MT6763)|| defined(MT6739) || defined(MT6771) || defined(MT6295M) || defined(MT6765) || defined(MT6761) || defined(MT3967) || defined(MT6779) || defined(MT6297) || defined(MT6885) || defined(MT6873) ||defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877) || defined(__MD97P__)
11 //rake - DE: Ethan Qian (Petrus_rakesys_global_con), shijie wu
12 #define MD32_RAKE_GLOBAL_CON BASE_MADDR_RAKESYS_GLOBAL_CON
13 #define MD32_RAKE_PM_CRC (0x50)
14 #define MD32_RAKE_DM_CRC (0x54)
15
16 #if defined(MT6763)|| defined(MT6739) || defined(MT6771) || defined(MT6295M) || defined(MT6765) || defined(MT6761) || defined(MT3967) || defined(MT6779)
17 #define MD32_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
18 #define SCQ_GLOBAL_CON_base BASE_MADDR_BRAM_SCQ_GLOBAL_CON
19 #elif defined(MT6297) || defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877) || defined(__MD97P__)
20 // AOCR - DE: Vincent Hu (MT6297_mdrxao_config), mercury: matthew yin
21 #define MD32_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG
22
23 // scq16 - DE: Playpony (MT6297_md32scq_global_con), mercury: PJ HSU
24 #define SCQ_GLOBAL_CON_base BASE_MADDR_INR0_SCQ_GLOBAL_CON
25
26 // sonic-mCore - Alex Tang
27 #if defined(MT6297)
28 #define MCORE_AO_CR_base BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR
29 #elif defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
30 #define MCORE_AO_CR_base BASE_MADDR_MODEML1_AO_U_MCORE_PAR_AO_CR
31 #endif
32
33 // sonic-vCore
34 #define VCORE_AO_CR_base BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_CR
35
36 // sonic
37 #define MCORE_CIPHER_CFG 0x0
38 #define MCORE_CIPHER_LOCK_CFG 0x4
39 #define VCORE_CIPHER_CFG 0x58
40 #define VCORE_CIPHER_LOCK_CFG 0x5C
41 #define CIPHER_KEY_SEL_OFFSET 0x4
42 #define CIPHER_EN_MASK 0x1
43 #else
44 #error "need to define address for new chip"
45 #endif
46
47 // scq16 - DE: Playpony (MT6297_md32scq_global_con), mercury: PJ HSU
48 #define SCQ_PM_CRC32_OFFSET 0x20
49 #define SCQ_DM_CRC32_OFFSET 0x24
50 // AOCR - DE: Vincent Hu (MT6297_mdrxao_config), mercury: matthew yin
51 #define MD32_RAKE_PM_CIPHER_EN 0xB0
52 #define MD32_RAKE_PM_CIPHER_LOCK 0xB4
53 #define MD32_SCQ_PM_CIPHER_EN 0xC0
54 #define MD32_SCQ_PM_CIPHER_LOCK 0xC4
55
56#else
57 #error "need to define address for new chip"
58#endif
59
60
61// rake
62extern void set_rake_pm_checksum(kal_uint32 pm_chksum);
63extern void set_rake_dm_checksum(kal_uint32 dm_chksum);
64extern kal_uint32 get_rake_pm_checksum();
65extern kal_uint32 get_rake_dm_checksum();
66extern void set_rake_cipher_en();
67extern void set_rake_cipher_lock();
68extern kal_uint32 get_rake_cipher_en();
69extern kal_uint32 get_rake_cipher_lock();
70extern void rake_cipher_en_check();
71
72// scq16
73extern void set_scq16_pm_checksum(kal_uint32 pm_chksum);
74extern void set_scq16_dm_checksum(kal_uint32 dm_chksum);
75extern kal_uint32 get_scq16_pm_checksum();
76extern kal_uint32 get_scq16_dm_checksum();
77extern void set_scq16_cipher_en();
78extern void set_scq16_cipher_lock();
79extern kal_uint32 get_scq16_cipher_en();
80extern kal_uint32 get_scq16_cipher_lock();
81extern void scq16_cipher_en_check();
82
83// sonic
84extern void set_mcore_cipher_en(kal_uint32 en_val, kal_uint32 key_sel);
85extern void set_mcore_cipher_lock();
86extern kal_uint32 get_mcore_cipher_en();
87extern kal_uint32 get_mcore_cipher_key();
88extern void set_vcore_cipher_en(kal_uint32 en_val, kal_uint32 key_sel);
89extern void set_vcore_cipher_lock();
90extern kal_uint32 get_vcore_cipher_en();
91extern kal_uint32 get_vcore_cipher_key();
92
93#endif /* DSP_CIPHER_H */