blob: 10ba279c3c2afcedea5d9bb4d8ed68df81e53bde [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +08001/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * mddbg.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * Modem debugging related implementation
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
59 * removed!
60 * removed!
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64 * removed!
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67 * removed!
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87 *
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89 * removed!
90 * removed!
91 *
92 *------------------------------------------------------------------------------
93 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
94 *============================================================================
95 ****************************************************************************/
96#ifndef __SST_MDDBG__
97#define __SST_MDDBG__
98
99#include "mddbg_public.h"
100
101#if !defined(DISABLE_MDDBG_FUNCTION)
102#include "kal_public_api.h"
103#include "ex_item.h"
104#endif
105
106
107#if defined(__MIPS_IA__) || defined(__MIPS_I7200__)
108#if defined(__MD93__)
109#define IRQ_MDDBG_CODE IRQ_SW_LISR22_CODE
110#endif
111#if defined(__MD95__)|| defined(__MD97__)|| defined(__MD97P__)
112#define IRQ_MDDBG_CODE IRQ_SW_LISR27_CODE
113#endif
114#endif
115
116#define MAX_CONFIG_VPE_NUM CONFIG_MAX_VPE
117
118#if defined(___MIPS_IA__) || defined(__MD95__)
119 #define MAX_BP_NUM 2
120 #define MAX_WP_NUM 1
121#elif defined(__MIPS_I7200__) || defined(__MD97__)|| defined(__MD97P__)
122 #define MAX_BP_NUM 4
123 #define MAX_WP_NUM 3
124#else
125 #error "incompatible architecture"
126#endif
127
128#if !defined(DISABLE_MDDBG_FUNCTION)
129/* MDDBG Flags */
130#define MDDBG_CTRL_BY_ICE (1UL<< 0)
131#define MDDBG_CTRL_BY_TARGET (1UL<< 1)
132#define MDDBG_CTRL_INIT_VAL (1UL<<30)
133#define MDDBG_MODE_M2H (1UL<<29)
134#define MDDBG_MODE_COND_CHECK (1UL<<28)
135#define MDDBG_MODE_LOG_ONLY (1UL<<27)
136#define MDDBG_MODE_TASK_INIT_SET (1UL<<26)
137
138
139enum mddbg_def_db{
140 MDDBG_VAR_COUNT=16U,
141 MDDBG_CONDITION_BUFFER=128U,
142 MDDBG_BP_MASK_OFFSET=0U,
143 MDDBG_WP_MASK_OFFSET=8U,
144 /* ILM Comands, bit15-0 are reserved for BP/WP */
145 MDDBG_CMD_SETBP = 1U<<31,
146 MDDBG_CMD_SETWP = 1U<<30,
147 MDDBG_CMD_REMOVEBP = 1U<<29,
148 MDDBG_CMD_REMOVEWP = 1U<<28,
149 MDDBG_CMD_MONITOR = 1U<<27,
150 MDDBG_CMD_M2H = 1U<<26,
151 MDDBG_CMD_LOG = 1U<<25, /* Output log, the MONITOR must be 1 */
152 MDDBG_CMD_QUERY = 1U<<24, /* Query Status */
153#if defined(__MIPS_I7200__)
154 MDDBG_CMD_VERSION = 1,
155#endif
156 CHIP_BP_CNT=MAX_BP_NUM,
157 CHIP_WP_CNT=MAX_WP_NUM,
158#if defined(__MIPS_I7200__)
159 MDDBG_CORES_PER_MODULE = 3,
160#endif
161 CHIP_CORE_CNT = CONFIG_MAX_VPE, /*VPE Num*/
162
163};
164
165
166typedef struct mddbg_req{
167 kal_uint8 ref_count;
168 kal_uint16 msg_len;
169 kal_uint32 cmd; //setting flags, which kinds of parameter is enabled, enable/disable/query
170 kal_uint32 proc_idx;
171 kal_uint32 bpAddr[CHIP_BP_CNT];
172 kal_uint32 bpMask[CHIP_BP_CNT];
173 kal_uint32 wpAddr[CHIP_WP_CNT];
174 kal_uint32 wpMask[CHIP_WP_CNT];
175 kal_uint32 wpType[CHIP_WP_CNT];
176 kal_uint32 var[MDDBG_VAR_COUNT];
177}mddbg_req_struct;
178
179typedef struct mddbg_response{
180 kal_uint8 ref_count;
181 kal_uint16 msg_len;
182 kal_uint32 cmd; //setting flags, which kinds of parameter is enabled, enable/disable/query
183 kal_uint32 proc_idx;
184 kal_uint32 bpAddr[CHIP_BP_CNT];
185 kal_uint32 bpMask[CHIP_BP_CNT];
186 kal_uint32 wpAddr[CHIP_WP_CNT];
187 kal_uint32 wpMask[CHIP_WP_CNT];
188 kal_uint32 wpType[CHIP_WP_CNT];
189 kal_uint32 var[MDDBG_VAR_COUNT];
190}mddbg_response_struct;
191
192extern void mddbg_backup(void);
193extern void mddbg_restore(void);
194extern void mddbg_init(void);
195
196#endif /* !DISABLE_MDDBG_FUNCTION */
197
198typedef struct mddbg_bp_config_t{
199 kal_uint32 addr;
200 kal_uint32 addr_mask;
201 kal_uint32 return_addr;
202}mddbg_bp_config_t;
203
204typedef struct mddbg_wp_config_t{
205 kal_uint32 addr;
206 kal_uint32 addr_mask;
207 kal_uint32 type;
208 kal_uint32 return_addr;
209}mddbg_wp_config_t;
210
211
212void mddbg_isr_lisr(void);
213
214
215#endif /* __SST_MDDBG__ */
216